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Fix the coding style and typo issue

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Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
anjiahao 2022-09-06 14:18:45 +08:00 committed by Masayuki Ishikawa
parent d07792a343
commit a4563b8744
148 changed files with 1747 additions and 1744 deletions
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2
arch/arm/src/cxd56xx/cxd56_adc.c
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@ -173,7 +173,7 @@ struct cxd56adc_dev_s
uint8_t fifomode; /* fifo mode */
struct scufifo_wm_s *wm; /* water mark */
struct math_filter_s *filter; /* math filter */
struct scuev_notify_s * notify; /* notify */
struct scuev_notify_s *notify; /* notify */
mutex_t lock; /* exclusive mutex */
int crefs; /* reference count */
};

17
arch/arm/src/cxd56xx/cxd56_dmac.c
View File

@ -292,6 +292,10 @@ struct dma_channel_s
static struct dma_channel_s g_dmach[NCHANNELS];
static mutex_t g_dmalock = NXMUTEX_INITIALIZER;
/****************************************************************************
* Private Functions
****************************************************************************/
static int dma_init(int ch);
static int dma_uninit(int ch);
static int dma_open(int ch);
@ -328,6 +332,7 @@ static struct dmac_register_map *get_device(int ch)
case 2: return (struct dmac_register_map *)DMAC2_REG_BASE;
case 3: return (struct dmac_register_map *)DMAC3_REG_BASE;
}
return NULL;
}
@ -335,15 +340,17 @@ static struct dmac_ch_register_map *get_channel(int ch)
{
struct dmac_register_map *dev = get_device(ch);
if (dev == NULL)
return NULL;
{
return NULL;
}
if (is_dmac(2, dev))
{
return &dev->channel[ch - 7];
return &dev->channel[ch - 7];
}
else if (is_dmac(3, dev))
{
return &((struct dmac080_register_map *)dev)->channel[ch - 2];
return &((struct dmac080_register_map *)dev)->channel[ch - 2];
}
return &dev->channel[ch & 1];
@ -397,12 +404,12 @@ static void _dmac_intc_handler(int ch)
if (is_dmac(2, dev))
{
mask = 1u << (ch - 7);
mask = 1u << (ch - 7);
}
else if (is_dmac(3, dev))
{
mask = 1u << (ch - 2);
mask = 1u << (ch - 2);
}
itc = dev->inttcstatus & mask;

6
arch/arm/src/cxd56xx/cxd56_emmc.c
View File

@ -271,7 +271,7 @@ static struct emmc_dma_desc_s *emmc_setupdma(void *buf, unsigned int nbytes)
int i;
int ndescs;
struct emmc_dma_desc_s *descs;
struct emmc_dma_desc_s *d;
struct emmc_dma_desc_s *d;
uint32_t addr;
uint32_t size;
unsigned int remain;
@ -935,13 +935,11 @@ static int cxd56_emmc_geometry(struct inode *inode,
int cxd56_emmcinitialize(void)
{
struct cxd56_emmc_state_s *priv;
struct cxd56_emmc_state_s *priv = &g_emmcdev;
uint8_t *buf;
struct emmc_dma_desc_s *descs;
int ret;
priv = &g_emmcdev;
ret = emmc_hwinitialize();
if (ret != OK)
{

4
arch/arm/src/cxd56xx/cxd56_geofence.c
View File

@ -399,7 +399,7 @@ static int cxd56_geofence_get_all_status(unsigned long arg)
static int cxd56_geofence_set_mode(unsigned long arg)
{
int ret;
int ret;
struct cxd56_geofence_mode_s *mode;
if (!arg)
@ -550,7 +550,7 @@ static int cxd56_geofence_poll(struct file *filep,
struct pollfd *fds,
bool setup)
{
struct inode * inode;
struct inode *inode;
struct cxd56_geofence_dev_s *priv;
int ret = OK;
int i;

12
arch/arm/src/cxd56xx/cxd56_gnss.c
View File

@ -161,7 +161,7 @@ struct cxd56_gnss_dev_s
uint8_t num_open;
uint8_t notify_data;
struct file cepfp;
void * cepbuf;
void *cepbuf;
struct pollfd *fds[CONFIG_CXD56_GNSS_NPOLLWAITERS];
#if CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0
struct cxd56_gnss_sig_s sigs[CONFIG_CXD56_GNSS_NSIGNALRECEIVERS];
@ -1884,8 +1884,8 @@ static int cxd56_gnss_select_rtk_satellite(struct file *filep,
static int cxd56_gnss_get_rtk_satellite(struct file *filep,
unsigned long arg)
{
int ret;
uint32_t gnss = 0;
int ret;
uint32_t gnss = 0;
if (!arg)
{
@ -2688,7 +2688,7 @@ static int cxd56_gnss_initialize(struct cxd56_gnss_dev_s *dev)
static int cxd56_gnss_open(struct file *filep)
{
struct inode * inode;
struct inode *inode;
struct cxd56_gnss_dev_s *priv;
int ret = OK;
int retry = 50;
@ -2795,7 +2795,7 @@ success:
static int cxd56_gnss_close(struct file *filep)
{
struct inode * inode;
struct inode *inode;
struct cxd56_gnss_dev_s *priv;
int ret = OK;
@ -2937,7 +2937,7 @@ static ssize_t cxd56_gnss_write(struct file *filep,
static int cxd56_gnss_ioctl(struct file *filep, int cmd,
unsigned long arg)
{
struct inode * inode;
struct inode *inode;
struct cxd56_gnss_dev_s *priv;
int ret;

4
arch/arm/src/cxd56xx/cxd56_hostif.c
View File

@ -442,9 +442,7 @@ static int hif_initialize(struct hostif_buff_s *buffer)
cxd56_iccinit(CXD56_PROTO_HOSTIF);
ret = cxd56_iccregisterhandler(CXD56_PROTO_HOSTIF, hif_rxhandler, NULL);
return ret;
return cxd56_iccregisterhandler(CXD56_PROTO_HOSTIF, hif_rxhandler, NULL);
}
/****************************************************************************

6
arch/arm/src/cxd56xx/cxd56_sdhci.c
View File

@ -261,8 +261,8 @@ struct cxd56_sdiodev_s
bool usedma;
bool dmasend_prepare;
size_t receive_size;
uint8_t *aligned_buffer; /* Used to buffer alignment */
uint8_t *receive_buffer; /* Used to keep receive buffer address */
uint8_t *aligned_buffer; /* Used to buffer alignment */
uint8_t *receive_buffer; /* Used to keep receive buffer address */
uint32_t dma_cmd;
uint32_t dmasend_cmd;
uint32_t dmasend_regcmd;
@ -2795,7 +2795,7 @@ static int cxd56_sdio_dmarecvsetup(struct sdio_dev_s *dev,
{
struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
unsigned int blocksize;
int ret = OK;
int ret = OK;
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
DEBUGASSERT(((uint32_t)buffer & 3) == 0);

24
arch/arm/src/cxd56xx/cxd56_spi.c
View File

@ -178,9 +178,9 @@ static const struct spi_ops_s g_spi4ops =
static struct cxd56_spidev_s g_spi4dev =
{
.spidev =
{
&g_spi4ops
},
{
.ops = &g_spi4ops,
},
.spibase = CXD56_IMG_SPI_BASE,
.spibasefreq = 0,
.port = 4,
@ -225,9 +225,9 @@ static const struct spi_ops_s g_spi5ops =
static struct cxd56_spidev_s g_spi5dev =
{
.spidev =
{
&g_spi5ops
},
{
.ops = &g_spi5ops,
},
.spibase = CXD56_IMG_WSPI_BASE,
.spibasefreq = 0,
.port = 5,
@ -271,9 +271,9 @@ static const struct spi_ops_s g_spi0ops =
static struct cxd56_spidev_s g_spi0dev =
{
.spidev =
{
&g_spi0ops
},
{
.ops = &g_spi0ops,
},
.spibase = CXD56_SPIM_BASE,
.spibasefreq = 0,
.port = 0,
@ -317,9 +317,9 @@ static const struct spi_ops_s g_spi3ops =
static struct cxd56_spidev_s g_spi3dev =
{
.spidev =
{
&g_spi3ops
},
{
.ops = &g_spi3ops,
},
.spibase = CXD56_SCU_SPI_BASE,
.spibasefreq = 0,
.port = 3,

10
arch/arm/src/cxd56xx/cxd56_uart0.c
View File

@ -231,15 +231,7 @@ static ssize_t uart0_write(struct file *filep,
int cxd56_uart0initialize(const char *devname)
{
int ret;
ret = register_driver(devname, &g_uart0fops, 0666, NULL);
if (ret != 0)
{
return ERROR;
}
return OK;
return register_driver(devname, &g_uart0fops, 0666, NULL);
}
/****************************************************************************

2
arch/arm/src/efm32/efm32_i2c.c
View File

@ -742,7 +742,7 @@ static void efm32_i2c_setclock(struct efm32_i2c_priv_s *priv,
#elif defined(CONFIG_EFM32_I2C_CLHR_ASYMMETRIC)
# define n (6 + 3) /* Ratio is 6:3 */
#else /* CLHR STANDARD */
# define n ( 4 + 4) /* Ratio is 4:4 */
# define n (4 + 4) /* Ratio is 4:4 */
#endif
div = (BOARD_HFPERCLK_FREQUENCY - (4 * frequency)) / (n * frequency);

6
arch/arm/src/efm32/efm32_usbhost.c
View File

@ -494,8 +494,8 @@ static struct efm32_usbhost_s g_usbhost =
static struct usbhost_connection_s g_usbconn =
{
.wait = efm32_wait,
.enumerate = efm32_enumerate,
.wait = efm32_wait,
.enumerate = efm32_enumerate,
};
#ifdef HAVE_USBHOST_TRACE
@ -5280,7 +5280,7 @@ static inline void efm32_sw_initialize(struct efm32_usbhost_s *priv)
struct efm32_chan_s *chan = &priv->chan[i];
chan->chidx = i;
nxsem_init(&chan->waitsem, 0, 0);
nxsem_init(&chan->waitsem, 0, 0);
}
}

2
arch/arm/src/gd32f4/gd32f4xx_dma.c
View File

@ -176,7 +176,7 @@ static struct gd32_dma_channel_s g_dmachan[DMA_NCHANNELS] =
.chan_num = GD32_DMA_CH6,
.irq = GD32_IRQ_DMA1_CHANNEL6,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
.dmabase = GD32_DMA1,
},
{
.chan_num = GD32_DMA_CH7,

18
arch/arm/src/gd32f4/gd32f4xx_spi.c
View File

@ -293,9 +293,9 @@ static uint8_t g_spi0_rxbuf[SPI0_DMA_BUFSIZE_ADJ] SPI_DMA_BUFEER_ALIGN;
static struct gd32_spidev_s g_spi0dev =
{
.spidev =
{
&g_spi0ops
},
{
.ops = &g_spi0ops
},
.spibase = GD32_SPI0,
.spiclock = GD32_PCLK2_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
@ -1451,12 +1451,12 @@ static void spi_exchange_nodma(struct spi_dev_s *dev,
struct gd32_spidev_s *priv = (struct gd32_spidev_s *)dev;
DEBUGASSERT(priv && priv->spibase);
uint8_t *brxptr = (uint8_t *)rxbuffer;
const uint8_t *btxptr = (uint8_t *)txbuffer;
uint16_t *wrxptr = (uint16_t *)rxbuffer;
const uint16_t *wtxptr = (const uint16_t *)txbuffer;
uint8_t byte;
uint16_t word;
uint8_t *brxptr = (uint8_t *)rxbuffer;
const uint8_t *btxptr = (uint8_t *)txbuffer;
uint16_t *wrxptr = (uint16_t *)rxbuffer;
const uint16_t *wtxptr = (const uint16_t *)txbuffer;
uint8_t byte;
uint16_t word;
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);

12
arch/arm/src/imx1/imx_spi.c
View File

@ -207,23 +207,23 @@ static struct imx_spidev_s g_spidev[] =
{
#ifdef CONFIG_IMX1_SPI1
{
.ops = &g_spiops,
.base = IMX_CSPI1_VBASE,
.ops = &g_spiops,
.base = IMX_CSPI1_VBASE,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_CSPI1,
.irq = IMX_IRQ_CSPI1,
#endif
},
#endif
#ifdef CONFIG_IMX1_SPI2
{
.ops = &g_spiops,
.base = IMX_CSPI2_VBASE,
.ops = &g_spiops,
.base = IMX_CSPI2_VBASE,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_CSPI2,
.irq = IMX_IRQ_CSPI2,
#endif
},
#endif

18
arch/arm/src/imxrt/imxrt_ehci.c
View File

@ -592,7 +592,7 @@ static struct imxrt_qh_s g_asynchead aligned_data(32);
#ifndef CONFIG_USBHOST_INT_DISABLE
/* The head of the periodic queue */
static struct imxrt_qh_s g_intrhead aligned_data(32);
static struct imxrt_qh_s g_intrhead aligned_data(32);
/* The frame list */
@ -4978,21 +4978,21 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
/* Sanity checks */
DEBUGASSERT(controller == 0);
DEBUGASSERT(((uintptr_t) & g_asynchead & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_asynchead & 0x1f) == 0);
DEBUGASSERT((sizeof(struct imxrt_qh_s) & 0x1f) == 0);
DEBUGASSERT((sizeof(struct imxrt_qtd_s) & 0x1f) == 0);
# ifdef CONFIG_IMXRT_EHCI_PREALLOCATE
DEBUGASSERT(((uintptr_t) & g_qhpool & 0x1f) == 0);
DEBUGASSERT(((uintptr_t) & g_qtdpool & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_qhpool & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_qtdpool & 0x1f) == 0);
# endif
# ifndef CONFIG_USBHOST_INT_DISABLE
DEBUGASSERT(((uintptr_t) & g_intrhead & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_intrhead & 0x1f) == 0);
# ifdef CONFIG_IMXRT_EHCI_PREALLOCATE
DEBUGASSERT(((uintptr_t) g_framelist & 0xfff) == 0);
DEBUGASSERT(((uintptr_t)g_framelist & 0xfff) == 0);
# endif
# endif /* CONFIG_USBHOST_INT_DISABLE */
# endif /* CONFIG_USBHOST_INT_DISABLE */
/* Software Configuration *************************************************/
@ -5199,7 +5199,7 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
*/
memset(&g_asynchead, 0, sizeof(struct imxrt_qh_s));
physaddr = imxrt_physramaddr((uintptr_t) & g_asynchead);
physaddr = imxrt_physramaddr((uintptr_t)&g_asynchead);
g_asynchead.hw.hlp = imxrt_swap32(physaddr | QH_HLP_TYP_QH);
g_asynchead.hw.epchar = imxrt_swap32(QH_EPCHAR_H | QH_EPCHAR_EPS_FULL);
g_asynchead.hw.overlay.nqp = imxrt_swap32(QH_NQP_T);
@ -5230,7 +5230,7 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
/* Attach the periodic QH to Period Frame List */
physaddr = imxrt_physramaddr((uintptr_t) & g_intrhead);
physaddr = imxrt_physramaddr((uintptr_t)&g_intrhead);
for (i = 0; i < FRAME_LIST_SIZE; i++)
{
g_framelist[i] = imxrt_swap32(physaddr) | PFL_TYP_QH;

2
arch/arm/src/imxrt/imxrt_enc.c
View File

@ -1201,7 +1201,7 @@ static int imxrt_ioctl(struct qe_lowerhalf_s *lower, int cmd,
int imxrt_qeinitialize(const char *devpath, int enc)
{
struct imxrt_enc_lowerhalf_s * priv = NULL;
struct imxrt_enc_lowerhalf_s *priv = NULL;
switch (enc)
{

2
arch/arm/src/imxrt/imxrt_flexspi.c
View File

@ -112,7 +112,7 @@ static struct imxrt_flexspidev_s g_flexspi0dev =
{
.ops = &g_flexspi0ops,
},
.base = (struct flexspi_type_s *) IMXRT_FLEXSPIC_BASE,
.base = (struct flexspi_type_s *)IMXRT_FLEXSPIC_BASE,
.lock = NXMUTEX_INITIALIZER,
};

4
arch/arm/src/imxrt/imxrt_lpi2c.c
View File

@ -1070,7 +1070,7 @@ static void imxrt_lpi2c_setclock(struct imxrt_lpi2c_priv_s *priv,
CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT;
lpi2c_clk_div = lpi2c_clk_div + 1;
src_freq = (BOARD_XTAL_FREQUENCY * pll3_div) /
(8 * lpi2c_clk_div) ;
(8 * lpi2c_clk_div);
}
/* LPI2C output frequency = (Source Clock (Hz)/ 2^prescale) /
@ -1976,7 +1976,7 @@ static int imxrt_lpi2c_dma_transfer(struct imxrt_lpi2c_priv_s *priv)
LPI2C_MIER_NDIE | LPI2C_MIER_ALIE |
LPI2C_MIER_PLTIE | LPI2C_MIER_FEIE);
imxrt_dmach_start(priv->dma, imxrt_dma_callback, (void *)priv);
imxrt_dmach_start(priv->dma, imxrt_dma_callback, priv);
imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MDER_OFFSET, 0,
LPI2C_MDER_TDDE | LPI2C_MDER_RDDE);

36
arch/arm/src/imxrt/imxrt_lpspi.c
View File

@ -242,7 +242,7 @@ static struct imxrt_lpspidev_s g_lpspi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.spibase = IMXRT_LPSPI1_BASE,
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
@ -291,7 +291,7 @@ static struct imxrt_lpspidev_s g_lpspi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.spibase = IMXRT_LPSPI2_BASE,
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
@ -340,7 +340,7 @@ static struct imxrt_lpspidev_s g_lpspi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.spibase = IMXRT_LPSPI3_BASE,
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
@ -389,7 +389,7 @@ static struct imxrt_lpspidev_s g_lpspi4dev =
{
.spidev =
{
&g_spi4ops
.ops = &g_spi4ops,
},
.spibase = IMXRT_LPSPI4_BASE,
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
@ -1310,8 +1310,8 @@ static void imxrt_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;
uint16_t *dest = (uint16_t *) rxbuffer;
const uint16_t *src = txbuffer;
uint16_t *dest = rxbuffer;
uint16_t word;
while (nwords-- > 0)
@ -1343,8 +1343,8 @@ static void imxrt_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *) rxbuffer;
const uint8_t *src = txbuffer;
uint8_t *dest = rxbuffer;
uint8_t word;
while (nwords-- > 0)
@ -1362,7 +1362,7 @@ static void imxrt_lpspi_exchange_nodma(struct spi_dev_s *dev,
/* Exchange one word */
word = (uint8_t) imxrt_lpspi_send(dev, (uint32_t) word);
word = (uint8_t)imxrt_lpspi_send(dev, word);
/* Is there a buffer to receive the return value? */
@ -1396,16 +1396,16 @@ static void imxrt_lpspi_exchange_nodma(struct spi_dev_s *dev,
****************************************************************************/
#ifdef CONFIG_IMXRT_LPSPI_DMA
static void imxrt_lpspi_exchange(struct spi_dev_s * dev,
const void * txbuffer,
void * rxbuffer, size_t nwords)
static void imxrt_lpspi_exchange(struct spi_dev_s *dev,
const void *txbuffer,
void *rxbuffer, size_t nwords)
{
int ret;
size_t adjust;
ssize_t nbytes;
static uint8_t rxdummy[4] aligned_data(4);
static const uint16_t txdummy = 0xffff;
uint32_t regval;
int ret;
size_t adjust;
ssize_t nbytes;
static uint8_t rxdummy[4] aligned_data(4);
static const uint16_t txdummy = 0xffff;
uint32_t regval;
struct imxrt_lpspidev_s *priv = (struct imxrt_lpspidev_s *)dev;
DEBUGASSERT(priv != NULL);

10
arch/arm/src/imxrt/imxrt_serial.c
View File

@ -1538,7 +1538,7 @@ static int imxrt_dma_setup(struct uart_dev_s *dev)
* worth of time to claim bytes before they are overwritten.
*/
imxrt_dmach_start(priv->rxdma, imxrt_dma_rxcallback, (void *)priv);
imxrt_dmach_start(priv->rxdma, imxrt_dma_rxcallback, priv);
}
#endif
@ -1866,7 +1866,7 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg)
#ifdef CONFIG_SERIAL_TERMIOS
case TCGETS:
{
struct termios *termiosp = (struct termios *)arg;
struct termios *termiosp = (struct termios *)arg;
struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev;
if (!termiosp)
@ -1928,7 +1928,7 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg)
case TCSETS:
{
struct termios *termiosp = (struct termios *)arg;
struct termios *termiosp = (struct termios *)arg;
struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev;
uint32_t baud;
uint32_t ie;
@ -2398,7 +2398,7 @@ static void imxrt_dma_reenable(struct imxrt_uart_s *priv)
* worth of time to claim bytes before they are overwritten.
*/
imxrt_dmach_start(priv->rxdma, imxrt_dma_rxcallback, (void *)priv);
imxrt_dmach_start(priv->rxdma, imxrt_dma_rxcallback, priv);
/* Clear DMA suspended flag. */
@ -2569,7 +2569,7 @@ static void imxrt_dma_send(struct uart_dev_s *dev)
/* Start transmission with the callback on DMA completion */
imxrt_dmach_start(priv->txdma, imxrt_dma_txcallback, (void *)priv);
imxrt_dmach_start(priv->txdma, imxrt_dma_txcallback, priv);
}
#endif

10
arch/arm/src/imxrt/imxrt_usdhc.c
View File

@ -950,7 +950,7 @@ static void imxrt_receive(struct imxrt_dev_s *priv)
{
/* Transfer any trailing fractional word */
uint8_t *ptr = (uint8_t *) priv->buffer;
uint8_t *ptr = (uint8_t *)priv->buffer;
int i;
for (i = 0; i < priv->remaining; i++)
@ -2244,7 +2244,8 @@ static int imxrt_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer,
* handler and DMA memory invalidation.
*/
priv->buffer = (uint32_t *) buffer; priv->remaining = nbytes;
priv->buffer = (uint32_t *)buffer;
priv->remaining = nbytes;
/* Then set up the SDIO data path */
@ -2292,7 +2293,8 @@ static int imxrt_sendsetup(struct sdio_dev_s *dev,
/* Save the source buffer information for use by the interrupt handler */
priv->buffer = (uint32_t *) buffer; priv->remaining = nbytes;
priv->buffer = (uint32_t *)buffer;
priv->remaining = nbytes;
/* Then set up the SDIO data path */
@ -3039,7 +3041,7 @@ static int imxrt_dmasendsetup(struct sdio_dev_s *dev,
# endif
#endif
priv->buffer = (uint32_t *) buffer;
priv->buffer = (uint32_t *)buffer;
priv->remaining = buflen;
/* Then set up the SDIO data path */

20
arch/arm/src/kinetis/kinetis_spi.c
View File

@ -221,13 +221,13 @@ static const struct spi_ops_s g_spi0ops =
static struct kinetis_spidev_s g_spi0dev =
{
.spidev =
.spidev =
{
&g_spi0ops
},
.spibase = KINETIS_SPI0_BASE,
.spibase = KINETIS_SPI0_BASE,
.lock = NXMUTEX_INITIALIZER,
.ctarsel = KINETIS_SPI_CTAR0_OFFSET,
.ctarsel = KINETIS_SPI_CTAR0_OFFSET,
#ifdef CONFIG_KINETIS_SPI_DMA
# ifdef CONFIG_KINETIS_SPI0_DMA
.rxch = KINETIS_DMA_REQUEST_SRC_SPI0_RX,
@ -273,13 +273,13 @@ static const struct spi_ops_s g_spi1ops =
static struct kinetis_spidev_s g_spi1dev =
{
.spidev =
.spidev =
{
&g_spi1ops
},
.spibase = KINETIS_SPI1_BASE,
.spibase = KINETIS_SPI1_BASE,
.lock = NXMUTEX_INITIALIZER,
.ctarsel = KINETIS_SPI_CTAR0_OFFSET,
.ctarsel = KINETIS_SPI_CTAR0_OFFSET,
#ifdef CONFIG_KINETIS_SPI_DMA
# ifdef CONFIG_KINETIS_SPI1_DMA
.rxch = KINETIS_DMA_REQUEST_SRC_SPI1_RX,
@ -325,13 +325,13 @@ static const struct spi_ops_s g_spi2ops =
static struct kinetis_spidev_s g_spi2dev =
{
.spidev =
.spidev =
{
&g_spi2ops
},
.spibase = KINETIS_SPI2_BASE,
.spibase = KINETIS_SPI2_BASE,
.lock = NXMUTEX_INITIALIZER,
.ctarsel = KINETIS_SPI_CTAR0_OFFSET,
.ctarsel = KINETIS_SPI_CTAR0_OFFSET,
#ifdef CONFIG_KINETIS_SPI_DMA
# ifdef CONFIG_KINETIS_SPI2_DMA
.rxch = KINETIS_DMA_REQUEST_SRC_FTM3_CH6__SPI2_RX,
@ -1667,7 +1667,7 @@ struct spi_dev_s *kinetis_spibus_initialize(int port)
/* select mode 0 */
priv->mode = SPIDEV_MODE3;
priv->mode = SPIDEV_MODE3;
spi_setmode(&priv->spidev, SPIDEV_MODE0);
/* Select a default frequency of approx. 400KHz */

18
arch/arm/src/kinetis/kinetis_usbhshost.c
View File

@ -4042,10 +4042,6 @@ static int kinetis_epalloc(struct usbhost_driver_s *drvr,
epinfo->xfrtype = epdesc->xfrtype;
epinfo->speed = hport->speed;
/* The iocsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(&epinfo->iocsem, 0, 0);
/* Success.. return an opaque reference to the endpoint information
@ -5052,21 +5048,21 @@ struct usbhost_connection_s *kinetis_ehci_initialize(int controller)
/* Sanity checks */
DEBUGASSERT(controller == 0);
DEBUGASSERT(((uintptr_t) & g_asynchead & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_asynchead & 0x1f) == 0);
DEBUGASSERT((sizeof(struct kinetis_qh_s) & 0x1f) == 0);
DEBUGASSERT((sizeof(struct kinetis_qtd_s) & 0x1f) == 0);
# ifdef CONFIG_KINETIS_EHCI_PREALLOCATE
DEBUGASSERT(((uintptr_t) & g_qhpool & 0x1f) == 0);
DEBUGASSERT(((uintptr_t) & g_qtdpool & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_qhpool & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_qtdpool & 0x1f) == 0);
# endif
# ifndef CONFIG_USBHOST_INT_DISABLE
DEBUGASSERT(((uintptr_t) & g_intrhead & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_intrhead & 0x1f) == 0);
# ifdef CONFIG_KINETIS_EHCI_PREALLOCATE
DEBUGASSERT(((uintptr_t) g_framelist & 0xfff) == 0);
DEBUGASSERT(((uintptr_t)g_framelist & 0xfff) == 0);
# endif
# endif /* CONFIG_USBHOST_INT_DISABLE */
# endif /* CONFIG_USBHOST_INT_DISABLE */
/* Software Configuration *************************************************/
@ -5300,7 +5296,7 @@ struct usbhost_connection_s *kinetis_ehci_initialize(int controller)
/* Attach the periodic QH to Period Frame List */
physaddr = kinetis_physramaddr((uintptr_t) & g_intrhead);
physaddr = kinetis_physramaddr((uintptr_t)&g_intrhead);
for (i = 0; i < FRAME_LIST_SIZE; i++)
{
g_framelist[i] = kinetis_swap32(physaddr) | PFL_TYP_QH;

12
arch/arm/src/kl/kl_spi.c
View File

@ -122,9 +122,9 @@ static const struct spi_ops_s g_spi0ops =
static struct kl_spidev_s g_spi0dev =
{
.spidev =
{
&g_spi0ops
},
{
.ops = &g_spi0ops
},
.spibase = KL_SPI0_BASE,
.lock = NXMUTEX_INITIALIZER,
};
@ -155,9 +155,9 @@ static const struct spi_ops_s g_spi1ops =
static struct kl_spidev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
},
{
.ops = &g_spi1ops
},
.spibase = KL_SPI1_BASE,
.lock = NXMUTEX_INITIALIZER,
};

2
arch/arm/src/lc823450/lc823450_dma.c
View File

@ -306,7 +306,7 @@ static void dma_done(DMA_HANDLE handle, void *arg, int result)
test_done = 1;
}
void lc823450_dma_test()
void lc823450_dma_test(void)
{
int i;
for (i = 0; i < 256; i++)

1
arch/arm/src/lc823450/lc823450_mtd.c
View File

@ -815,7 +815,6 @@ int lc823450_mtd_uninitialize(uint32_t devno)
DEBUGASSERT(ret == OK);
nxmutex_destroy(&priv->lock);
kmm_free(g_mtdmaster[ch]);
g_mtdmaster[ch] = NULL;

2
arch/arm/src/lc823450/lc823450_sdc.c
View File

@ -82,7 +82,7 @@
static mutex_t _sdc_lock[2] =
{
NXMUTEX_INITIALIZER,
NXMUTEX_INITIALIZER
NXMUTEX_INITIALIZER,
};
static struct sddrcfg_s _sdch0;

3
arch/arm/src/lc823450/lc823450_serial.c
View File

@ -168,7 +168,6 @@ struct up_dev_s
DMA_HANDLE hrxdma;
DMA_HANDLE htxdma;
sem_t rxdma_wait;
sem_t rxpkt_wait;
sem_t txdma_wait;
#endif /* CONFIG_HSUART */
spinlock_t lock;
@ -1112,7 +1111,7 @@ static void uart_rxdma_callback(DMA_HANDLE hdma, void *arg, int result)
* Name: up_hs_dmasetup
****************************************************************************/
static void up_hs_dmasetup()
static void up_hs_dmasetup(void)
{
irqstate_t flags;

8
arch/arm/src/lc823450/lc823450_spi.c
View File

@ -73,7 +73,7 @@ struct lc823450_spidev_s
#endif
#ifdef CONFIG_LC823450_SPI_DMA
DMA_HANDLE hdma;
sem_t dma_wait;
sem_t dma_wait;
#endif /* CONFIG_LC823450_SPI_DMA */
};
@ -127,9 +127,9 @@ static const struct spi_ops_s g_spiops =
static struct lc823450_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
},
{
.ops = &g_spiops
},
#ifndef CONFIG_SPI_OWNBUS
.lock = NXMUTEX_INITIALIZER,
#endif

7
arch/arm/src/lc823450/lc823450_usbdev.c
View File

@ -560,7 +560,7 @@ static struct usbdev_req_s *lc823450_epallocreq(struct usbdev_ep_s *ep)
usbtrace(TRACE_EPALLOCREQ, ((struct lc823450_ep_s *)ep)->epphy);
privreq = (struct lc823450_req_s *)
kmm_malloc(sizeof(struct lc823450_req_s));
kmm_zalloc(sizeof(struct lc823450_req_s));
if (!privreq)
{
@ -568,7 +568,6 @@ static struct usbdev_req_s *lc823450_epallocreq(struct usbdev_ep_s *ep)
return NULL;
}
memset(privreq, 0, sizeof(struct lc823450_req_s));
return &privreq->req;
}
@ -1710,7 +1709,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
* Name: usbdev_msc_read_enter
****************************************************************************/
void usbdev_msc_read_enter()
void usbdev_msc_read_enter(void)
{
struct lc823450_ep_s *privep;
# ifdef CONFIG_DVFS
@ -1727,7 +1726,7 @@ void usbdev_msc_read_enter()
* Name: usbdev_msc_read_exit
****************************************************************************/
void usbdev_msc_read_exit()
void usbdev_msc_read_exit(void)
{
struct lc823450_ep_s *privep;

8
arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c
View File

@ -139,7 +139,7 @@ static void lpc17_40_stopnext(struct lpc17_40_i2cdev_s *priv);
static int lpc17_40_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int lpc17_40_i2c_reset(struct i2c_master_s * dev);
static int lpc17_40_i2c_reset(struct i2c_master_s *dev);
#endif
/****************************************************************************
@ -505,7 +505,7 @@ static int lpc17_40_i2c_interrupt(int irq, void *context, void *arg)
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int lpc17_40_i2c_reset(struct i2c_master_s * dev)
static int lpc17_40_i2c_reset(struct i2c_master_s *dev)
{
return OK;
}
@ -651,9 +651,9 @@ struct i2c_master_s *lpc17_40_i2cbus_initialize(int port)
*
****************************************************************************/
int lpc17_40_i2cbus_uninitialize(struct i2c_master_s * dev)
int lpc17_40_i2cbus_uninitialize(struct i2c_master_s *dev)
{
struct lpc17_40_i2cdev_s *priv = (struct lpc17_40_i2cdev_s *) dev;
struct lpc17_40_i2cdev_s *priv = (struct lpc17_40_i2cdev_s *)dev;
/* Disable I2C */

8
arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c
View File

@ -139,10 +139,10 @@ static const struct spi_ops_s g_spiops =
static struct lpc17_40_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
},
.lock = NXMUTEX_INITIALIZER,
{
.ops = &g_spiops,
},
.lock = NXMUTEX_INITIALIZER,
};
/****************************************************************************

18
arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c
View File

@ -177,9 +177,9 @@ static const struct spi_ops_s g_spi0ops =
static struct lpc17_40_sspdev_s g_ssp0dev =
{
.spidev =
{
&g_spi0ops
},
{
.ops = &g_spi0ops,
},
.sspbase = LPC17_40_SSP0_BASE,
#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS
.sspirq = LPC17_40_IRQ_SSP0,
@ -213,9 +213,9 @@ static const struct spi_ops_s g_spi1ops =
static struct lpc17_40_sspdev_s g_ssp1dev =
{
.spidev =
{
&g_spi1ops
},
{
.ops = &g_spi1ops,
},
.sspbase = LPC17_40_SSP1_BASE,
#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS
.sspirq = LPC17_40_IRQ_SSP1,
@ -249,9 +249,9 @@ static const struct spi_ops_s g_spi2ops =
static struct lpc17_40_sspdev_s g_ssp2dev =
{
.spidev =
{
&g_spi2ops
},
{
.ops = &g_spi2ops,
},
.sspbase = LPC17_40_SSP2_BASE,
#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS
.sspirq = LPC17_40_IRQ_SSP2,

8
arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c
View File

@ -421,8 +421,8 @@ static struct lpc17_40_usbhost_s g_usbhost =
static struct usbhost_connection_s g_usbconn =
{
.wait = lpc17_40_wait,
.enumerate = lpc17_40_enumerate,
.wait = lpc17_40_wait,
.enumerate = lpc17_40_enumerate,
};
/* This is a free list of EDs and TD buffers */
@ -2665,7 +2665,7 @@ static int lpc17_40_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
struct lpc17_40_usbhost_s *priv = (struct lpc17_40_usbhost_s *)drvr;
struct lpc17_40_ed_s *ed = (struct lpc17_40_ed_s *)ep0;
uint16_t len;
int ret;
int ret;
DEBUGASSERT(priv != NULL && ed != NULL && req != NULL);
@ -3634,7 +3634,7 @@ static inline void lpc17_40_ep0init(struct lpc17_40_usbhost_s *priv)
/* Initialize the common tail TD. */
memset(TDTAIL, 0, sizeof(struct lpc17_40_gtd_s));
TDTAIL->ed = EDCTRL;
TDTAIL->ed = EDCTRL;
/* Link the common tail TD to the ED's TD list */

8
arch/arm/src/lpc2378/lpc23xx_i2c.c
View File

@ -145,7 +145,7 @@ static void lpc2378_stopnext(struct lpc2378_i2cdev_s *priv);
static int lpc2378_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int lpc2378_i2c_reset(struct i2c_master_s * dev);
static int lpc2378_i2c_reset(struct i2c_master_s *dev);
#endif
/****************************************************************************
@ -457,7 +457,7 @@ static int lpc2378_i2c_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int lpc2378_i2c_reset(struct i2c_master_s * dev)
static int lpc2378_i2c_reset(struct i2c_master_s *dev)
{
return OK;
}
@ -614,9 +614,9 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port)
*
****************************************************************************/
int lpc2378_i2cbus_uninitialize(struct i2c_master_s * dev)
int lpc2378_i2cbus_uninitialize(struct i2c_master_s *dev)
{
struct lpc2378_i2cdev_s *priv = (struct lpc2378_i2cdev_s *) dev;
struct lpc2378_i2cdev_s *priv = (struct lpc2378_i2cdev_s *)dev;
/* Disable I2C */

8
arch/arm/src/lpc2378/lpc23xx_spi.c
View File

@ -158,10 +158,10 @@ static const struct spi_ops_s g_spiops =
static struct lpc23xx_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
},
.lock = NXMUTEX_INITIALIZER,
{
.ops = &g_spiops,
},
.lock = NXMUTEX_INITIALIZER,
};
/****************************************************************************

8
arch/arm/src/lpc31xx/lpc31_i2c.c
View File

@ -115,7 +115,7 @@ static void i2c_setfrequency(struct lpc31_i2cdev_s *priv,
static int i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int i2c_reset(struct i2c_master_s * dev);
static int i2c_reset(struct i2c_master_s *dev);
#endif
/****************************************************************************
@ -418,7 +418,7 @@ out:
static void i2c_timeout(wdparm_t arg)
{
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) arg;
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *)arg;
irqstate_t flags = enter_critical_section();
@ -478,7 +478,7 @@ static void i2c_hwreset(struct lpc31_i2cdev_s *priv)
static int i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count)
{
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev;
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *)dev;
irqstate_t flags;
int ret;
@ -539,7 +539,7 @@ static int i2c_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int i2c_reset(struct i2c_master_s * dev)
static int i2c_reset(struct i2c_master_s *dev)
{
return OK;
}

10
arch/arm/src/lpc31xx/lpc31_spi.c
View File

@ -154,10 +154,10 @@ static const struct spi_ops_s g_spiops =
static struct lpc31_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
},
.lock = NXMUTEX_INITIALIZER,
{
.ops = &g_spiops,
},
.lock = NXMUTEX_INITIALIZER,
};
#ifdef CONFIG_LPC31_SPI_REGDEBUG
@ -489,7 +489,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock)
static void spi_select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
struct lpc31_spidev_s *priv = (struct lpc31_spidev_s *) dev;
struct lpc31_spidev_s *priv = (struct lpc31_spidev_s *)dev;
uint8_t slave = 0;
/* FIXME: map the devid to the SPI slave - this should really

8
arch/arm/src/lpc43xx/lpc43_i2c.c
View File

@ -145,7 +145,7 @@ static void lpc43_i2c_setfrequency(struct lpc43_i2cdev_s *priv,
static int lpc43_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int lpc43_i2c_reset(struct i2c_master_s * dev);
static int lpc43_i2c_reset(struct i2c_master_s *dev);
#endif
/****************************************************************************
@ -436,7 +436,7 @@ static int lpc43_i2c_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int lpc43_i2c_reset(struct i2c_master_s * dev)
static int lpc43_i2c_reset(struct i2c_master_s *dev)
{
return OK;
}
@ -558,9 +558,9 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
*
****************************************************************************/
int lpc43_i2cbus_uninitialize(struct i2c_master_s * dev)
int lpc43_i2cbus_uninitialize(struct i2c_master_s *dev)
{
struct lpc43_i2cdev_s *priv = (struct lpc43_i2cdev_s *) dev;
struct lpc43_i2cdev_s *priv = (struct lpc43_i2cdev_s *)dev;
putreg32(I2C_CONCLRT_I2ENC, priv->base + LPC43_I2C_CONCLR_OFFSET);
up_disable_irq(priv->irqid);

8
arch/arm/src/lpc43xx/lpc43_spi.c
View File

@ -130,10 +130,10 @@ static const struct spi_ops_s g_spiops =
static struct lpc43_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
},
.lock = NXMUTEX_INITIALIZER,
{
.ops = &g_spiops,
},
.lock = NXMUTEX_INITIALIZER,
};
/****************************************************************************

12
arch/arm/src/lpc43xx/lpc43_ssp.c
View File

@ -144,9 +144,9 @@ static const struct spi_ops_s g_spi0ops =
static struct lpc43_sspdev_s g_ssp0dev =
{
.spidev =
{
&g_spi0ops
},
{
.ops = &g_spi0ops,
},
.sspbase = LPC43_SSP0_BASE,
.sspbasefreq = BOARD_SSP0_BASEFREQ,
#ifdef CONFIG_LPC43_SSP_INTERRUPTS
@ -185,9 +185,9 @@ static const struct spi_ops_s g_spi1ops =
static struct lpc43_sspdev_s g_ssp1dev =
{
.spidev =
{
&g_spi1ops
},
{
.ops = &g_spi1ops,
},
.sspbase = LPC43_SSP1_BASE,
.sspbasefreq = BOARD_SSP1_BASEFREQ,
#ifdef CONFIG_LPC43_SSP_INTERRUPTS

8
arch/arm/src/lpc54xx/lpc54_i2c_master.c
View File

@ -169,7 +169,7 @@ static int lpc54_i2c_poll(struct lpc54_i2cdev_s *priv);
static int lpc54_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int lpc54_i2c_reset(struct i2c_master_s * dev);
static int lpc54_i2c_reset(struct i2c_master_s *dev);
#endif
/****************************************************************************
@ -878,7 +878,7 @@ static int lpc54_i2c_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int lpc54_i2c_reset(struct i2c_master_s * dev)
static int lpc54_i2c_reset(struct i2c_master_s *dev)
{
#warning Missing logic
return OK;
@ -1302,9 +1302,9 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
*
****************************************************************************/
int lpc54_i2cbus_uninitialize(struct i2c_master_s * dev)
int lpc54_i2cbus_uninitialize(struct i2c_master_s *dev)
{
struct lpc54_i2cdev_s *priv = (struct lpc54_i2cdev_s *) dev;
struct lpc54_i2cdev_s *priv = (struct lpc54_i2cdev_s *)dev;
uint32_t regval;
/* Disable I2C interrupts */

2
arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c
View File

@ -145,7 +145,7 @@ static const struct rtc_ops_s g_rtc_ops =
static struct lpc54_lowerhalf_s g_rtc_lowerhalf =
{
.ops = &g_rtc_ops,
.ops = &g_rtc_ops,
.devlock = NXMUTEX_INITIALIZER,
};

10
arch/arm/src/lpc54xx/lpc54_usb0_ohci.c
View File

@ -510,8 +510,8 @@ static struct lpc54_usbhost_s g_usbhost =
static struct usbhost_connection_s g_usbconn =
{
.wait = lpc54_wait,
.enumerate = lpc54_enumerate,
.wait = lpc54_wait,
.enumerate = lpc54_enumerate,
};
/* Aligned static memory allocations */
@ -2756,7 +2756,7 @@ static int lpc54_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
struct lpc54_usbhost_s *priv = (struct lpc54_usbhost_s *)drvr;
struct lpc54_ed_s *ed = (struct lpc54_ed_s *)ep0;
uint16_t len;
int ret;
int ret;
DEBUGASSERT(priv != NULL && ed != NULL && req != NULL);
@ -2799,7 +2799,7 @@ static int lpc54_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
struct lpc54_usbhost_s *priv = (struct lpc54_usbhost_s *)drvr;
struct lpc54_ed_s *ed = (struct lpc54_ed_s *)ep0;
uint16_t len;
int ret;
int ret;
DEBUGASSERT(priv != NULL && ed != NULL && req != NULL);
@ -3721,7 +3721,7 @@ static inline void lpc54_ep0init(struct lpc54_usbhost_s *priv)
/* Initialize the common tail TD. */
memset(TDTAIL, 0, sizeof(struct lpc54_gtd_s));
TDTAIL->ed = EDCTRL;
TDTAIL->ed = EDCTRL;
/* Link the common tail TD to the ED's TD list */

2
arch/arm/src/max326xx/common/max326_rtc_lowerhalf.c
View File

@ -151,7 +151,7 @@ static const struct rtc_ops_s g_rtc_ops =
static struct max326_lowerhalf_s g_rtc_lowerhalf =
{
.ops = &g_rtc_ops,
.ops = &g_rtc_ops,
.devlock = NXMUTEX_INITIALIZER,
};

8
arch/arm/src/max326xx/max32660/max32660_spim.c
View File

@ -189,7 +189,7 @@ static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer,
/* Initialization */
static void spi_bus_initialize(struct max326_spidev_s *priv);
static void spi_bus_initialize(struct max326_spidev_s *priv);
/****************************************************************************
* Private Data
@ -232,9 +232,9 @@ static const struct spi_ops_s g_sp0iops =
static struct max326_spidev_s g_spi0dev =
{
.dev =
{
&g_sp0iops
},
{
.ops = &g_sp0iops,
},
.base = MAX326_SPI0_BASE,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_MAX326_SPI_INTERRUPTS

4
arch/arm/src/nrf52/nrf52_rng.c
View File

@ -145,7 +145,7 @@ static int nrf52_rng_initialize(void)
static int nrf52_rng_irqhandler(int irq, void *context, void *arg)
{
struct rng_dev_s *priv = (struct rng_dev_s *) &g_rngdev;
struct rng_dev_s *priv = (struct rng_dev_s *)&g_rngdev;
uint8_t *addr;
if (getreg32(NRF52_RNG_EVENTS_RDY) == RNG_INT_RDY)
@ -200,7 +200,7 @@ static ssize_t nrf52_rng_read(struct file *filep, char *buffer,
return -EBUSY;
}
priv->rd_buf = (uint8_t *) buffer;
priv->rd_buf = (uint8_t *)buffer;
priv->buflen = buflen;
priv->rd_count = 0;

8
arch/arm/src/nrf52/nrf52_spi.c
View File

@ -198,7 +198,7 @@ static struct nrf52_spidev_s g_spi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.base = NRF52_SPIM0_BASE,
@ -251,7 +251,7 @@ static struct nrf52_spidev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.base = NRF52_SPIM1_BASE,
@ -304,7 +304,7 @@ static struct nrf52_spidev_s g_spi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.base = NRF52_SPIM2_BASE,
@ -357,7 +357,7 @@ static struct nrf52_spidev_s g_spi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.base = NRF52_SPIM3_BASE,

32
arch/arm/src/rp2040/rp2040_flash_mtd.c
View File

@ -68,8 +68,8 @@
#define FLASH_BLOCK_ERASE_CMD 0x20
#define BOOT_2_SIZE 256
#define FLASH_START_OFFSET (rp2040_smart_flash_start - (uint8_t *) XIP_BASE)
#define FLASH_END_OFFSET (rp2040_smart_flash_end - (uint8_t *) XIP_BASE)
#define FLASH_START_OFFSET (rp2040_smart_flash_start - (uint8_t *)XIP_BASE)
#define FLASH_END_OFFSET (rp2040_smart_flash_end - (uint8_t *)XIP_BASE)
#define FLASH_START_READ (rp2040_smart_flash_start + 0x03000000)
/* Note: There is some ambiguity in terminology when it comes to flash.
@ -155,16 +155,16 @@ extern const uint8_t rp2040_smart_flash_end[0];
static struct rp2040_flash_dev_s my_dev =
{
.mtd_dev =
{
rp2040_flash_erase,
rp2040_flash_block_read,
rp2040_flash_block_write,
rp2040_flash_byte_read,
{
rp2040_flash_erase,
rp2040_flash_block_read,
rp2040_flash_block_write,
rp2040_flash_byte_read,
#ifdef CONFIG_MTD_BYTE_WRITE
NULL,
NULL,
#endif
rp2040_flash_ioctl,
"rp_flash"
rp2040_flash_ioctl,
"rp_flash"
},
.lock = NXMUTEX_INITIALIZER,
};
@ -247,7 +247,7 @@ static int rp2040_flash_erase(struct mtd_dev_s *dev,
off_t startblock,
size_t nblocks)
{
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *) dev;
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *)dev;
irqstate_t flags;
int ret = OK;
@ -293,7 +293,7 @@ static ssize_t rp2040_flash_block_read(struct mtd_dev_s *dev,
size_t nblocks,
uint8_t *buffer)
{
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *) dev;
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *)dev;
int start;
int length;
int ret = OK;
@ -336,7 +336,7 @@ static ssize_t rp2040_flash_block_write(struct mtd_dev_s *dev,
size_t nblocks,
const uint8_t *buffer)
{
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *) dev;
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *)dev;
irqstate_t flags;
int ret;
@ -443,7 +443,7 @@ static int rp2040_flash_ioctl(struct mtd_dev_s *dev,
int cmd,
unsigned long arg)
{
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *) dev;
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *)dev;
int ret = OK;
UNUSED(rp_dev);
@ -452,7 +452,7 @@ static int rp2040_flash_ioctl(struct mtd_dev_s *dev,
{
case MTDIOC_GEOMETRY:
{
struct mtd_geometry_s *geo = (struct mtd_geometry_s *) arg;
struct mtd_geometry_s *geo = (struct mtd_geometry_s *)arg;
if (geo != NULL)
{
@ -525,7 +525,7 @@ struct mtd_dev_s *rp2040_flash_mtd_initialize(void)
* the rom until after this call completes.
*/
memcpy(my_dev.boot_2, (void *) XIP_BASE, BOOT_2_SIZE);
memcpy(my_dev.boot_2, (void *)XIP_BASE, BOOT_2_SIZE);
rom_functions.flash_enable_xip = (flash_enable_xip_f)my_dev.boot_2 + 1;
/* Do we need to initialize the flash? */

6
arch/arm/src/rp2040/rp2040_i2s.c
View File

@ -964,7 +964,7 @@ static int rp2040_i2s_ioctl(struct i2s_dev_s *dev, int cmd,
unsigned long arg)
{
struct rp2040_i2s_s *priv = (struct rp2040_i2s_s *)dev;
struct audio_buf_desc_s *bufdesc;
struct audio_buf_desc_s *bufdesc;
int ret = -ENOTTY;
switch (cmd)
@ -1095,7 +1095,7 @@ static int rp2040_i2s_ioctl(struct i2s_dev_s *dev, int cmd,
{
i2sinfo("AUDIOIOC_ALLOCBUFFER\n");
bufdesc = (struct audio_buf_desc_s *) arg;
bufdesc = (struct audio_buf_desc_s *)arg;
ret = apb_alloc(bufdesc);
}
break;
@ -1109,7 +1109,7 @@ static int rp2040_i2s_ioctl(struct i2s_dev_s *dev, int cmd,
{
i2sinfo("AUDIOIOC_FREEBUFFER\n");
bufdesc = (struct audio_buf_desc_s *) arg;
bufdesc = (struct audio_buf_desc_s *)arg;
DEBUGASSERT(bufdesc->u.buffer != NULL);
apb_free(bufdesc->u.buffer);
ret = sizeof(struct audio_buf_desc_s);

13
arch/arm/src/rp2040/rp2040_spi.c
View File

@ -177,9 +177,9 @@ static const struct spi_ops_s g_spi0ops =
static struct rp2040_spidev_s g_spi0dev =
{
.spidev =
{
&g_spi0ops
},
{
.ops = &g_spi0ops,
},
.spibase = RP2040_SPI0_BASE,
.spibasefreq = 0,
.port = 0,
@ -226,9 +226,9 @@ static const struct spi_ops_s g_spi1ops =
static struct rp2040_spidev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
},
{
.ops = &g_spi1ops,
},
.spibase = RP2040_SPI1_BASE,
.spibasefreq = 0,
.port = 1,
@ -874,7 +874,6 @@ struct spi_dev_s *rp2040_spibus_initialize(int port)
/* Set a initialized flag */
priv->initialized = 1;
return &priv->spidev;
}

4
arch/arm/src/s32k1xx/s32k1xx_lpi2c.c
View File

@ -1776,8 +1776,8 @@ static int s32k1xx_lpi2c_dma_transfer(struct s32k1xx_lpi2c_priv_s *priv)
LPI2C_MIER_NDIE | LPI2C_MIER_ALIE |
LPI2C_MIER_PLTIE | LPI2C_MIER_FEIE);
s32k1xx_dmach_start(priv->rxdma, s32k1xx_rxdma_callback, (void *)priv);
s32k1xx_dmach_start(priv->txdma, s32k1xx_txdma_callback, (void *)priv);
s32k1xx_dmach_start(priv->rxdma, s32k1xx_rxdma_callback, priv);
s32k1xx_dmach_start(priv->txdma, s32k1xx_txdma_callback, priv);
s32k1xx_lpi2c_modifyreg(priv, S32K1XX_LPI2C_MDER_OFFSET, 0,
LPI2C_MDER_TDDE | LPI2C_MDER_RDDE);

22
arch/arm/src/s32k1xx/s32k1xx_lpspi.c
View File

@ -255,7 +255,7 @@ static struct s32k1xx_lpspidev_s g_lpspi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.spibase = S32K1XX_LPSPI0_BASE,
#ifdef CONFIG_S32K1XX_LPSPI_INTERRUPTS
@ -306,7 +306,7 @@ static struct s32k1xx_lpspidev_s g_lpspi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.spibase = S32K1XX_LPSPI1_BASE,
#ifdef CONFIG_S32K1XX_LPSPI_INTERRUPTS
@ -357,7 +357,7 @@ static struct s32k1xx_lpspidev_s g_lpspi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.spibase = S32K1XX_LPSPI2_BASE,
#ifdef CONFIG_S32K1XX_LPSPI_INTERRUPTS
@ -1369,8 +1369,8 @@ static void s32k1xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
* take care of big endian mode of hardware !!
*/
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *) rxbuffer;
const uint8_t *src = txbuffer;
uint8_t *dest = rxbuffer;
uint32_t word = 0x0;
#ifdef CONFIG_S32K1XX_LPSPI_DWORD
uint32_t word1 = 0x0;
@ -1447,8 +1447,8 @@ static void s32k1xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 32-bit or 64 bit, word size memory transfers */
const uint32_t *src = (const uint32_t *)txbuffer;
uint32_t *dest = (uint32_t *) rxbuffer;
const uint32_t *src = txbuffer;
uint32_t *dest = rxbuffer;
uint32_t word = 0x0;
#ifdef CONFIG_S32K1XX_LPSPI_DWORD
uint32_t word1 = 0x0;
@ -1528,8 +1528,8 @@ static void s32k1xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;
uint16_t *dest = (uint16_t *) rxbuffer;
const uint16_t *src = txbuffer;
uint16_t *dest = rxbuffer;
uint16_t word;
while (nwords-- > 0)
@ -1563,8 +1563,8 @@ static void s32k1xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *) rxbuffer;
const uint8_t *src = txbuffer;
uint8_t *dest = rxbuffer;
uint8_t word;
while (nwords-- > 0)

40
arch/arm/src/s32k3xx/s32k3xx_lpspi.c
View File

@ -246,7 +246,7 @@ static struct s32k3xx_lpspidev_s g_lpspi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.spibase = S32K3XX_LPSPI0_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@ -296,7 +296,7 @@ static struct s32k3xx_lpspidev_s g_lpspi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.spibase = S32K3XX_LPSPI1_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@ -346,7 +346,7 @@ static struct s32k3xx_lpspidev_s g_lpspi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.spibase = S32K3XX_LPSPI2_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@ -396,7 +396,7 @@ static struct s32k3xx_lpspidev_s g_lpspi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.spibase = S32K3XX_LPSPI3_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@ -446,7 +446,7 @@ static struct s32k3xx_lpspidev_s g_lpspi4dev =
{
.spidev =
{
&g_spi4ops
.ops = &g_spi4ops,
},
.spibase = S32K3XX_LPSPI4_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@ -496,7 +496,7 @@ static struct s32k3xx_lpspidev_s g_lpspi5dev =
{
.spidev =
{
&g_spi5ops
.ops = &g_spi5ops,
},
.spibase = S32K3XX_LPSPI5_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@ -1535,8 +1535,8 @@ static void s32k3xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
* take care of big endian mode of hardware !!
*/
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *) rxbuffer;
const uint8_t *src = txbuffer;
uint8_t *dest = rxbuffer;
uint32_t word = 0x0;
#ifdef CONFIG_S32K3XX_LPSPI_DWORD
uint32_t word1 = 0x0;
@ -1613,8 +1613,8 @@ static void s32k3xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 32-bit or 64 bit, word size memory transfers */
const uint32_t *src = (const uint32_t *)txbuffer;
uint32_t *dest = (uint32_t *) rxbuffer;
const uint32_t *src = txbuffer;
uint32_t *dest = rxbuffer;
uint32_t word = 0x0;
#ifdef CONFIG_S32K3XX_LPSPI_DWORD
uint32_t word1 = 0x0;
@ -1694,8 +1694,8 @@ static void s32k3xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;
uint16_t *dest = (uint16_t *) rxbuffer;
const uint16_t *src = txbuffer;
uint16_t *dest = rxbuffer;
uint16_t word;
while (nwords-- > 0)
@ -1729,8 +1729,8 @@ static void s32k3xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *) rxbuffer;
const uint8_t *src = txbuffer;
uint8_t *dest = rxbuffer;
uint8_t word;
while (nwords-- > 0)
@ -1786,12 +1786,12 @@ static void s32k3xx_lpspi_exchange(struct spi_dev_s *dev,
const void *txbuffer, void *rxbuffer,
size_t nwords)
{
int ret;
size_t adjust;
ssize_t nbytes;
static uint8_t rxdummy[4] aligned_data(4);
static const uint16_t txdummy = 0xffff;
uint32_t regval;
int ret;
size_t adjust;
ssize_t nbytes;
static uint8_t rxdummy[4] aligned_data(4);
static const uint16_t txdummy = 0xffff;
uint32_t regval;
struct s32k3xx_lpspidev_s *priv = (struct s32k3xx_lpspidev_s *)dev;
DEBUGASSERT(priv != NULL);

2
arch/arm/src/s32k3xx/s32k3xx_qspi.c
View File

@ -221,7 +221,7 @@ static const struct qspi_ops_s g_qspi0ops =
static struct s32k3xx_qspidev_s g_qspi0dev =
{
.qspi =
.qspi =
{
.ops = &g_qspi0ops,
},

12
arch/arm/src/sam34/sam_twi.c
View File

@ -172,16 +172,16 @@ static void twi_startmessage(struct twi_dev_s *priv, struct i2c_msg_s *msg);
/* I2C device operations */
static int twi_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int twi_reset(struct i2c_master_s * dev);
static int twi_reset(struct i2c_master_s *dev);
#endif
/* Initialization */
static void twi_setfrequency(struct twi_dev_s *priv, uint32_t frequency);
static void twi_hw_initialize(struct twi_dev_s *priv, unsigned int pid,
uint32_t frequency);
uint32_t frequency);
/****************************************************************************
* Private Data
@ -747,7 +747,7 @@ static int twi_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int twi_reset(struct i2c_master_s * dev)
static int twi_reset(struct i2c_master_s *dev)
{
return OK;
}
@ -982,9 +982,9 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
*
****************************************************************************/
int sam_i2cbus_uninitialize(struct i2c_master_s * dev)
int sam_i2cbus_uninitialize(struct i2c_master_s *dev)
{
struct twi_dev_s *priv = (struct twi_dev_s *) dev;
struct twi_dev_s *priv = (struct twi_dev_s *)dev;
i2cinfo("TWI%d Un-initializing\n", priv->twi);

2
arch/arm/src/sama5/sam_ohci.c
View File

@ -3114,7 +3114,7 @@ static int sam_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
struct sam_rhport_s *rhport = (struct sam_rhport_s *)drvr;
struct sam_eplist_s *eplist = (struct sam_eplist_s *)ep0;
uint16_t len;
int ret;
int ret;
DEBUGASSERT(rhport != NULL && eplist != NULL && req != NULL);

21
arch/arm/src/sama5/sam_sdmmc.c
View File

@ -378,7 +378,7 @@ struct sam_dev_s g_sdmmcdev[SAM_MAX_SDMMC_DEV_SLOTS] =
.sw_cd_gpio = PIN_SDMMC0_CD_GPIO,
#endif
#if defined(CONFIG_SAMA5_SDMMC0_INVERT_CD)
.cd_invert = true,
.cd_invert = true,
#endif
.dev =
{
@ -437,7 +437,7 @@ struct sam_dev_s g_sdmmcdev[SAM_MAX_SDMMC_DEV_SLOTS] =
.sw_cd_gpio = PIN_SDMMC1_CD_GPIO,
#endif
#if defined(CONFIG_SAMA5_SDMMC1_INVERT_CD)
.cd_invert = true,
.cd_invert = true,
#endif
.dev =
{
@ -1111,7 +1111,7 @@ static void sam_receive(struct sam_dev_s *priv)
{
/* Transfer any trailing fractional word */
uint8_t *ptr = (uint8_t *) priv->buffer;
uint8_t *ptr = (uint8_t *)priv->buffer;
int i;
for (i = 0; i < priv->remaining; i++)
@ -1873,7 +1873,7 @@ static void sam_frequency(struct sdio_dev_s *dev, uint32_t frequency)
static void sam_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate)
{
struct sam_dev_s *priv = (struct sam_dev_s *) dev;
struct sam_dev_s *priv = (struct sam_dev_s *)dev;
uint32_t regval;
int wait_microseconds = 0;
@ -2354,7 +2354,7 @@ static int sam_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer,
* handler and DMA memory invalidation.
*/
priv->buffer = (uint32_t *) buffer;
priv->buffer = (uint32_t *)buffer;
priv->remaining = nbytes;
/* Then set up the SDIO data path */
@ -2408,7 +2408,8 @@ static int sam_sendsetup(struct sdio_dev_s *dev,
/* Save the source buffer information for use by the interrupt handler */
priv->buffer = (uint32_t *) buffer; priv->remaining = nbytes;
priv->buffer = (uint32_t *)buffer;
priv->remaining = nbytes;
/* Then set up the SDIO data path */
@ -3052,7 +3053,7 @@ static int sam_dmarecvsetup(struct sdio_dev_s *dev,
* handler
*/
priv->buffer = (uint32_t *) buffer;
priv->buffer = (uint32_t *)buffer;
priv->remaining = buflen;
priv->bufferend = (uint32_t *)(buffer + buflen);
@ -3122,7 +3123,7 @@ static int sam_dmasendsetup(struct sdio_dev_s *dev,
/* Save the source buffer information for use by the interrupt handler */
priv->buffer = (uint32_t *) buffer;
priv->buffer = (uint32_t *)buffer;
priv->remaining = buflen;
priv->bufferend = (uint32_t *)(buffer + buflen);
@ -3610,8 +3611,8 @@ struct sdio_dev_s *sam_sdmmc_sdio_initialize(int slotno)
sam_configpio(PIO_SDMMC0_CK);
sam_configpio(PIO_SDMMC0_CMD);
# if ( defined(CONFIG_SAMA5_SDMMC0_WIDTH_D1_D4) || \
defined(CONFIG_SAMA5_SDMMC0_WIDTH_D1_D8) )
# if (defined(CONFIG_SAMA5_SDMMC0_WIDTH_D1_D4) || \
defined(CONFIG_SAMA5_SDMMC0_WIDTH_D1_D8))
sam_configpio(PIO_SDMMC0_DAT1);
sam_configpio(PIO_SDMMC0_DAT2);
sam_configpio(PIO_SDMMC0_DAT3);

6
arch/arm/src/sama5/sam_twi.c
View File

@ -215,9 +215,9 @@ static void twi_startmessage(struct twi_dev_s *priv, struct i2c_msg_s *msg);
/* I2C device operations */
static int twi_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int twi_reset(struct i2c_master_s * dev);
static int twi_reset(struct i2c_master_s *dev);
#endif
/* Initialization */
@ -1289,7 +1289,7 @@ errout_with_lock:
int sam_i2cbus_uninitialize(struct i2c_master_s *dev)
{
struct twi_dev_s *priv = (struct twi_dev_s *) dev;
struct twi_dev_s *priv = (struct twi_dev_s *)dev;
i2cinfo("TWI%d Un-initializing\n", priv->attr->twi);

4
arch/arm/src/sama5/sam_xdmac.c
View File

@ -548,7 +548,7 @@ static struct sam_xdmac_s g_xdmac0 =
/* This array describes the available link list descriptors */
.descr = g_desc0,
.descr = g_desc0,
/* This array describes each DMA channel */
@ -725,7 +725,7 @@ static struct sam_xdmac_s g_xdmac1 =
/* This array describes the available link list descriptors */
.descr = g_desc1,
.descr = g_desc1,
/* This array describes each DMA channel */

4
arch/arm/src/samd2l2/sam_spi.c
View File

@ -1174,8 +1174,8 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
/* Start RX and TX DMA channels */
sam_dmastart(priv->dma_tx, spi_dma_callback, (void *)priv);
sam_dmastart(priv->dma_rx, spi_dma_callback, (void *)priv);
sam_dmastart(priv->dma_tx, spi_dma_callback, priv);
sam_dmastart(priv->dma_rx, spi_dma_callback, priv);
/* Enable SPI to trigger the TX DMA channel */

4
arch/arm/src/samd5e5/sam_spi.c
View File

@ -1270,8 +1270,8 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
/* Start RX and TX DMA channels */
sam_dmastart(priv->dma_tx, spi_dma_callback, (void *)priv);
sam_dmastart(priv->dma_rx, spi_dma_callback, (void *)priv);
sam_dmastart(priv->dma_tx, spi_dma_callback, priv);
sam_dmastart(priv->dma_rx, spi_dma_callback, priv);
/* Enable SPI to trigger the TX DMA channel */

24
arch/arm/src/samd5e5/sam_usb.c
View File

@ -1012,8 +1012,8 @@ static struct sam_usbhost_s g_usbhost =
static struct usbhost_connection_s g_usbconn =
{
.wait = sam_wait,
.enumerate = sam_enumerate,
.wait = sam_wait,
.enumerate = sam_enumerate,
};
#endif
@ -3134,16 +3134,16 @@ static void sam_setdevaddr(struct sam_usbdev_s *priv, uint8_t address)
static void sam_ep0_setup(struct sam_usbdev_s *priv)
{
struct sam_ep_s *ep0 = &priv->eplist[EP0];
struct sam_ep_s *privep;
union wb_u value;
union wb_u index;
union wb_u len;
union wb_u response;
enum sam_ep0setup_e ep0result;
uint8_t epno;
int nbytes = 0; /* Assume zero-length packet */
int ret;
struct sam_ep_s *ep0 = &priv->eplist[EP0];
struct sam_ep_s *privep;
union wb_u value;
union wb_u index;
union wb_u len;
union wb_u response;
enum sam_ep0setup_e ep0result;
uint8_t epno;
int nbytes = 0; /* Assume zero-length packet */
int ret;
/* Terminate any pending requests */

8
arch/arm/src/samv7/sam_mcan.c
View File

@ -384,7 +384,7 @@
(MCAN0_TXEVENTFIFO_BYTES >> 2)
# define MCAN0_TXFIFIOQ_BYTES \
MCAN_ALIGN_UP(CONFIG_SAMV7_MCAN0_TXFIFOQ_SIZE * \
MCAN_ALIGN_UP(CONFIG_SAMV7_MCAN0_TXFIFOQ_SIZE * \
(MCAN0_TXBUFFER_ELEMENT_SIZE + 8))
# define MCAN0_TXFIFIOQ_WORDS (MCAN0_TXFIFIOQ_BYTES >> 2)
@ -669,7 +669,7 @@
(MCAN1_TXEVENTFIFO_BYTES >> 2)
# define MCAN1_TXFIFIOQ_BYTES \
MCAN_ALIGN_UP(CONFIG_SAMV7_MCAN1_TXFIFOQ_SIZE * \
MCAN_ALIGN_UP(CONFIG_SAMV7_MCAN1_TXFIFOQ_SIZE * \
(MCAN1_TXBUFFER_ELEMENT_SIZE + 8))
# define MCAN1_TXFIFIOQ_WORDS (MCAN1_TXFIFIOQ_BYTES >> 2)
@ -1006,7 +1006,7 @@ static uint32_t g_mcan0_msgram[MCAN0_MSGRAM_WORDS]
/* Constant configuration */
static struct sam_config_s g_mcan0const =
static const struct sam_config_s g_mcan0const =
{
.rxpinset = GPIO_MCAN0_RX,
.txpinset = GPIO_MCAN0_TX,
@ -1104,7 +1104,7 @@ static uint32_t g_mcan1_msgram[MCAN1_MSGRAM_WORDS]
/* MCAN1 constant configuration */
static struct sam_config_s g_mcan1const =
static const struct sam_config_s g_mcan1const =
{
.rxpinset = GPIO_MCAN1_RX,
.txpinset = GPIO_MCAN1_TX,

4
arch/arm/src/samv7/sam_qspi.c
View File

@ -302,7 +302,7 @@ static const struct qspi_ops_s g_qspi0ops =
static struct sam_qspidev_s g_qspi0dev =
{
.qspi =
.qspi =
{
.ops = &g_qspi0ops,
},
@ -856,7 +856,7 @@ static int qspi_memory_dma(struct sam_qspidev_s *priv,
/* Start the DMA */
priv->result = -EBUSY;
ret = sam_dmastart(priv->dmach, qspi_dma_callback, (void *)priv);
ret = sam_dmastart(priv->dmach, qspi_dma_callback, priv);
if (ret < 0)
{
spierr("ERROR: sam_dmastart failed: %d\n", ret);

10
arch/arm/src/samv7/sam_spi_slave.c
View File

@ -170,11 +170,11 @@ static const uint8_t g_csroffset[4] =
static const struct spi_slave_ctrlrops_s g_ctrlr_ops =
{
.bind = spi_bind,
.unbind = spi_unbind,
.enqueue = spi_enqueue,
.qfull = spi_qfull,
.qflush = spi_qflush,
.bind = spi_bind,
.unbind = spi_unbind,
.enqueue = spi_enqueue,
.qfull = spi_qfull,
.qflush = spi_qflush,
};
#ifdef CONFIG_SAMV7_SPI0_SLAVE

8
arch/arm/src/samv7/sam_twihs.c
View File

@ -214,10 +214,10 @@ static void twi_startmessage(struct twi_dev_s *priv, struct i2c_msg_s *msg);
/* I2C device operations */
static int twi_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int twi_reset_internal(struct i2c_master_s *dev);
static int twi_reset(struct i2c_master_s * dev);
static int twi_reset_internal(struct i2c_master_s *dev);
static int twi_reset(struct i2c_master_s *dev);
#endif
/* Initialization */
@ -1461,7 +1461,7 @@ errout_with_lock:
int sam_i2cbus_uninitialize(struct i2c_master_s *dev)
{
struct twi_dev_s *priv = (struct twi_dev_s *) dev;
struct twi_dev_s *priv = (struct twi_dev_s *)dev;
DEBUGASSERT(priv);

2
arch/arm/src/samv7/sam_xdmac.c
View File

@ -189,7 +189,7 @@ static const struct sam_pidmap_s g_xdmac_txchan[] =
/* This array describes the available link list descriptors */
struct chnext_view1_s g_lldesc[CONFIG_SAMV7_NLLDESC];
static struct chnext_view1_s g_lldesc[CONFIG_SAMV7_NLLDESC];
/* This array describes the state of each XDMAC channel 0 */

4
arch/arm/src/stm32/stm32_1wire.c
View File

@ -129,8 +129,8 @@ struct stm32_1wire_priv_s
struct stm32_1wire_inst_s
{
const struct onewire_ops_s *ops; /* Standard 1-Wire operations */
struct stm32_1wire_priv_s *priv; /* Common driver private data structure */
const struct onewire_ops_s *ops; /* Standard 1-Wire operations */
struct stm32_1wire_priv_s *priv; /* Common driver private data structure */
};
/****************************************************************************

2
arch/arm/src/stm32/stm32_adc.c
View File

@ -1348,7 +1348,7 @@ static int adc_timinit(struct stm32_dev_s *priv)
* 0 <= prescaler <= 65536
* 1 <= reload <= 65535
*
* So ( prescaler = pclck / 65535 / freq ) would be optimal.
* So (prescaler = pclck / 65535 / freq) would be optimal.
*/
prescaler = (priv->pclck / priv->freq + 65534) / 65535;

23
arch/arm/src/stm32/stm32_dma2d.c
View File

@ -110,7 +110,6 @@ struct stm32_dma2d_s
#ifdef CONFIG_STM32_FB_CMAP
uint32_t *clut; /* Color lookup table */
#endif
mutex_t *lock; /* Ensure mutually exclusive access */
};
@ -463,8 +462,8 @@ static int stm32_dma2d_waitforirq(void)
#ifdef CONFIG_STM32_DMA2D_L8
static int stm32_dma2d_loadclut(uintptr_t pfcreg)
{
int ret;
uint32_t regval;
int ret;
uint32_t regval;
/* Start clut loading */
@ -497,7 +496,7 @@ static int stm32_dma2d_loadclut(uintptr_t pfcreg)
static int stm32_dma2d_start(void)
{
int ret;
int ret;
/* Start dma transfer */
@ -683,7 +682,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha,
#ifdef CONFIG_STM32_FB_CMAP
if (fmt == DMA2D_PF_L8)
{
struct stm32_dma2d_s * layer = &g_dma2ddev;
struct stm32_dma2d_s *layer = &g_dma2ddev;
/* Load CLUT automatically */
@ -747,7 +746,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha,
static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap)
{
int n;
struct stm32_dma2d_s * priv = &g_dma2ddev;
struct stm32_dma2d_s *priv = &g_dma2ddev;
lcdinfo("cmap=%p\n", cmap);
@ -816,7 +815,7 @@ static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo,
uint32_t argb)
{
int ret;
struct stm32_dma2d_s * priv = &g_dma2ddev;
struct stm32_dma2d_s *priv = &g_dma2ddev;
DEBUGASSERT(oinfo != NULL && oinfo->oinfo != NULL && area != NULL);
lcdinfo("oinfo=%p, argb=%08" PRIx32 "\n", oinfo, argb);
@ -897,9 +896,9 @@ static int stm32_dma2d_blit(struct stm32_dma2d_overlay_s *doverlay,
struct stm32_dma2d_overlay_s *soverlay,
const struct fb_area_s *sarea)
{
int ret;
uint32_t mode;
struct stm32_dma2d_s * priv = &g_dma2ddev;
int ret;
uint32_t mode;
struct stm32_dma2d_s *priv = &g_dma2ddev;
lcdinfo("doverlay=%p, destxpos=%" PRId32 ", destypos=%" PRId32
", soverlay=%p, sarea=%p\n",
@ -997,8 +996,8 @@ static int stm32_dma2d_blend(struct stm32_dma2d_overlay_s *doverlay,
struct stm32_dma2d_overlay_s *boverlay,
const struct fb_area_s *barea)
{
int ret;
struct stm32_dma2d_s * priv = &g_dma2ddev;
int ret;
struct stm32_dma2d_s *priv = &g_dma2ddev;
lcdinfo("doverlay=%p, destxpos=%" PRId32 ", destypos=%" PRId32 ", "
"foverlay=%p, forexpos=%" PRId32 ", foreypos=%" PRId32 ", "

10
arch/arm/src/stm32/stm32_foc.c
View File

@ -1136,7 +1136,7 @@ static int stm32_foc_adc_start(struct foc_dev_s *dev, bool state)
static int stm32_foc_adc_cfg(struct foc_dev_s *dev)
{
struct stm32_foc_dev_s *foc_dev = STM32_FOC_DEV_FROM_DEV_GET(dev);
struct stm32_foc_dev_s *foc_dev = STM32_FOC_DEV_FROM_DEV_GET(dev);
DEBUGASSERT(dev);
DEBUGASSERT(foc_dev);
@ -1452,10 +1452,10 @@ errout:
static int stm32_foc_shutdown(struct foc_dev_s *dev)
{
struct stm32_foc_dev_s *foc_dev = STM32_FOC_DEV_FROM_DEV_GET(dev);
struct stm32_foc_board_s *board = STM32_FOC_BOARD_FROM_DEV_GET(dev);
struct stm32_foc_priv_s *priv = STM32_FOC_PRIV_FROM_DEV_GET(dev);
int ret = OK;
struct stm32_foc_dev_s *foc_dev = STM32_FOC_DEV_FROM_DEV_GET(dev);
struct stm32_foc_board_s *board = STM32_FOC_BOARD_FROM_DEV_GET(dev);
struct stm32_foc_priv_s *priv = STM32_FOC_PRIV_FROM_DEV_GET(dev);
int ret = OK;
DEBUGASSERT(dev);
DEBUGASSERT(foc_dev);

98
arch/arm/src/stm32/stm32_hciuart.c
View File

@ -369,20 +369,20 @@ static struct hciuart_state_s g_hciusart1_state =
static const struct hciuart_config_s g_hciusart1_config =
{
.lower =
{
.rxattach = hciuart_rxattach,
.rxenable = hciuart_rxenable,
.setbaud = hciuart_setbaud,
.read = hciuart_read,
.write = hciuart_write,
.rxdrain = hciuart_rxdrain,
},
{
.rxattach = hciuart_rxattach,
.rxenable = hciuart_rxenable,
.setbaud = hciuart_setbaud,
.read = hciuart_read,
.write = hciuart_write,
.rxdrain = hciuart_rxdrain,
},
.state = &g_hciusart1_state,
.rxbuffer = g_usart1_rxbuffer,
.txbuffer = g_usart1_txbuffer,
#ifdef CONFIG_STM32_HCIUART1_RXDMA
.rxdmabuffer = ,
.rxdmabuffer = g_usart1_rxdmabuffer,
#endif
.rxbufsize = CONFIG_STM32_HCIUART1_RXBUFSIZE,
.txbufsize = CONFIG_STM32_HCIUART1_TXBUFSIZE,
@ -433,14 +433,14 @@ static struct hciuart_state_s g_hciusart2_state =
static const struct hciuart_config_s g_hciusart2_config =
{
.lower =
{
.rxattach = hciuart_rxattach,
.rxenable = hciuart_rxenable,
.setbaud = hciuart_setbaud,
.read = hciuart_read,
.write = hciuart_write,
.rxdrain = hciuart_rxdrain,
},
{
.rxattach = hciuart_rxattach,
.rxenable = hciuart_rxenable,
.setbaud = hciuart_setbaud,
.read = hciuart_read,
.write = hciuart_write,
.rxdrain = hciuart_rxdrain,
},
.state = &g_hciusart2_state,
.rxbuffer = g_usart2_rxbuffer,
@ -493,14 +493,14 @@ static struct hciuart_state_s g_hciusart3_state =
static const struct hciuart_config_s g_hciusart3_config =
{
.lower =
{
.rxattach = hciuart_rxattach,
.rxenable = hciuart_rxenable,
.setbaud = hciuart_setbaud,
.read = hciuart_read,
.write = hciuart_write,
.rxdrain = hciuart_rxdrain,
},
{
.rxattach = hciuart_rxattach,
.rxenable = hciuart_rxenable,
.setbaud = hciuart_setbaud,
.read = hciuart_read,
.write = hciuart_write,
.rxdrain = hciuart_rxdrain,
},
.state = &g_hciusart3_state,
.rxbuffer = g_usart3_rxbuffer,
@ -555,14 +555,14 @@ static struct hciuart_state_s g_hciusart6_state =
static const struct hciuart_config_s g_hciusart6_config =
{
.lower =
{
.rxattach = hciuart_rxattach,
.rxenable = hciuart_rxenable,
.setbaud = hciuart_setbaud,
.read = hciuart_read,
.write = hciuart_write,
.rxdrain = hciuart_rxdrain,
},
{
.rxattach = hciuart_rxattach,
.rxenable = hciuart_rxenable,
.setbaud = hciuart_setbaud,
.read = hciuart_read,
.write = hciuart_write,
.rxdrain = hciuart_rxdrain,
},
.state = &g_hciusart6_state,
.rxbuffer = g_usart6_rxbuffer,
@ -615,14 +615,14 @@ static struct hciuart_state_s g_hciuart7_state =
static const struct hciuart_config_s g_hciuart7_config =
{
.lower =
{
.rxattach = hciuart_rxattach,
.rxenable = hciuart_rxenable,
.setbaud = hciuart_setbaud,
.read = hciuart_read,
.write = hciuart_write,
.rxdrain = hciuart_rxdrain,
},
{
.rxattach = hciuart_rxattach,
.rxenable = hciuart_rxenable,
.setbaud = hciuart_setbaud,
.read = hciuart_read,
.write = hciuart_write,
.rxdrain = hciuart_rxdrain,
},
.state = &g_hciuart7_state,
.rxbuffer = g_uart7_rxbuffer,
@ -675,14 +675,14 @@ static struct hciuart_state_s g_hciuart8_state =
static const struct hciuart_config_s g_hciuart8_config =
{
.lower =
{
.rxattach = hciuart_rxattach,
.rxenable = hciuart_rxenable,
.setbaud = hciuart_setbaud,
.read = hciuart_read,
.write = hciuart_write,
.rxdrain = hciuart_rxdrain,
},
{
.rxattach = hciuart_rxattach,
.rxenable = hciuart_rxenable,
.setbaud = hciuart_setbaud,
.read = hciuart_read,
.write = hciuart_write,
.rxdrain = hciuart_rxdrain,
},
.state = &g_hciuart8_state,
.rxbuffer = g_uart8_rxbuffer,

4
arch/arm/src/stm32/stm32_i2c_alt.c
View File

@ -10,7 +10,7 @@
* Copyright (C) 2011-2014, 2016-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Copyright( C) 2014 Patrizio Simona. All rights reserved.
* Copyright (C) 2014 Patrizio Simona. All rights reserved.
* Author: Patrizio Simona <psimona@ethz.ch>
*
* Redistribution and use in source and binary forms, with or without
@ -2233,7 +2233,7 @@ static int stm32_i2c_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int stm32_i2c_reset(struct i2c_master_s * dev)
static int stm32_i2c_reset(struct i2c_master_s *dev)
{
struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev;
unsigned int clock_count;

15
arch/arm/src/stm32/stm32_i2c_v2.c
View File

@ -473,7 +473,7 @@ static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv);
static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv);
static inline
uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv);
static int stm32_i2c_isr_process(struct stm32_i2c_priv_s * priv);
static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv);
#ifndef CONFIG_I2C_POLLED
static int stm32_i2c_isr(int irq, void *context, void *arg);
#endif
@ -485,7 +485,7 @@ static int stm32_i2c_process(struct i2c_master_s *dev,
static int stm32_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int stm32_i2c_reset(struct i2c_master_s * dev);
static int stm32_i2c_reset(struct i2c_master_s *dev);
#endif
#ifdef CONFIG_PM
static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain,
@ -2468,11 +2468,18 @@ static int stm32_i2c_process(struct i2c_master_s *dev,
static int stm32_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count)
{
struct stm32_i2c_priv_s *priv;
int ret;
DEBUGASSERT(dev);
/* Get I2C private structure */
priv = ((struct stm32_i2c_inst_s *)dev)->priv;
/* Ensure that address or flags don't change meanwhile */
ret = nxmutex_lock(&((struct stm32_i2c_inst_s *)dev)->priv->lock);
ret = nxmutex_lock(&priv->lock);
if (ret >= 0)
{
ret = stm32_i2c_process(dev, msgs, count);
@ -2490,7 +2497,7 @@ static int stm32_i2c_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int stm32_i2c_reset(struct i2c_master_s * dev)
static int stm32_i2c_reset(struct i2c_master_s *dev)
{
struct stm32_i2c_priv_s *priv;
unsigned int clock_count;

32
arch/arm/src/stm32/stm32_ltdc.c
View File

@ -682,7 +682,7 @@ static int stm32_ltdc_reload(uint8_t value, bool waitvblank);
static void stm32_ltdc_lpixelformat(struct stm32_ltdc_s *layer);
static void stm32_ltdc_lframebuffer(struct stm32_ltdc_s *layer);
static void stm32_ltdc_lenable(struct stm32_ltdc_s *layer, bool enable);
static void stm32_ltdc_ldefaultcolor(struct stm32_ltdc_s * layer,
static void stm32_ltdc_ldefaultcolor(struct stm32_ltdc_s *layer,
uint32_t rgb);
static void stm32_ltdc_ltransp(struct stm32_ltdc_s *layer,
uint8_t transp,
@ -703,9 +703,9 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer,
#endif
#ifdef CONFIG_STM32_FB_CMAP
static void stm32_ltdc_lputclut(struct stm32_ltdc_s * layer,
static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer,
const struct fb_cmap_s *cmap);
static void stm32_ltdc_lgetclut(struct stm32_ltdc_s * layer,
static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer,
struct fb_cmap_s *cmap);
static void stm32_ltdc_lclutenable(struct stm32_ltdc_s *layer,
bool enable);
@ -1339,7 +1339,7 @@ static void stm32_ltdc_periphconfig(void)
*
****************************************************************************/
static void stm32_ltdc_ldefaultcolor(struct stm32_ltdc_s * layer,
static void stm32_ltdc_ldefaultcolor(struct stm32_ltdc_s *layer,
uint32_t rgb)
{
DEBUGASSERT(layer->layerno < LTDC_NLAYERS);
@ -2079,8 +2079,8 @@ static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer,
*
****************************************************************************/
static void stm32_ltdc_lgetclut(struct stm32_ltdc_s * layer,
struct fb_cmap_s * cmap)
static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer,
struct fb_cmap_s *cmap)
{
int n;
struct fb_cmap_s *priv_cmap = &g_vtable.cmap;
@ -2401,7 +2401,7 @@ static int stm32_getcmap(struct fb_vtable_s *vtable,
* from the main overlay.
*/
struct stm32_ltdc_s * layer;
struct stm32_ltdc_s *layer;
# ifdef CONFIG_STM32_LTDC_L2
layer = &priv->layer[LTDC_LAYER_L2];
# else
@ -2488,7 +2488,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable,
for (n = 0; n < LTDC_NLAYERS; n++)
{
struct stm32_ltdc_s * layer = &priv->layer[n];
struct stm32_ltdc_s *layer = &priv->layer[n];
stm32_ltdc_lputclut(layer, priv_cmap);
}
@ -2545,7 +2545,7 @@ static int stm32_getoverlayinfo(struct fb_vtable_s *vtable,
if (overlayno < LTDC_NOVERLAYS)
{
struct stm32_ltdc_s * layer = &priv->layer[overlayno];
struct stm32_ltdc_s *layer = &priv->layer[overlayno];
memcpy(oinfo, &layer->oinfo, sizeof(struct fb_overlayinfo_s));
return OK;
}
@ -2577,7 +2577,7 @@ static int stm32_settransp(struct fb_vtable_s *vtable,
if (oinfo->overlay < LTDC_NOVERLAYS)
{
struct stm32_ltdc_s * layer = &priv->layer[oinfo->overlay];
struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay];
nxmutex_lock(layer->lock);
layer->oinfo.transp.transp = oinfo->transp.transp;
@ -2628,7 +2628,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable,
if (oinfo->overlay < LTDC_NLAYERS)
{
int ret;
struct stm32_ltdc_s * layer = &priv->layer[oinfo->overlay];
struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay];
# ifndef CONFIG_STM32_LTDC_L1_CHROMAKEY
if (oinfo->overlay == LTDC_LAYER_L1)
@ -2703,8 +2703,8 @@ static int stm32_setcolor(struct fb_vtable_s *vtable,
int ret;
struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)
vtable;
struct stm32_ltdc_s * layer = &priv->layer[oinfo->overlay];
struct fb_overlayinfo_s * poverlay = layer->dma2dinfo.oinfo;
struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay];
struct fb_overlayinfo_s *poverlay = layer->dma2dinfo.oinfo;
DEBUGASSERT(&layer->oinfo == poverlay);
@ -2743,7 +2743,7 @@ static int stm32_setblank(struct fb_vtable_s *vtable,
if (oinfo->overlay < LTDC_NLAYERS)
{
struct stm32_ltdc_s * layer = &priv->layer[oinfo->overlay];
struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay];
nxmutex_lock(layer->lock);
layer->oinfo.blank = oinfo->blank;
@ -2794,7 +2794,7 @@ static int stm32_setarea(struct fb_vtable_s *vtable,
{
struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)
vtable;
struct stm32_ltdc_s * layer = &priv->layer[oinfo->overlay];
struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay];
nxmutex_lock(layer->lock);
memcpy(&layer->oinfo.sarea, &oinfo->sarea, sizeof(struct fb_area_s));
@ -2968,7 +2968,7 @@ void stm32_ltdcreset(void)
int stm32_ltdcinitialize(void)
{
int ret = OK;
int ret = OK;
lcdinfo("Initialize LTDC driver\n");

6
arch/arm/src/stm32/stm32_otgfshost.c
View File

@ -484,8 +484,8 @@ static struct stm32_usbhost_s g_usbhost =
static struct usbhost_connection_s g_usbconn =
{
.wait = stm32_wait,
.enumerate = stm32_enumerate,
.wait = stm32_wait,
.enumerate = stm32_enumerate,
};
/****************************************************************************
@ -5271,7 +5271,7 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv)
struct stm32_chan_s *chan = &priv->chan[i];
chan->chidx = i;
nxsem_init(&chan->waitsem, 0, 0);
nxsem_init(&chan->waitsem, 0, 0);
}
}

6
arch/arm/src/stm32/stm32_otghshost.c
View File

@ -489,8 +489,8 @@ static struct stm32_usbhost_s g_usbhost =
static struct usbhost_connection_s g_usbconn =
{
.wait = stm32_wait,
.enumerate = stm32_enumerate,
.wait = stm32_wait,
.enumerate = stm32_enumerate,
};
/****************************************************************************
@ -5270,7 +5270,7 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv)
struct stm32_chan_s *chan = &priv->chan[i];
chan->chidx = i;
nxsem_init(&chan->waitsem, 0, 0);
nxsem_init(&chan->waitsem, 0, 0);
}
}

2
arch/arm/src/stm32/stm32_rtc_lowerhalf.c
View File

@ -158,7 +158,7 @@ static const struct rtc_ops_s g_rtc_ops =
static struct stm32_lowerhalf_s g_rtc_lowerhalf =
{
.ops = &g_rtc_ops,
.ops = &g_rtc_ops,
.devlock = NXMUTEX_INITIALIZER,
};

48
arch/arm/src/stm32/stm32_spi.c
View File

@ -349,9 +349,9 @@ static uint8_t g_spi1_rxbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN;
static struct stm32_spidev_s g_spi1dev =
{
.spidev =
{
&g_sp1iops
},
{
.ops = &g_sp1iops
},
.spibase = STM32_SPI1_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
#ifdef CONFIG_STM32_SPI_INTERRUPTS
@ -361,7 +361,7 @@ static struct stm32_spidev_s g_spi1dev =
# ifdef CONFIG_STM32_SPI1_DMA
.rxch = DMACHAN_SPI1_RX,
.txch = DMACHAN_SPI1_TX,
#if defined(SPI1_DMABUFSIZE_ADJUSTED)
# ifdef SPI1_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi1_rxbuf,
.txbuf = g_spi1_txbuf,
.buflen = SPI1_DMABUFSIZE_ADJUSTED,
@ -417,9 +417,9 @@ static uint8_t g_spi2_rxbuf[SPI2_DMABUFSIZE_ADJUSTED] SPI2_DMABUFSIZE_ALGN;
static struct stm32_spidev_s g_spi2dev =
{
.spidev =
{
&g_sp2iops
},
{
.ops = &g_sp2iops
},
.spibase = STM32_SPI2_BASE,
.spiclock = STM32_PCLK1_FREQUENCY,
#ifdef CONFIG_STM32_SPI_INTERRUPTS
@ -429,7 +429,7 @@ static struct stm32_spidev_s g_spi2dev =
# ifdef CONFIG_STM32_SPI2_DMA
.rxch = DMACHAN_SPI2_RX,
.txch = DMACHAN_SPI2_TX,
#if defined(SPI2_DMABUFSIZE_ADJUSTED)
# ifdef SPI2_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi2_rxbuf,
.txbuf = g_spi2_txbuf,
.buflen = SPI2_DMABUFSIZE_ADJUSTED,
@ -485,9 +485,9 @@ static uint8_t g_spi3_rxbuf[SPI3_DMABUFSIZE_ADJUSTED] SPI3_DMABUFSIZE_ALGN;
static struct stm32_spidev_s g_spi3dev =
{
.spidev =
{
&g_sp3iops
},
{
.ops = &g_sp3iops
},
.spibase = STM32_SPI3_BASE,
.spiclock = STM32_PCLK1_FREQUENCY,
#ifdef CONFIG_STM32_SPI_INTERRUPTS
@ -497,7 +497,7 @@ static struct stm32_spidev_s g_spi3dev =
# ifdef CONFIG_STM32_SPI3_DMA
.rxch = DMACHAN_SPI3_RX,
.txch = DMACHAN_SPI3_TX,
#if defined(SPI3_DMABUFSIZE_ADJUSTED)
# ifdef SPI3_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi3_rxbuf,
.txbuf = g_spi3_txbuf,
.buflen = SPI3_DMABUFSIZE_ADJUSTED,
@ -553,9 +553,9 @@ static uint8_t g_spi4_rxbuf[SPI4_DMABUFSIZE_ADJUSTED] SPI4_DMABUFSIZE_ALGN;
static struct stm32_spidev_s g_spi4dev =
{
.spidev =
{
&g_sp4iops
},
{
.ops = &g_sp4iops
},
.spibase = STM32_SPI4_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
#ifdef CONFIG_STM32_SPI_INTERRUPTS
@ -565,7 +565,7 @@ static struct stm32_spidev_s g_spi4dev =
# ifdef CONFIG_STM32_SPI4_DMA
.rxch = DMACHAN_SPI4_RX,
.txch = DMACHAN_SPI4_TX,
#if defined(SPI4_DMABUFSIZE_ADJUSTED)
# ifdef SPI4_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi4_rxbuf,
.txbuf = g_spi4_txbuf,
.buflen = SPI4_DMABUFSIZE_ADJUSTED,
@ -621,9 +621,9 @@ static uint8_t g_spi5_rxbuf[SPI5_DMABUFSIZE_ADJUSTED] SPI5_DMABUFSIZE_ALGN;
static struct stm32_spidev_s g_spi5dev =
{
.spidev =
{
&g_sp5iops
},
{
.ops = &g_sp5iops
},
.spibase = STM32_SPI5_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
#ifdef CONFIG_STM32_SPI_INTERRUPTS
@ -633,7 +633,7 @@ static struct stm32_spidev_s g_spi5dev =
# ifdef CONFIG_STM32_SPI5_DMA
.rxch = DMACHAN_SPI5_RX,
.txch = DMACHAN_SPI5_TX,
#if defined(SPI5_DMABUFSIZE_ADJUSTED)
# ifdef SPI5_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi5_rxbuf,
.txbuf = g_spi5_txbuf,
.buflen = SPI5_DMABUFSIZE_ADJUSTED,
@ -689,9 +689,9 @@ static uint8_t g_spi6_rxbuf[SPI6_DMABUFSIZE_ADJUSTED] SPI6_DMABUFSIZE_ALGN;
static struct stm32_spidev_s g_spi6dev =
{
.spidev =
{
&g_sp6iops
},
{
.ops = &g_sp6iops
},
.spibase = STM32_SPI6_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
#ifdef CONFIG_STM32_SPI_INTERRUPTS
@ -701,7 +701,7 @@ static struct stm32_spidev_s g_spi6dev =
# ifdef CONFIG_STM32_SPI6_DMA
.rxch = DMACHAN_SPI6_RX,
.txch = DMACHAN_SPI6_TX,
#if defined(SPI6_DMABUFSIZE_ADJUSTED)
# ifdef SPI6_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi6_rxbuf,
.txbuf = g_spi6_txbuf,
.buflen = SPI6_DMABUFSIZE_ADJUSTED,

15
arch/arm/src/stm32f0l0g0/stm32_i2c.c
View File

@ -474,7 +474,7 @@ static inline void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv);
static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv);
static inline
uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv);
static int stm32_i2c_isr_process(struct stm32_i2c_priv_s * priv);
static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv);
#ifndef CONFIG_I2C_POLLED
static int stm32_i2c_isr(int irq, void *context, void *arg);
#endif
@ -486,7 +486,7 @@ static int stm32_i2c_process(struct i2c_master_s *dev,
static int stm32_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int stm32_i2c_reset(struct i2c_master_s * dev);
static int stm32_i2c_reset(struct i2c_master_s *dev);
#endif
#ifdef CONFIG_PM
static int stm32_i2c_pm_prepare(struct pm_callback_s *cb,
@ -2464,11 +2464,18 @@ static int stm32_i2c_process(struct i2c_master_s *dev,
static int stm32_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count)
{
struct stm32_i2c_priv_s *priv;
int ret;
DEBUGASSERT(dev);
/* Get I2C private structure */
priv = ((struct stm32_i2c_inst_s *)dev)->priv;
/* Ensure that address or flags don't change meanwhile */
ret = nxmutex_lock(&((struct stm32_i2c_inst_s *)dev)->priv->lock);
ret = nxmutex_lock(&priv->lock);
if (ret >= 0)
{
ret = stm32_i2c_process(dev, msgs, count);
@ -2486,7 +2493,7 @@ static int stm32_i2c_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int stm32_i2c_reset(struct i2c_master_s * dev)
static int stm32_i2c_reset(struct i2c_master_s *dev)
{
struct stm32_i2c_priv_s *priv;
unsigned int clock_count;

18
arch/arm/src/stm32f0l0g0/stm32_spi.c
View File

@ -312,9 +312,9 @@ static const struct spi_ops_s g_spi1ops =
static struct stm32_spidev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
},
{
.ops = &g_spi1ops,
},
.spibase = STM32_SPI1_BASE,
.spiclock = SPI1_PCLK_FREQUENCY,
#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
@ -371,9 +371,9 @@ static const struct spi_ops_s g_spi2ops =
static struct stm32_spidev_s g_spi2dev =
{
.spidev =
{
&g_spi2ops
},
{
.ops = &g_spi2ops,
},
.spibase = STM32_SPI2_BASE,
.spiclock = SPI1_PCLK_FREQUENCY,
#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
@ -428,9 +428,9 @@ static const struct spi_ops_s g_spi3ops =
static struct stm32_spidev_s g_spi3dev =
{
.spidev =
{
&g_spi3ops
},
{
.ops = &g_spi3ops,
},
.spibase = STM32_SPI3_BASE,
.spiclock = SPI1_PCLK_FREQUENCY,
#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS

6
arch/arm/src/stm32f7/stm32_adc.c
View File

@ -307,7 +307,7 @@ static void adc_enable(struct stm32_dev_s *priv, bool enable);
static uint32_t adc_sqrbits(struct stm32_dev_s *priv, int first,
int last, int offset);
static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch);
static bool adc_internal(struct stm32_dev_s * priv);
static bool adc_internal(struct stm32_dev_s *priv);
static int adc_resolution_set(struct adc_dev_s *dev, uint8_t res);
@ -930,7 +930,7 @@ static int adc_timinit(struct stm32_dev_s *priv)
* 0 <= prescaler <= 65536
* 1 <= reload <= 65535
*
* So ( prescaler = pclck / 65535 / freq ) would be optimal.
* So (prescaler = pclck / 65535 / freq) would be optimal.
*/
prescaler = (priv->pclck / priv->freq + 65534) / 65535;
@ -2158,7 +2158,7 @@ static uint32_t adc_sqrbits(struct stm32_dev_s *priv, int first,
* Name: adc_internal
****************************************************************************/
static bool adc_internal(struct stm32_dev_s * priv)
static bool adc_internal(struct stm32_dev_s *priv)
{
int i;

22
arch/arm/src/stm32f7/stm32_dma2d.c
View File

@ -461,8 +461,8 @@ static int stm32_dma2d_waitforirq(void)
#ifdef CONFIG_STM32F7_DMA2D_L8
static int stm32_dma2d_loadclut(uintptr_t pfcreg)
{
int ret;
uint32_t regval;
int ret;
uint32_t regval;
/* Start clut loading */
@ -495,7 +495,7 @@ static int stm32_dma2d_loadclut(uintptr_t pfcreg)
static int stm32_dma2d_start(void)
{
int ret;
int ret;
/* Start dma transfer */
@ -681,7 +681,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha,
#ifdef CONFIG_STM32F7_FB_CMAP
if (fmt == DMA2D_PF_L8)
{
struct stm32_dma2d_s * layer = &g_dma2ddev;
struct stm32_dma2d_s *layer = &g_dma2ddev;
/* Load CLUT automatically */
@ -745,7 +745,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha,
static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap)
{
int n;
struct stm32_dma2d_s * priv = &g_dma2ddev;
struct stm32_dma2d_s *priv = &g_dma2ddev;
lcdinfo("cmap=%p\n", cmap);
@ -814,7 +814,7 @@ static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo,
uint32_t argb)
{
int ret;
struct stm32_dma2d_s * priv = &g_dma2ddev;
struct stm32_dma2d_s *priv = &g_dma2ddev;
DEBUGASSERT(oinfo != NULL && oinfo->oinfo != NULL && area != NULL);
lcdinfo("oinfo=%p, argb=%08x\n", oinfo, argb);
@ -895,9 +895,9 @@ static int stm32_dma2d_blit(struct stm32_dma2d_overlay_s *doverlay,
struct stm32_dma2d_overlay_s *soverlay,
const struct fb_area_s *sarea)
{
int ret;
uint32_t mode;
struct stm32_dma2d_s * priv = &g_dma2ddev;
int ret;
uint32_t mode;
struct stm32_dma2d_s *priv = &g_dma2ddev;
lcdinfo("doverlay=%p, destxpos=%d, destypos=%d, soverlay=%p, sarea=%p\n",
doverlay, destxpos, destypos, soverlay, sarea);
@ -994,8 +994,8 @@ static int stm32_dma2d_blend(struct stm32_dma2d_overlay_s *doverlay,
struct stm32_dma2d_overlay_s *boverlay,
const struct fb_area_s *barea)
{
int ret;
struct stm32_dma2d_s * priv = &g_dma2ddev;
int ret;
struct stm32_dma2d_s *priv = &g_dma2ddev;
lcdinfo("doverlay=%p, destxpos=%d, destypos=%d, "
"foverlay=%p, forexpos=%d, foreypos=%d, "

10
arch/arm/src/stm32f7/stm32_foc.c
View File

@ -936,7 +936,7 @@ static int stm32_foc_adc_start(struct foc_dev_s *dev, bool state)
static int stm32_foc_adc_cfg(struct foc_dev_s *dev)
{
struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev);
struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev);
DEBUGASSERT(dev);
DEBUGASSERT(foc_dev);
@ -1248,10 +1248,10 @@ errout:
static int stm32_foc_shutdown(struct foc_dev_s *dev)
{
struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev);
struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev);
struct stm32_foc_priv_s *priv = STM32_FOCPRIV_FROM_DEV_GET(dev);
int ret = OK;
struct stm32_foc_dev_s *foc_dev = STM32_FOCDEV_FROM_DEV_GET(dev);
struct stm32_foc_board_s *board = STM32_FOCBOARD_FROM_DEV_GET(dev);
struct stm32_foc_priv_s *priv = STM32_FOCPRIV_FROM_DEV_GET(dev);
int ret = OK;
DEBUGASSERT(dev);
DEBUGASSERT(foc_dev);

13
arch/arm/src/stm32f7/stm32_i2c.c
View File

@ -522,7 +522,7 @@ static int stm32_i2c_process(struct i2c_master_s *dev,
static int stm32_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int stm32_i2c_reset(struct i2c_master_s * dev);
static int stm32_i2c_reset(struct i2c_master_s *dev);
#endif
#ifdef CONFIG_PM
static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain,
@ -2505,11 +2505,18 @@ static int stm32_i2c_process(struct i2c_master_s *dev,
static int stm32_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count)
{
struct stm32_i2c_priv_s *priv;
int ret;
DEBUGASSERT(dev);
/* Get I2C private structure */
priv = ((struct stm32_i2c_inst_s *)dev)->priv;
/* Ensure that address or flags don't change meanwhile */
ret = nxmutex_lock(&((struct stm32_i2c_inst_s *)dev)->priv->lock);
ret = nxmutex_lock(&priv->lock);
if (ret >= 0)
{
ret = stm32_i2c_process(dev, msgs, count);
@ -2527,7 +2534,7 @@ static int stm32_i2c_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int stm32_i2c_reset(struct i2c_master_s * dev)
static int stm32_i2c_reset(struct i2c_master_s *dev)
{
struct stm32_i2c_priv_s *priv;
unsigned int clock_count;

32
arch/arm/src/stm32f7/stm32_ltdc.c
View File

@ -683,7 +683,7 @@ static int stm32_ltdc_reload(uint8_t value, bool waitvblank);
static void stm32_ltdc_lpixelformat(struct stm32_ltdc_s *layer);
static void stm32_ltdc_lframebuffer(struct stm32_ltdc_s *layer);
static void stm32_ltdc_lenable(struct stm32_ltdc_s *layer, bool enable);
static void stm32_ltdc_ldefaultcolor(struct stm32_ltdc_s * layer,
static void stm32_ltdc_ldefaultcolor(struct stm32_ltdc_s *layer,
uint32_t rgb);
static void stm32_ltdc_ltransp(struct stm32_ltdc_s *layer,
uint8_t transp,
@ -704,9 +704,9 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer,
#endif
#ifdef CONFIG_STM32F7_FB_CMAP
static void stm32_ltdc_lputclut(struct stm32_ltdc_s * layer,
static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer,
const struct fb_cmap_s *cmap);
static void stm32_ltdc_lgetclut(struct stm32_ltdc_s * layer,
static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer,
struct fb_cmap_s *cmap);
static void stm32_ltdc_lclutenable(struct stm32_ltdc_s *layer,
bool enable);
@ -1342,7 +1342,7 @@ static void stm32_ltdc_periphconfig(void)
*
****************************************************************************/
static void stm32_ltdc_ldefaultcolor(struct stm32_ltdc_s * layer,
static void stm32_ltdc_ldefaultcolor(struct stm32_ltdc_s *layer,
uint32_t rgb)
{
DEBUGASSERT(layer->layerno < LTDC_NLAYERS);
@ -2081,8 +2081,8 @@ static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer,
*
****************************************************************************/
static void stm32_ltdc_lgetclut(struct stm32_ltdc_s * layer,
struct fb_cmap_s * cmap)
static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer,
struct fb_cmap_s *cmap)
{
int n;
struct fb_cmap_s *priv_cmap = &g_vtable.cmap;
@ -2403,7 +2403,7 @@ static int stm32_getcmap(struct fb_vtable_s *vtable,
* from the main overlay.
*/
struct stm32_ltdc_s * layer;
struct stm32_ltdc_s *layer;
# ifdef CONFIG_STM32F7_LTDC_L2
layer = &priv->layer[LTDC_LAYER_L2];
# else
@ -2490,7 +2490,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable,
for (n = 0; n < LTDC_NLAYERS; n++)
{
struct stm32_ltdc_s * layer = &priv->layer[n];
struct stm32_ltdc_s *layer = &priv->layer[n];
stm32_ltdc_lputclut(layer, priv_cmap);
}
@ -2547,7 +2547,7 @@ static int stm32_getoverlayinfo(struct fb_vtable_s *vtable,
if (overlayno < LTDC_NOVERLAYS)
{
struct stm32_ltdc_s * layer = &priv->layer[overlayno];
struct stm32_ltdc_s *layer = &priv->layer[overlayno];
memcpy(oinfo, &layer->oinfo, sizeof(struct fb_overlayinfo_s));
return OK;
}
@ -2579,7 +2579,7 @@ static int stm32_settransp(struct fb_vtable_s *vtable,
if (oinfo->overlay < LTDC_NOVERLAYS)
{
struct stm32_ltdc_s * layer = &priv->layer[oinfo->overlay];
struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay];
nxmutex_lock(layer->lock);
layer->oinfo.transp.transp = oinfo->transp.transp;
@ -2630,7 +2630,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable,
if (oinfo->overlay < LTDC_NLAYERS)
{
int ret;
struct stm32_ltdc_s * layer = &priv->layer[oinfo->overlay];
struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay];
# ifndef CONFIG_STM32F7_LTDC_L1_CHROMAKEY
if (oinfo->overlay == LTDC_LAYER_L1)
@ -2703,8 +2703,8 @@ static int stm32_setcolor(struct fb_vtable_s *vtable,
int ret;
struct stm32_ltdcdev_s *priv =
(struct stm32_ltdcdev_s *)vtable;
struct stm32_ltdc_s * layer = &priv->layer[oinfo->overlay];
struct fb_overlayinfo_s * poverlay = layer->dma2dinfo.oinfo;
struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay];
struct fb_overlayinfo_s *poverlay = layer->dma2dinfo.oinfo;
DEBUGASSERT(&layer->oinfo == poverlay);
@ -2742,7 +2742,7 @@ static int stm32_setblank(struct fb_vtable_s *vtable,
if (oinfo->overlay < LTDC_NLAYERS)
{
struct stm32_ltdc_s * layer = &priv->layer[oinfo->overlay];
struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay];
nxmutex_lock(layer->lock);
layer->oinfo.blank = oinfo->blank;
@ -2793,7 +2793,7 @@ static int stm32_setarea(struct fb_vtable_s *vtable,
{
struct stm32_ltdcdev_s *priv =
(struct stm32_ltdcdev_s *)vtable;
struct stm32_ltdc_s * layer =
struct stm32_ltdc_s *layer =
&priv->layer[oinfo->overlay];
nxmutex_lock(layer->lock);
@ -2970,7 +2970,7 @@ void stm32_ltdcreset(void)
int stm32_ltdcinitialize(void)
{
int ret = OK;
int ret = OK;
lcdinfo("Initialize LTDC driver\n");

6
arch/arm/src/stm32f7/stm32_otghost.c
View File

@ -483,8 +483,8 @@ static struct stm32_usbhost_s g_usbhost =
static struct usbhost_connection_s g_usbconn =
{
.wait = stm32_wait,
.enumerate = stm32_enumerate,
.wait = stm32_wait,
.enumerate = stm32_enumerate,
};
/****************************************************************************
@ -5243,7 +5243,7 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv)
struct stm32_chan_s *chan = &priv->chan[i];
chan->chidx = i;
nxsem_init(&chan->waitsem, 0, 0);
nxsem_init(&chan->waitsem, 0, 0);
}
}

2
arch/arm/src/stm32f7/stm32_qspi.c
View File

@ -335,7 +335,7 @@ static const struct qspi_ops_s g_qspi0ops =
static struct stm32f7_qspidev_s g_qspi0dev =
{
.qspi =
.qspi =
{
.ops = &g_qspi0ops,
},

2
arch/arm/src/stm32f7/stm32_sdmmc.c
View File

@ -1598,7 +1598,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg)
#ifdef HAVE_SDMMC_SDIO_MODE
uint32_t mask;
#endif
struct stm32_dev_s *priv = (struct stm32_dev_s *) arg;
struct stm32_dev_s *priv = (struct stm32_dev_s *)arg;
DEBUGASSERT(priv != NULL);

26
arch/arm/src/stm32f7/stm32_spi.c
View File

@ -330,7 +330,7 @@ static struct stm32_spidev_s g_spi1dev =
{
.spidev =
{
&g_sp1iops
.ops = &g_sp1iops,
},
.spibase = STM32_SPI1_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
@ -341,7 +341,7 @@ static struct stm32_spidev_s g_spi1dev =
# ifdef CONFIG_STM32F7_SPI1_DMA
.rxch = DMAMAP_SPI1_RX,
.txch = DMAMAP_SPI1_TX,
#if defined(SPI1_DMABUFSIZE_ADJUSTED)
# ifdef SPI1_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi1_rxbuf,
.txbuf = g_spi1_txbuf,
.buflen = SPI1_DMABUFSIZE_ADJUSTED,
@ -401,7 +401,7 @@ static struct stm32_spidev_s g_spi2dev =
{
.spidev =
{
&g_sp2iops
.ops = &g_sp2iops,
},
.spibase = STM32_SPI2_BASE,
.spiclock = STM32_PCLK1_FREQUENCY,
@ -412,7 +412,7 @@ static struct stm32_spidev_s g_spi2dev =
# ifdef CONFIG_STM32F7_SPI2_DMA
.rxch = DMAMAP_SPI2_RX,
.txch = DMAMAP_SPI2_TX,
#if defined(SPI2_DMABUFSIZE_ADJUSTED)
# ifdef SPI3_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi2_rxbuf,
.txbuf = g_spi2_txbuf,
.buflen = SPI2_DMABUFSIZE_ADJUSTED,
@ -472,7 +472,7 @@ static struct stm32_spidev_s g_spi3dev =
{
.spidev =
{
&g_sp3iops
.ops = &g_sp3iops,
},
.spibase = STM32_SPI3_BASE,
.spiclock = STM32_PCLK1_FREQUENCY,
@ -483,7 +483,7 @@ static struct stm32_spidev_s g_spi3dev =
# ifdef CONFIG_STM32F7_SPI3_DMA
.rxch = DMAMAP_SPI3_RX,
.txch = DMAMAP_SPI3_TX,
#if defined(SPI3_DMABUFSIZE_ADJUSTED)
# ifdef SPI3_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi3_rxbuf,
.txbuf = g_spi3_txbuf,
.buflen = SPI3_DMABUFSIZE_ADJUSTED,
@ -543,7 +543,7 @@ static struct stm32_spidev_s g_spi4dev =
{
.spidev =
{
&g_sp4iops
.ops = &g_sp4iops,
},
.spibase = STM32_SPI4_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
@ -554,7 +554,7 @@ static struct stm32_spidev_s g_spi4dev =
# ifdef CONFIG_STM32F7_SPI4_DMA
.rxch = DMAMAP_SPI4_RX,
.txch = DMAMAP_SPI4_TX,
#if defined(SPI4_DMABUFSIZE_ADJUSTED)
# ifdef SPI4_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi4_rxbuf,
.txbuf = g_spi4_txbuf,
.buflen = SPI4_DMABUFSIZE_ADJUSTED,
@ -614,7 +614,7 @@ static struct stm32_spidev_s g_spi5dev =
{
.spidev =
{
&g_sp5iops
.ops = &g_sp5iops,
},
.spibase = STM32_SPI5_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
@ -625,7 +625,7 @@ static struct stm32_spidev_s g_spi5dev =
# ifdef CONFIG_STM32F7_SPI5_DMA
.rxch = DMAMAP_SPI5_RX,
.txch = DMAMAP_SPI5_TX,
#if defined(SPI5_DMABUFSIZE_ADJUSTED)
# ifdef SPI5_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi5_rxbuf,
.txbuf = g_spi5_txbuf,
.buflen = SPI5_DMABUFSIZE_ADJUSTED,
@ -685,7 +685,7 @@ static struct stm32_spidev_s g_spi6dev =
{
.spidev =
{
&g_sp6iops
.ops = &g_sp6iops,
},
.spibase = STM32_SPI6_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
@ -696,7 +696,7 @@ static struct stm32_spidev_s g_spi6dev =
# ifdef CONFIG_STM32F7_SPI6_DMA
.rxch = DMAMAP_SPI6_RX,
.txch = DMAMAP_SPI6_TX,
#if defined(SPI6_DMABUFSIZE_ADJUSTED)
# ifdef SPI6_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi6_rxbuf,
.txbuf = g_spi6_txbuf,
.buflen = SPI6_DMABUFSIZE_ADJUSTED,
@ -1805,7 +1805,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
void *rxbuffer, size_t nwords)
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
void * xbuffer = rxbuffer;
void *xbuffer = rxbuffer;
int ret;
DEBUGASSERT(priv != NULL);

13
arch/arm/src/stm32h7/stm32_i2c.c
View File

@ -481,7 +481,7 @@ static int stm32_i2c_process(struct i2c_master_s *dev,
static int stm32_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int stm32_i2c_reset(struct i2c_master_s * dev);
static int stm32_i2c_reset(struct i2c_master_s *dev);
#endif
#ifdef CONFIG_PM
static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain,
@ -2469,11 +2469,18 @@ static int stm32_i2c_process(struct i2c_master_s *dev,
static int stm32_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count)
{
struct stm32_i2c_priv_s *priv;
int ret;
DEBUGASSERT(dev);
/* Get I2C private structure */
priv = ((struct stm32_i2c_inst_s *)dev)->priv;
/* Ensure that address or flags don't change meanwhile */
ret = nxmutex_lock(&((struct stm32_i2c_inst_s *)dev)->priv->lock);
ret = nxmutex_lock(&priv->lock);
if (ret >= 0)
{
ret = stm32_i2c_process(dev, msgs, count);
@ -2491,7 +2498,7 @@ static int stm32_i2c_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int stm32_i2c_reset(struct i2c_master_s * dev)
static int stm32_i2c_reset(struct i2c_master_s *dev)
{
struct stm32_i2c_priv_s *priv;
unsigned int clock_count;

6
arch/arm/src/stm32h7/stm32_otghost.c
View File

@ -485,8 +485,8 @@ static struct stm32_usbhost_s g_usbhost =
static struct usbhost_connection_s g_usbconn =
{
.wait = stm32_wait,
.enumerate = stm32_enumerate,
.wait = stm32_wait,
.enumerate = stm32_enumerate,
};
/****************************************************************************
@ -5247,7 +5247,7 @@ static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv)
struct stm32_chan_s *chan = &priv->chan[i];
chan->chidx = i;
nxsem_init(&chan->waitsem, 0, 0);
nxsem_init(&chan->waitsem, 0, 0);
}
}

2
arch/arm/src/stm32h7/stm32_qspi.c
View File

@ -360,7 +360,7 @@ static const struct qspi_ops_s g_qspi0ops =
static struct stm32h7_qspidev_s g_qspi0dev =
{
.qspi =
.qspi =
{
.ops = &g_qspi0ops,
},

2
arch/arm/src/stm32h7/stm32_rtc_lowerhalf.c
View File

@ -155,7 +155,7 @@ static const struct rtc_ops_s g_rtc_ops =
static struct stm32_lowerhalf_s g_rtc_lowerhalf =
{
.ops = &g_rtc_ops,
.ops = &g_rtc_ops,
.devlock = NXMUTEX_INITIALIZER,
};

16
arch/arm/src/stm32h7/stm32_sdmmc.c
View File

@ -588,14 +588,14 @@ struct stm32_dev_s g_sdmmcdev1 =
.dmasendsetup = stm32_dmasendsetup,
#endif
},
.base = STM32_SDMMC1_BASE,
.nirq = STM32_IRQ_SDMMC1,
.base = STM32_SDMMC1_BASE,
.nirq = STM32_IRQ_SDMMC1,
#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE)
.d0_gpio = SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0),
.d0_gpio = SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0),
#endif
.waitsem = SEM_INITIALIZER(0),
#if defined(HAVE_SDMMC_SDIO_MODE) && defined(CONFIG_SDMMC1_SDIO_MODE)
.sdiomode = true,
.sdiomode = true,
#endif
};
#endif
@ -643,14 +643,14 @@ struct stm32_dev_s g_sdmmcdev2 =
.dmasendsetup = stm32_dmasendsetup,
#endif
},
.base = STM32_SDMMC2_BASE,
.nirq = STM32_IRQ_SDMMC2,
.base = STM32_SDMMC2_BASE,
.nirq = STM32_IRQ_SDMMC2,
#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE)
.d0_gpio = SDMMC2_SDIO_PULL(GPIO_SDMMC2_D0),
.d0_gpio = SDMMC2_SDIO_PULL(GPIO_SDMMC2_D0),
#endif
.waitsem = SEM_INITIALIZER(0),
#if defined(HAVE_SDMMC_SDIO_MODE) && defined(CONFIG_SDMMC2_SDIO_MODE)
.sdiomode = true,
.sdiomode = true,
#endif
};
#endif

362
arch/arm/src/stm32h7/stm32_serial.c
View File

@ -919,31 +919,31 @@ static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \
static struct up_dev_s g_usart1priv =
{
.dev =
{
{
#if CONSOLE_UART == 1
.isconsole = true,
.isconsole = true,
#endif
.recv =
{
.size = sizeof(g_usart1rxbuffer),
.buffer = g_usart1rxbuffer,
},
.xmit =
{
.size = sizeof(g_usart1txbuffer),
.buffer = g_usart1txbuffer,
},
#if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_USART1_RXDMA) && !defined(CONFIG_USART1_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_usart1priv,
.recv =
{
.size = sizeof(g_usart1rxbuffer),
.buffer = g_usart1rxbuffer,
},
.xmit =
{
.size = sizeof(g_usart1txbuffer),
.buffer = g_usart1txbuffer,
},
#if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_USART1_RXDMA) && !defined(CONFIG_USART1_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_usart1priv,
},
.irq = STM32_IRQ_USART1,
.rxftcfg = CONFIG_USART1_RXFIFO_THRES,
@ -989,31 +989,31 @@ static struct up_dev_s g_usart1priv =
static struct up_dev_s g_usart2priv =
{
.dev =
{
{
#if CONSOLE_UART == 2
.isconsole = true,
.isconsole = true,
#endif
.recv =
{
.size = sizeof(g_usart2rxbuffer),
.buffer = g_usart2rxbuffer,
},
.xmit =
{
.size = sizeof(g_usart2txbuffer),
.buffer = g_usart2txbuffer,
},
#if defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_USART2_RXDMA) && !defined(CONFIG_USART2_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_usart2priv,
.recv =
{
.size = sizeof(g_usart2rxbuffer),
.buffer = g_usart2rxbuffer,
},
.xmit =
{
.size = sizeof(g_usart2txbuffer),
.buffer = g_usart2txbuffer,
},
#if defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_USART2_RXDMA) && !defined(CONFIG_USART2_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_usart2priv,
},
.irq = STM32_IRQ_USART2,
.rxftcfg = CONFIG_USART2_RXFIFO_THRES,
@ -1059,31 +1059,31 @@ static struct up_dev_s g_usart2priv =
static struct up_dev_s g_usart3priv =
{
.dev =
{
{
#if CONSOLE_UART == 3
.isconsole = true,
.isconsole = true,
#endif
.recv =
{
.size = sizeof(g_usart3rxbuffer),
.buffer = g_usart3rxbuffer,
},
.xmit =
{
.size = sizeof(g_usart3txbuffer),
.buffer = g_usart3txbuffer,
},
#if defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_USART3_RXDMA) && !defined(CONFIG_USART3_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_usart3priv,
.recv =
{
.size = sizeof(g_usart3rxbuffer),
.buffer = g_usart3rxbuffer,
},
.xmit =
{
.size = sizeof(g_usart3txbuffer),
.buffer = g_usart3txbuffer,
},
#if defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_USART3_RXDMA) && !defined(CONFIG_USART3_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_usart3priv,
},
.irq = STM32_IRQ_USART3,
.rxftcfg = CONFIG_USART3_RXFIFO_THRES,
@ -1129,31 +1129,31 @@ static struct up_dev_s g_usart3priv =
static struct up_dev_s g_uart4priv =
{
.dev =
{
{
#if CONSOLE_UART == 4
.isconsole = true,
.isconsole = true,
#endif
.recv =
{
.size = sizeof(g_uart4rxbuffer),
.buffer = g_uart4rxbuffer,
},
.xmit =
{
.size = sizeof(g_uart4txbuffer),
.buffer = g_uart4txbuffer,
},
#if defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_UART4_RXDMA) && !defined(CONFIG_UART4_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_uart4priv,
.recv =
{
.size = sizeof(g_uart4rxbuffer),
.buffer = g_uart4rxbuffer,
},
.xmit =
{
.size = sizeof(g_uart4txbuffer),
.buffer = g_uart4txbuffer,
},
#if defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_UART4_RXDMA) && !defined(CONFIG_UART4_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_uart4priv,
},
.irq = STM32_IRQ_UART4,
.rxftcfg = CONFIG_UART4_RXFIFO_THRES,
@ -1199,31 +1199,31 @@ static struct up_dev_s g_uart4priv =
static struct up_dev_s g_uart5priv =
{
.dev =
{
{
#if CONSOLE_UART == 5
.isconsole = true,
.isconsole = true,
#endif
.recv =
{
.size = sizeof(g_uart5rxbuffer),
.buffer = g_uart5rxbuffer,
},
.xmit =
{
.size = sizeof(g_uart5txbuffer),
.buffer = g_uart5txbuffer,
},
#if defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_UART5_RXDMA) && !defined(CONFIG_UART5_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_uart5priv,
.recv =
{
.size = sizeof(g_uart5rxbuffer),
.buffer = g_uart5rxbuffer,
},
.xmit =
{
.size = sizeof(g_uart5txbuffer),
.buffer = g_uart5txbuffer,
},
#if defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_UART5_RXDMA) && !defined(CONFIG_UART5_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_uart5priv,
},
.irq = STM32_IRQ_UART5,
.rxftcfg = CONFIG_UART5_RXFIFO_THRES,
@ -1269,31 +1269,31 @@ static struct up_dev_s g_uart5priv =
static struct up_dev_s g_usart6priv =
{
.dev =
{
{
#if CONSOLE_UART == 6
.isconsole = true,
.isconsole = true,
#endif
.recv =
{
.size = sizeof(g_usart6rxbuffer),
.buffer = g_usart6rxbuffer,
},
.xmit =
{
.size = sizeof(g_usart6txbuffer),
.buffer = g_usart6txbuffer,
},
#if defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_USART6_RXDMA) && !defined(CONFIG_USART6_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_usart6priv,
.recv =
{
.size = sizeof(g_usart6rxbuffer),
.buffer = g_usart6rxbuffer,
},
.xmit =
{
.size = sizeof(g_usart6txbuffer),
.buffer = g_usart6txbuffer,
},
#if defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_USART6_RXDMA) && !defined(CONFIG_USART6_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_usart6priv,
},
.irq = STM32_IRQ_USART6,
.rxftcfg = CONFIG_USART6_RXFIFO_THRES,
@ -1339,31 +1339,31 @@ static struct up_dev_s g_usart6priv =
static struct up_dev_s g_uart7priv =
{
.dev =
{
{
#if CONSOLE_UART == 7
.isconsole = true,
.isconsole = true,
#endif
.recv =
{
.size = sizeof(g_uart7rxbuffer),
.buffer = g_uart7rxbuffer,
},
.xmit =
{
.size = sizeof(g_uart7txbuffer),
.buffer = g_uart7txbuffer,
},
#if defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_UART7_RXDMA) && !defined(CONFIG_UART7_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_uart7priv,
.recv =
{
.size = sizeof(g_uart7rxbuffer),
.buffer = g_uart7rxbuffer,
},
.xmit =
{
.size = sizeof(g_uart7txbuffer),
.buffer = g_uart7txbuffer,
},
#if defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_UART7_RXDMA) && !defined(CONFIG_UART7_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_uart7priv,
},
.irq = STM32_IRQ_UART7,
.rxftcfg = CONFIG_UART7_RXFIFO_THRES,
@ -1409,31 +1409,31 @@ static struct up_dev_s g_uart7priv =
static struct up_dev_s g_uart8priv =
{
.dev =
{
{
#if CONSOLE_UART == 8
.isconsole = true,
.isconsole = true,
#endif
.recv =
{
.size = sizeof(g_uart8rxbuffer),
.buffer = g_uart8rxbuffer,
},
.xmit =
{
.size = sizeof(g_uart8txbuffer),
.buffer = g_uart8txbuffer,
},
#if defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_UART8_RXDMA) && !defined(CONFIG_UART8_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_uart8priv,
.recv =
{
.size = sizeof(g_uart8rxbuffer),
.buffer = g_uart8rxbuffer,
},
.xmit =
{
.size = sizeof(g_uart8txbuffer),
.buffer = g_uart8txbuffer,
},
#if defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_UART8_RXDMA) && !defined(CONFIG_UART8_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_uart8priv,
},
.irq = STM32_IRQ_UART8,
.rxftcfg = CONFIG_UART8_RXFIFO_THRES,
@ -2274,7 +2274,7 @@ static int up_dma_setup(struct uart_dev_s *dev)
* worth of time to claim bytes before they are overwritten.
*/
stm32_dmastart(priv->rxdma, up_dma_rxcallback, (void *)priv, true);
stm32_dmastart(priv->rxdma, up_dma_rxcallback, priv, true);
}
#endif
@ -3253,7 +3253,7 @@ static void up_dma_reenable(struct up_dev_s *priv)
* worth of time to claim bytes before they are overwritten.
*/
stm32_dmastart(priv->rxdma, up_dma_rxcallback, (void *)priv, true);
stm32_dmastart(priv->rxdma, up_dma_rxcallback, priv, true);
/* Clear DMA suspended flag. */
@ -3352,7 +3352,7 @@ static void up_dma_txcallback(DMA_HANDLE handle, uint8_t status, void *arg)
/* Start transmission with the callback on DMA completion */
stm32_dmastart(priv->txdma, up_dma_txcallback,
(void *)priv, false);
priv, false);
return;
}
@ -3438,7 +3438,7 @@ static void up_dma_send(struct uart_dev_s *dev)
/* Start transmission with the callback on DMA completion */
stm32_dmastart(priv->txdma, up_dma_txcallback, (void *)priv, false);
stm32_dmastart(priv->txdma, up_dma_txcallback, priv, false);
}
#endif
@ -3481,7 +3481,7 @@ static void up_dma_txint(struct uart_dev_s *dev, bool enable)
* Instead, we use DMA interrupts that are activated once during boot
* sequence. Furthermore we can use up_dma_txcallback() to handle staff at
* half DMA transfer or after transfer completion (depending configuration,
* see stm32_dmastart(...) ).
* see stm32_dmastart(...)).
*/
}
#endif

42
arch/arm/src/stm32h7/stm32_spi.c
View File

@ -395,9 +395,9 @@ static uint8_t g_spi1_rxbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN;
static struct stm32_spidev_s g_spi1dev =
{
.spidev =
{
&g_sp1iops
},
{
.ops = &g_sp1iops,
},
.spibase = STM32_SPI1_BASE,
.spiclock = SPI123_KERNEL_CLOCK_FREQ,
.spiirq = STM32_IRQ_SPI1,
@ -467,9 +467,9 @@ static uint8_t g_spi2_rxbuf[SPI2_DMABUFSIZE_ADJUSTED] SPI2_DMABUFSIZE_ALGN;
static struct stm32_spidev_s g_spi2dev =
{
.spidev =
{
&g_sp2iops
},
{
.ops = &g_sp2iops,
},
.spibase = STM32_SPI2_BASE,
.spiclock = SPI123_KERNEL_CLOCK_FREQ,
.spiirq = STM32_IRQ_SPI2,
@ -539,9 +539,9 @@ static uint8_t g_spi3_rxbuf[SPI3_DMABUFSIZE_ADJUSTED] SPI3_DMABUFSIZE_ALGN;
static struct stm32_spidev_s g_spi3dev =
{
.spidev =
{
&g_sp3iops
},
{
.ops = &g_sp3iops,
},
.spibase = STM32_SPI3_BASE,
.spiclock = SPI123_KERNEL_CLOCK_FREQ,
.spiirq = STM32_IRQ_SPI3,
@ -611,9 +611,9 @@ static uint8_t g_spi4_rxbuf[SPI4_DMABUFSIZE_ADJUSTED] SPI4_DMABUFSIZE_ALGN;
static struct stm32_spidev_s g_spi4dev =
{
.spidev =
{
&g_sp4iops
},
{
.ops = &g_sp4iops,
},
.spibase = STM32_SPI4_BASE,
.spiclock = SPI45_KERNEL_CLOCK_FREQ,
.spiirq = STM32_IRQ_SPI4,
@ -683,9 +683,9 @@ static uint8_t g_spi5_rxbuf[SPI5_DMABUFSIZE_ADJUSTED] SPI5_DMABUFSIZE_ALGN;
static struct stm32_spidev_s g_spi5dev =
{
.spidev =
{
&g_sp5iops
},
{
.ops = &g_sp5iops,
},
.spibase = STM32_SPI5_BASE,
.spiclock = SPI45_KERNEL_CLOCK_FREQ,
.spiirq = STM32_IRQ_SPI5,
@ -756,20 +756,20 @@ static uint8_t g_spi6_rxbuf[SPI6_DMABUFSIZE_ADJUSTED] SPI6_DMABUFSIZE_ALGN
static struct stm32_spidev_s g_spi6dev =
{
.spidev =
{
&g_sp6iops
},
{
.ops = &g_sp6iops,
},
.spibase = STM32_SPI6_BASE,
.spiclock = SPI6_KERNEL_CLOCK_FREQ,
.spiirq = STM32_IRQ_SPI6,
#ifdef CONFIG_STM32H7_SPI6_DMA
.rxch = DMAMAP_SPI6_RX,
.txch = DMAMAP_SPI6_TX,
#if defined(SPI6_DMABUFSIZE_ADJUSTED)
# if defined(SPI6_DMABUFSIZE_ADJUSTED)
.rxbuf = g_spi6_rxbuf,
.txbuf = g_spi6_txbuf,
.buflen = SPI6_DMABUFSIZE_ADJUSTED,
# endif
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
@ -2053,7 +2053,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
static uint8_t rxdummy[ARMV7M_DCACHE_LINESIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
static const uint16_t txdummy = 0xffff;
void * orig_rxbuffer = rxbuffer;
void *orig_rxbuffer = rxbuffer;
DEBUGASSERT(priv != NULL);

4
arch/arm/src/stm32l4/stm32l4_1wire.c
View File

@ -125,8 +125,8 @@ struct stm32_1wire_priv_s
struct stm32_1wire_inst_s
{
const struct onewire_ops_s *ops; /* Standard 1-Wire operations */
struct stm32_1wire_priv_s *priv; /* Common driver private data structure */
const struct onewire_ops_s *ops; /* Standard 1-Wire operations */
struct stm32_1wire_priv_s *priv; /* Common driver private data structure */
};
/****************************************************************************

2
arch/arm/src/stm32l4/stm32l4_i2c.c
View File

@ -2704,7 +2704,7 @@ static int stm32l4_i2c_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int stm32l4_i2c_reset(struct i2c_master_s * dev)
static int stm32l4_i2c_reset(struct i2c_master_s *dev)
{
struct stm32l4_i2c_priv_s *priv;
unsigned int clock_count;

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