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Fix the coding style and typo issue

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Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
anjiahao 2022-09-06 14:18:45 +08:00 committed by Masayuki Ishikawa
parent d07792a343
commit a4563b8744
148 changed files with 1747 additions and 1744 deletions
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7
arch/arm/src/cxd56xx/cxd56_dmac.c
View File

@ -292,6 +292,10 @@ struct dma_channel_s
static struct dma_channel_s g_dmach[NCHANNELS];
static mutex_t g_dmalock = NXMUTEX_INITIALIZER;
/****************************************************************************
* Private Functions
****************************************************************************/
static int dma_init(int ch);
static int dma_uninit(int ch);
static int dma_open(int ch);
@ -328,6 +332,7 @@ static struct dmac_register_map *get_device(int ch)
case 2: return (struct dmac_register_map *)DMAC2_REG_BASE;
case 3: return (struct dmac_register_map *)DMAC3_REG_BASE;
}
return NULL;
}
@ -335,7 +340,9 @@ static struct dmac_ch_register_map *get_channel(int ch)
{
struct dmac_register_map *dev = get_device(ch);
if (dev == NULL)
{
return NULL;
}
if (is_dmac(2, dev))
{

4
arch/arm/src/cxd56xx/cxd56_emmc.c
View File

@ -935,13 +935,11 @@ static int cxd56_emmc_geometry(struct inode *inode,
int cxd56_emmcinitialize(void)
{
struct cxd56_emmc_state_s *priv;
struct cxd56_emmc_state_s *priv = &g_emmcdev;
uint8_t *buf;
struct emmc_dma_desc_s *descs;
int ret;
priv = &g_emmcdev;
ret = emmc_hwinitialize();
if (ret != OK)
{

4
arch/arm/src/cxd56xx/cxd56_hostif.c
View File

@ -442,9 +442,7 @@ static int hif_initialize(struct hostif_buff_s *buffer)
cxd56_iccinit(CXD56_PROTO_HOSTIF);
ret = cxd56_iccregisterhandler(CXD56_PROTO_HOSTIF, hif_rxhandler, NULL);
return ret;
return cxd56_iccregisterhandler(CXD56_PROTO_HOSTIF, hif_rxhandler, NULL);
}
/****************************************************************************

8
arch/arm/src/cxd56xx/cxd56_spi.c
View File

@ -179,7 +179,7 @@ static struct cxd56_spidev_s g_spi4dev =
{
.spidev =
{
&g_spi4ops
.ops = &g_spi4ops,
},
.spibase = CXD56_IMG_SPI_BASE,
.spibasefreq = 0,
@ -226,7 +226,7 @@ static struct cxd56_spidev_s g_spi5dev =
{
.spidev =
{
&g_spi5ops
.ops = &g_spi5ops,
},
.spibase = CXD56_IMG_WSPI_BASE,
.spibasefreq = 0,
@ -272,7 +272,7 @@ static struct cxd56_spidev_s g_spi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.spibase = CXD56_SPIM_BASE,
.spibasefreq = 0,
@ -318,7 +318,7 @@ static struct cxd56_spidev_s g_spi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.spibase = CXD56_SCU_SPI_BASE,
.spibasefreq = 0,

10
arch/arm/src/cxd56xx/cxd56_uart0.c
View File

@ -231,15 +231,7 @@ static ssize_t uart0_write(struct file *filep,
int cxd56_uart0initialize(const char *devname)
{
int ret;
ret = register_driver(devname, &g_uart0fops, 0666, NULL);
if (ret != 0)
{
return ERROR;
}
return OK;
return register_driver(devname, &g_uart0fops, 0666, NULL);
}
/****************************************************************************

2
arch/arm/src/gd32f4/gd32f4xx_spi.c
View File

@ -294,7 +294,7 @@ static struct gd32_spidev_s g_spi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops
},
.spibase = GD32_SPI0,
.spiclock = GD32_PCLK2_FREQUENCY,

2
arch/arm/src/imxrt/imxrt_lpi2c.c
View File

@ -1976,7 +1976,7 @@ static int imxrt_lpi2c_dma_transfer(struct imxrt_lpi2c_priv_s *priv)
LPI2C_MIER_NDIE | LPI2C_MIER_ALIE |
LPI2C_MIER_PLTIE | LPI2C_MIER_FEIE);
imxrt_dmach_start(priv->dma, imxrt_dma_callback, (void *)priv);
imxrt_dmach_start(priv->dma, imxrt_dma_callback, priv);
imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MDER_OFFSET, 0,
LPI2C_MDER_TDDE | LPI2C_MDER_RDDE);

18
arch/arm/src/imxrt/imxrt_lpspi.c
View File

@ -242,7 +242,7 @@ static struct imxrt_lpspidev_s g_lpspi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.spibase = IMXRT_LPSPI1_BASE,
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
@ -291,7 +291,7 @@ static struct imxrt_lpspidev_s g_lpspi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.spibase = IMXRT_LPSPI2_BASE,
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
@ -340,7 +340,7 @@ static struct imxrt_lpspidev_s g_lpspi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.spibase = IMXRT_LPSPI3_BASE,
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
@ -389,7 +389,7 @@ static struct imxrt_lpspidev_s g_lpspi4dev =
{
.spidev =
{
&g_spi4ops
.ops = &g_spi4ops,
},
.spibase = IMXRT_LPSPI4_BASE,
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
@ -1310,8 +1310,8 @@ static void imxrt_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;
uint16_t *dest = (uint16_t *) rxbuffer;
const uint16_t *src = txbuffer;
uint16_t *dest = rxbuffer;
uint16_t word;
while (nwords-- > 0)
@ -1343,8 +1343,8 @@ static void imxrt_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *) rxbuffer;
const uint8_t *src = txbuffer;
uint8_t *dest = rxbuffer;
uint8_t word;
while (nwords-- > 0)
@ -1362,7 +1362,7 @@ static void imxrt_lpspi_exchange_nodma(struct spi_dev_s *dev,
/* Exchange one word */
word = (uint8_t) imxrt_lpspi_send(dev, (uint32_t) word);
word = (uint8_t)imxrt_lpspi_send(dev, word);
/* Is there a buffer to receive the return value? */

6
arch/arm/src/imxrt/imxrt_serial.c
View File

@ -1538,7 +1538,7 @@ static int imxrt_dma_setup(struct uart_dev_s *dev)
* worth of time to claim bytes before they are overwritten.
*/
imxrt_dmach_start(priv->rxdma, imxrt_dma_rxcallback, (void *)priv);
imxrt_dmach_start(priv->rxdma, imxrt_dma_rxcallback, priv);
}
#endif
@ -2398,7 +2398,7 @@ static void imxrt_dma_reenable(struct imxrt_uart_s *priv)
* worth of time to claim bytes before they are overwritten.
*/
imxrt_dmach_start(priv->rxdma, imxrt_dma_rxcallback, (void *)priv);
imxrt_dmach_start(priv->rxdma, imxrt_dma_rxcallback, priv);
/* Clear DMA suspended flag. */
@ -2569,7 +2569,7 @@ static void imxrt_dma_send(struct uart_dev_s *dev)
/* Start transmission with the callback on DMA completion */
imxrt_dmach_start(priv->txdma, imxrt_dma_txcallback, (void *)priv);
imxrt_dmach_start(priv->txdma, imxrt_dma_txcallback, priv);
}
#endif

6
arch/arm/src/imxrt/imxrt_usdhc.c
View File

@ -2244,7 +2244,8 @@ static int imxrt_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer,
* handler and DMA memory invalidation.
*/
priv->buffer = (uint32_t *) buffer; priv->remaining = nbytes;
priv->buffer = (uint32_t *)buffer;
priv->remaining = nbytes;
/* Then set up the SDIO data path */
@ -2292,7 +2293,8 @@ static int imxrt_sendsetup(struct sdio_dev_s *dev,
/* Save the source buffer information for use by the interrupt handler */
priv->buffer = (uint32_t *) buffer; priv->remaining = nbytes;
priv->buffer = (uint32_t *)buffer;
priv->remaining = nbytes;
/* Then set up the SDIO data path */

4
arch/arm/src/kinetis/kinetis_usbhshost.c
View File

@ -4042,10 +4042,6 @@ static int kinetis_epalloc(struct usbhost_driver_s *drvr,
epinfo->xfrtype = epdesc->xfrtype;
epinfo->speed = hport->speed;
/* The iocsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(&epinfo->iocsem, 0, 0);
/* Success.. return an opaque reference to the endpoint information

4
arch/arm/src/kl/kl_spi.c
View File

@ -123,7 +123,7 @@ static struct kl_spidev_s g_spi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops
},
.spibase = KL_SPI0_BASE,
.lock = NXMUTEX_INITIALIZER,
@ -156,7 +156,7 @@ static struct kl_spidev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops
},
.spibase = KL_SPI1_BASE,
.lock = NXMUTEX_INITIALIZER,

2
arch/arm/src/lc823450/lc823450_dma.c
View File

@ -306,7 +306,7 @@ static void dma_done(DMA_HANDLE handle, void *arg, int result)
test_done = 1;
}
void lc823450_dma_test()
void lc823450_dma_test(void)
{
int i;
for (i = 0; i < 256; i++)

1
arch/arm/src/lc823450/lc823450_mtd.c
View File

@ -815,7 +815,6 @@ int lc823450_mtd_uninitialize(uint32_t devno)
DEBUGASSERT(ret == OK);
nxmutex_destroy(&priv->lock);
kmm_free(g_mtdmaster[ch]);
g_mtdmaster[ch] = NULL;

2
arch/arm/src/lc823450/lc823450_sdc.c
View File

@ -82,7 +82,7 @@
static mutex_t _sdc_lock[2] =
{
NXMUTEX_INITIALIZER,
NXMUTEX_INITIALIZER
NXMUTEX_INITIALIZER,
};
static struct sddrcfg_s _sdch0;

3
arch/arm/src/lc823450/lc823450_serial.c
View File

@ -168,7 +168,6 @@ struct up_dev_s
DMA_HANDLE hrxdma;
DMA_HANDLE htxdma;
sem_t rxdma_wait;
sem_t rxpkt_wait;
sem_t txdma_wait;
#endif /* CONFIG_HSUART */
spinlock_t lock;
@ -1112,7 +1111,7 @@ static void uart_rxdma_callback(DMA_HANDLE hdma, void *arg, int result)
* Name: up_hs_dmasetup
****************************************************************************/
static void up_hs_dmasetup()
static void up_hs_dmasetup(void)
{
irqstate_t flags;

2
arch/arm/src/lc823450/lc823450_spi.c
View File

@ -128,7 +128,7 @@ static struct lc823450_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
.ops = &g_spiops
},
#ifndef CONFIG_SPI_OWNBUS
.lock = NXMUTEX_INITIALIZER,

7
arch/arm/src/lc823450/lc823450_usbdev.c
View File

@ -560,7 +560,7 @@ static struct usbdev_req_s *lc823450_epallocreq(struct usbdev_ep_s *ep)
usbtrace(TRACE_EPALLOCREQ, ((struct lc823450_ep_s *)ep)->epphy);
privreq = (struct lc823450_req_s *)
kmm_malloc(sizeof(struct lc823450_req_s));
kmm_zalloc(sizeof(struct lc823450_req_s));
if (!privreq)
{
@ -568,7 +568,6 @@ static struct usbdev_req_s *lc823450_epallocreq(struct usbdev_ep_s *ep)
return NULL;
}
memset(privreq, 0, sizeof(struct lc823450_req_s));
return &privreq->req;
}
@ -1710,7 +1709,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
* Name: usbdev_msc_read_enter
****************************************************************************/
void usbdev_msc_read_enter()
void usbdev_msc_read_enter(void)
{
struct lc823450_ep_s *privep;
# ifdef CONFIG_DVFS
@ -1727,7 +1726,7 @@ void usbdev_msc_read_enter()
* Name: usbdev_msc_read_exit
****************************************************************************/
void usbdev_msc_read_exit()
void usbdev_msc_read_exit(void)
{
struct lc823450_ep_s *privep;

2
arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c
View File

@ -140,7 +140,7 @@ static struct lpc17_40_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
.ops = &g_spiops,
},
.lock = NXMUTEX_INITIALIZER,
};

6
arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c
View File

@ -178,7 +178,7 @@ static struct lpc17_40_sspdev_s g_ssp0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.sspbase = LPC17_40_SSP0_BASE,
#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS
@ -214,7 +214,7 @@ static struct lpc17_40_sspdev_s g_ssp1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.sspbase = LPC17_40_SSP1_BASE,
#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS
@ -250,7 +250,7 @@ static struct lpc17_40_sspdev_s g_ssp2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.sspbase = LPC17_40_SSP2_BASE,
#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS

2
arch/arm/src/lpc2378/lpc23xx_spi.c
View File

@ -159,7 +159,7 @@ static struct lpc23xx_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
.ops = &g_spiops,
},
.lock = NXMUTEX_INITIALIZER,
};

2
arch/arm/src/lpc31xx/lpc31_spi.c
View File

@ -155,7 +155,7 @@ static struct lpc31_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
.ops = &g_spiops,
},
.lock = NXMUTEX_INITIALIZER,
};

2
arch/arm/src/lpc43xx/lpc43_spi.c
View File

@ -131,7 +131,7 @@ static struct lpc43_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
.ops = &g_spiops,
},
.lock = NXMUTEX_INITIALIZER,
};

4
arch/arm/src/lpc43xx/lpc43_ssp.c
View File

@ -145,7 +145,7 @@ static struct lpc43_sspdev_s g_ssp0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.sspbase = LPC43_SSP0_BASE,
.sspbasefreq = BOARD_SSP0_BASEFREQ,
@ -186,7 +186,7 @@ static struct lpc43_sspdev_s g_ssp1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.sspbase = LPC43_SSP1_BASE,
.sspbasefreq = BOARD_SSP1_BASEFREQ,

2
arch/arm/src/max326xx/max32660/max32660_spim.c
View File

@ -233,7 +233,7 @@ static struct max326_spidev_s g_spi0dev =
{
.dev =
{
&g_sp0iops
.ops = &g_sp0iops,
},
.base = MAX326_SPI0_BASE,
.lock = NXMUTEX_INITIALIZER,

8
arch/arm/src/nrf52/nrf52_spi.c
View File

@ -198,7 +198,7 @@ static struct nrf52_spidev_s g_spi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.base = NRF52_SPIM0_BASE,
@ -251,7 +251,7 @@ static struct nrf52_spidev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.base = NRF52_SPIM1_BASE,
@ -304,7 +304,7 @@ static struct nrf52_spidev_s g_spi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.base = NRF52_SPIM2_BASE,
@ -357,7 +357,7 @@ static struct nrf52_spidev_s g_spi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.base = NRF52_SPIM3_BASE,

5
arch/arm/src/rp2040/rp2040_spi.c
View File

@ -178,7 +178,7 @@ static struct rp2040_spidev_s g_spi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.spibase = RP2040_SPI0_BASE,
.spibasefreq = 0,
@ -227,7 +227,7 @@ static struct rp2040_spidev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.spibase = RP2040_SPI1_BASE,
.spibasefreq = 0,
@ -874,7 +874,6 @@ struct spi_dev_s *rp2040_spibus_initialize(int port)
/* Set a initialized flag */
priv->initialized = 1;
return &priv->spidev;
}

4
arch/arm/src/s32k1xx/s32k1xx_lpi2c.c
View File

@ -1776,8 +1776,8 @@ static int s32k1xx_lpi2c_dma_transfer(struct s32k1xx_lpi2c_priv_s *priv)
LPI2C_MIER_NDIE | LPI2C_MIER_ALIE |
LPI2C_MIER_PLTIE | LPI2C_MIER_FEIE);
s32k1xx_dmach_start(priv->rxdma, s32k1xx_rxdma_callback, (void *)priv);
s32k1xx_dmach_start(priv->txdma, s32k1xx_txdma_callback, (void *)priv);
s32k1xx_dmach_start(priv->rxdma, s32k1xx_rxdma_callback, priv);
s32k1xx_dmach_start(priv->txdma, s32k1xx_txdma_callback, priv);
s32k1xx_lpi2c_modifyreg(priv, S32K1XX_LPI2C_MDER_OFFSET, 0,
LPI2C_MDER_TDDE | LPI2C_MDER_RDDE);

22
arch/arm/src/s32k1xx/s32k1xx_lpspi.c
View File

@ -255,7 +255,7 @@ static struct s32k1xx_lpspidev_s g_lpspi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.spibase = S32K1XX_LPSPI0_BASE,
#ifdef CONFIG_S32K1XX_LPSPI_INTERRUPTS
@ -306,7 +306,7 @@ static struct s32k1xx_lpspidev_s g_lpspi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.spibase = S32K1XX_LPSPI1_BASE,
#ifdef CONFIG_S32K1XX_LPSPI_INTERRUPTS
@ -357,7 +357,7 @@ static struct s32k1xx_lpspidev_s g_lpspi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.spibase = S32K1XX_LPSPI2_BASE,
#ifdef CONFIG_S32K1XX_LPSPI_INTERRUPTS
@ -1369,8 +1369,8 @@ static void s32k1xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
* take care of big endian mode of hardware !!
*/
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *) rxbuffer;
const uint8_t *src = txbuffer;
uint8_t *dest = rxbuffer;
uint32_t word = 0x0;
#ifdef CONFIG_S32K1XX_LPSPI_DWORD
uint32_t word1 = 0x0;
@ -1447,8 +1447,8 @@ static void s32k1xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 32-bit or 64 bit, word size memory transfers */
const uint32_t *src = (const uint32_t *)txbuffer;
uint32_t *dest = (uint32_t *) rxbuffer;
const uint32_t *src = txbuffer;
uint32_t *dest = rxbuffer;
uint32_t word = 0x0;
#ifdef CONFIG_S32K1XX_LPSPI_DWORD
uint32_t word1 = 0x0;
@ -1528,8 +1528,8 @@ static void s32k1xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;
uint16_t *dest = (uint16_t *) rxbuffer;
const uint16_t *src = txbuffer;
uint16_t *dest = rxbuffer;
uint16_t word;
while (nwords-- > 0)
@ -1563,8 +1563,8 @@ static void s32k1xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *) rxbuffer;
const uint8_t *src = txbuffer;
uint8_t *dest = rxbuffer;
uint8_t word;
while (nwords-- > 0)

28
arch/arm/src/s32k3xx/s32k3xx_lpspi.c
View File

@ -246,7 +246,7 @@ static struct s32k3xx_lpspidev_s g_lpspi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.spibase = S32K3XX_LPSPI0_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@ -296,7 +296,7 @@ static struct s32k3xx_lpspidev_s g_lpspi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.spibase = S32K3XX_LPSPI1_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@ -346,7 +346,7 @@ static struct s32k3xx_lpspidev_s g_lpspi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.spibase = S32K3XX_LPSPI2_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@ -396,7 +396,7 @@ static struct s32k3xx_lpspidev_s g_lpspi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.spibase = S32K3XX_LPSPI3_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@ -446,7 +446,7 @@ static struct s32k3xx_lpspidev_s g_lpspi4dev =
{
.spidev =
{
&g_spi4ops
.ops = &g_spi4ops,
},
.spibase = S32K3XX_LPSPI4_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@ -496,7 +496,7 @@ static struct s32k3xx_lpspidev_s g_lpspi5dev =
{
.spidev =
{
&g_spi5ops
.ops = &g_spi5ops,
},
.spibase = S32K3XX_LPSPI5_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@ -1535,8 +1535,8 @@ static void s32k3xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
* take care of big endian mode of hardware !!
*/
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *) rxbuffer;
const uint8_t *src = txbuffer;
uint8_t *dest = rxbuffer;
uint32_t word = 0x0;
#ifdef CONFIG_S32K3XX_LPSPI_DWORD
uint32_t word1 = 0x0;
@ -1613,8 +1613,8 @@ static void s32k3xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 32-bit or 64 bit, word size memory transfers */
const uint32_t *src = (const uint32_t *)txbuffer;
uint32_t *dest = (uint32_t *) rxbuffer;
const uint32_t *src = txbuffer;
uint32_t *dest = rxbuffer;
uint32_t word = 0x0;
#ifdef CONFIG_S32K3XX_LPSPI_DWORD
uint32_t word1 = 0x0;
@ -1694,8 +1694,8 @@ static void s32k3xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;
uint16_t *dest = (uint16_t *) rxbuffer;
const uint16_t *src = txbuffer;
uint16_t *dest = rxbuffer;
uint16_t word;
while (nwords-- > 0)
@ -1729,8 +1729,8 @@ static void s32k3xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *) rxbuffer;
const uint8_t *src = txbuffer;
uint8_t *dest = rxbuffer;
uint8_t word;
while (nwords-- > 0)

3
arch/arm/src/sama5/sam_sdmmc.c
View File

@ -2408,7 +2408,8 @@ static int sam_sendsetup(struct sdio_dev_s *dev,
/* Save the source buffer information for use by the interrupt handler */
priv->buffer = (uint32_t *) buffer; priv->remaining = nbytes;
priv->buffer = (uint32_t *)buffer;
priv->remaining = nbytes;
/* Then set up the SDIO data path */

4
arch/arm/src/samd2l2/sam_spi.c
View File

@ -1174,8 +1174,8 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
/* Start RX and TX DMA channels */
sam_dmastart(priv->dma_tx, spi_dma_callback, (void *)priv);
sam_dmastart(priv->dma_rx, spi_dma_callback, (void *)priv);
sam_dmastart(priv->dma_tx, spi_dma_callback, priv);
sam_dmastart(priv->dma_rx, spi_dma_callback, priv);
/* Enable SPI to trigger the TX DMA channel */

4
arch/arm/src/samd5e5/sam_spi.c
View File

@ -1270,8 +1270,8 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
/* Start RX and TX DMA channels */
sam_dmastart(priv->dma_tx, spi_dma_callback, (void *)priv);
sam_dmastart(priv->dma_rx, spi_dma_callback, (void *)priv);
sam_dmastart(priv->dma_tx, spi_dma_callback, priv);
sam_dmastart(priv->dma_rx, spi_dma_callback, priv);
/* Enable SPI to trigger the TX DMA channel */

4
arch/arm/src/samv7/sam_mcan.c
View File

@ -1006,7 +1006,7 @@ static uint32_t g_mcan0_msgram[MCAN0_MSGRAM_WORDS]
/* Constant configuration */
static struct sam_config_s g_mcan0const =
static const struct sam_config_s g_mcan0const =
{
.rxpinset = GPIO_MCAN0_RX,
.txpinset = GPIO_MCAN0_TX,
@ -1104,7 +1104,7 @@ static uint32_t g_mcan1_msgram[MCAN1_MSGRAM_WORDS]
/* MCAN1 constant configuration */
static struct sam_config_s g_mcan1const =
static const struct sam_config_s g_mcan1const =
{
.rxpinset = GPIO_MCAN1_RX,
.txpinset = GPIO_MCAN1_TX,

2
arch/arm/src/samv7/sam_qspi.c
View File

@ -856,7 +856,7 @@ static int qspi_memory_dma(struct sam_qspidev_s *priv,
/* Start the DMA */
priv->result = -EBUSY;
ret = sam_dmastart(priv->dmach, qspi_dma_callback, (void *)priv);
ret = sam_dmastart(priv->dmach, qspi_dma_callback, priv);
if (ret < 0)
{
spierr("ERROR: sam_dmastart failed: %d\n", ret);

2
arch/arm/src/samv7/sam_xdmac.c
View File

@ -189,7 +189,7 @@ static const struct sam_pidmap_s g_xdmac_txchan[] =
/* This array describes the available link list descriptors */
struct chnext_view1_s g_lldesc[CONFIG_SAMV7_NLLDESC];
static struct chnext_view1_s g_lldesc[CONFIG_SAMV7_NLLDESC];
/* This array describes the state of each XDMAC channel 0 */

1
arch/arm/src/stm32/stm32_dma2d.c
View File

@ -110,7 +110,6 @@ struct stm32_dma2d_s
#ifdef CONFIG_STM32_FB_CMAP
uint32_t *clut; /* Color lookup table */
#endif
mutex_t *lock; /* Ensure mutually exclusive access */
};

2
arch/arm/src/stm32/stm32_hciuart.c
View File

@ -382,7 +382,7 @@ static const struct hciuart_config_s g_hciusart1_config =
.rxbuffer = g_usart1_rxbuffer,
.txbuffer = g_usart1_txbuffer,
#ifdef CONFIG_STM32_HCIUART1_RXDMA
.rxdmabuffer = ,
.rxdmabuffer = g_usart1_rxdmabuffer,
#endif
.rxbufsize = CONFIG_STM32_HCIUART1_RXBUFSIZE,
.txbufsize = CONFIG_STM32_HCIUART1_TXBUFSIZE,

9
arch/arm/src/stm32/stm32_i2c_v2.c
View File

@ -2468,11 +2468,18 @@ static int stm32_i2c_process(struct i2c_master_s *dev,
static int stm32_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count)
{
struct stm32_i2c_priv_s *priv;
int ret;
DEBUGASSERT(dev);
/* Get I2C private structure */
priv = ((struct stm32_i2c_inst_s *)dev)->priv;
/* Ensure that address or flags don't change meanwhile */
ret = nxmutex_lock(&((struct stm32_i2c_inst_s *)dev)->priv->lock);
ret = nxmutex_lock(&priv->lock);
if (ret >= 0)
{
ret = stm32_i2c_process(dev, msgs, count);

24
arch/arm/src/stm32/stm32_spi.c
View File

@ -350,7 +350,7 @@ static struct stm32_spidev_s g_spi1dev =
{
.spidev =
{
&g_sp1iops
.ops = &g_sp1iops
},
.spibase = STM32_SPI1_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
@ -361,7 +361,7 @@ static struct stm32_spidev_s g_spi1dev =
# ifdef CONFIG_STM32_SPI1_DMA
.rxch = DMACHAN_SPI1_RX,
.txch = DMACHAN_SPI1_TX,
#if defined(SPI1_DMABUFSIZE_ADJUSTED)
# ifdef SPI1_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi1_rxbuf,
.txbuf = g_spi1_txbuf,
.buflen = SPI1_DMABUFSIZE_ADJUSTED,
@ -418,7 +418,7 @@ static struct stm32_spidev_s g_spi2dev =
{
.spidev =
{
&g_sp2iops
.ops = &g_sp2iops
},
.spibase = STM32_SPI2_BASE,
.spiclock = STM32_PCLK1_FREQUENCY,
@ -429,7 +429,7 @@ static struct stm32_spidev_s g_spi2dev =
# ifdef CONFIG_STM32_SPI2_DMA
.rxch = DMACHAN_SPI2_RX,
.txch = DMACHAN_SPI2_TX,
#if defined(SPI2_DMABUFSIZE_ADJUSTED)
# ifdef SPI2_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi2_rxbuf,
.txbuf = g_spi2_txbuf,
.buflen = SPI2_DMABUFSIZE_ADJUSTED,
@ -486,7 +486,7 @@ static struct stm32_spidev_s g_spi3dev =
{
.spidev =
{
&g_sp3iops
.ops = &g_sp3iops
},
.spibase = STM32_SPI3_BASE,
.spiclock = STM32_PCLK1_FREQUENCY,
@ -497,7 +497,7 @@ static struct stm32_spidev_s g_spi3dev =
# ifdef CONFIG_STM32_SPI3_DMA
.rxch = DMACHAN_SPI3_RX,
.txch = DMACHAN_SPI3_TX,
#if defined(SPI3_DMABUFSIZE_ADJUSTED)
# ifdef SPI3_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi3_rxbuf,
.txbuf = g_spi3_txbuf,
.buflen = SPI3_DMABUFSIZE_ADJUSTED,
@ -554,7 +554,7 @@ static struct stm32_spidev_s g_spi4dev =
{
.spidev =
{
&g_sp4iops
.ops = &g_sp4iops
},
.spibase = STM32_SPI4_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
@ -565,7 +565,7 @@ static struct stm32_spidev_s g_spi4dev =
# ifdef CONFIG_STM32_SPI4_DMA
.rxch = DMACHAN_SPI4_RX,
.txch = DMACHAN_SPI4_TX,
#if defined(SPI4_DMABUFSIZE_ADJUSTED)
# ifdef SPI4_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi4_rxbuf,
.txbuf = g_spi4_txbuf,
.buflen = SPI4_DMABUFSIZE_ADJUSTED,
@ -622,7 +622,7 @@ static struct stm32_spidev_s g_spi5dev =
{
.spidev =
{
&g_sp5iops
.ops = &g_sp5iops
},
.spibase = STM32_SPI5_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
@ -633,7 +633,7 @@ static struct stm32_spidev_s g_spi5dev =
# ifdef CONFIG_STM32_SPI5_DMA
.rxch = DMACHAN_SPI5_RX,
.txch = DMACHAN_SPI5_TX,
#if defined(SPI5_DMABUFSIZE_ADJUSTED)
# ifdef SPI5_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi5_rxbuf,
.txbuf = g_spi5_txbuf,
.buflen = SPI5_DMABUFSIZE_ADJUSTED,
@ -690,7 +690,7 @@ static struct stm32_spidev_s g_spi6dev =
{
.spidev =
{
&g_sp6iops
.ops = &g_sp6iops
},
.spibase = STM32_SPI6_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
@ -701,7 +701,7 @@ static struct stm32_spidev_s g_spi6dev =
# ifdef CONFIG_STM32_SPI6_DMA
.rxch = DMACHAN_SPI6_RX,
.txch = DMACHAN_SPI6_TX,
#if defined(SPI6_DMABUFSIZE_ADJUSTED)
# ifdef SPI6_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi6_rxbuf,
.txbuf = g_spi6_txbuf,
.buflen = SPI6_DMABUFSIZE_ADJUSTED,

9
arch/arm/src/stm32f0l0g0/stm32_i2c.c
View File

@ -2464,11 +2464,18 @@ static int stm32_i2c_process(struct i2c_master_s *dev,
static int stm32_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count)
{
struct stm32_i2c_priv_s *priv;
int ret;
DEBUGASSERT(dev);
/* Get I2C private structure */
priv = ((struct stm32_i2c_inst_s *)dev)->priv;
/* Ensure that address or flags don't change meanwhile */
ret = nxmutex_lock(&((struct stm32_i2c_inst_s *)dev)->priv->lock);
ret = nxmutex_lock(&priv->lock);
if (ret >= 0)
{
ret = stm32_i2c_process(dev, msgs, count);

6
arch/arm/src/stm32f0l0g0/stm32_spi.c
View File

@ -313,7 +313,7 @@ static struct stm32_spidev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.spibase = STM32_SPI1_BASE,
.spiclock = SPI1_PCLK_FREQUENCY,
@ -372,7 +372,7 @@ static struct stm32_spidev_s g_spi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.spibase = STM32_SPI2_BASE,
.spiclock = SPI1_PCLK_FREQUENCY,
@ -429,7 +429,7 @@ static struct stm32_spidev_s g_spi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.spibase = STM32_SPI3_BASE,
.spiclock = SPI1_PCLK_FREQUENCY,

9
arch/arm/src/stm32f7/stm32_i2c.c
View File

@ -2505,11 +2505,18 @@ static int stm32_i2c_process(struct i2c_master_s *dev,
static int stm32_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count)
{
struct stm32_i2c_priv_s *priv;
int ret;
DEBUGASSERT(dev);
/* Get I2C private structure */
priv = ((struct stm32_i2c_inst_s *)dev)->priv;
/* Ensure that address or flags don't change meanwhile */
ret = nxmutex_lock(&((struct stm32_i2c_inst_s *)dev)->priv->lock);
ret = nxmutex_lock(&priv->lock);
if (ret >= 0)
{
ret = stm32_i2c_process(dev, msgs, count);

24
arch/arm/src/stm32f7/stm32_spi.c
View File

@ -330,7 +330,7 @@ static struct stm32_spidev_s g_spi1dev =
{
.spidev =
{
&g_sp1iops
.ops = &g_sp1iops,
},
.spibase = STM32_SPI1_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
@ -341,7 +341,7 @@ static struct stm32_spidev_s g_spi1dev =
# ifdef CONFIG_STM32F7_SPI1_DMA
.rxch = DMAMAP_SPI1_RX,
.txch = DMAMAP_SPI1_TX,
#if defined(SPI1_DMABUFSIZE_ADJUSTED)
# ifdef SPI1_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi1_rxbuf,
.txbuf = g_spi1_txbuf,
.buflen = SPI1_DMABUFSIZE_ADJUSTED,
@ -401,7 +401,7 @@ static struct stm32_spidev_s g_spi2dev =
{
.spidev =
{
&g_sp2iops
.ops = &g_sp2iops,
},
.spibase = STM32_SPI2_BASE,
.spiclock = STM32_PCLK1_FREQUENCY,
@ -412,7 +412,7 @@ static struct stm32_spidev_s g_spi2dev =
# ifdef CONFIG_STM32F7_SPI2_DMA
.rxch = DMAMAP_SPI2_RX,
.txch = DMAMAP_SPI2_TX,
#if defined(SPI2_DMABUFSIZE_ADJUSTED)
# ifdef SPI3_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi2_rxbuf,
.txbuf = g_spi2_txbuf,
.buflen = SPI2_DMABUFSIZE_ADJUSTED,
@ -472,7 +472,7 @@ static struct stm32_spidev_s g_spi3dev =
{
.spidev =
{
&g_sp3iops
.ops = &g_sp3iops,
},
.spibase = STM32_SPI3_BASE,
.spiclock = STM32_PCLK1_FREQUENCY,
@ -483,7 +483,7 @@ static struct stm32_spidev_s g_spi3dev =
# ifdef CONFIG_STM32F7_SPI3_DMA
.rxch = DMAMAP_SPI3_RX,
.txch = DMAMAP_SPI3_TX,
#if defined(SPI3_DMABUFSIZE_ADJUSTED)
# ifdef SPI3_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi3_rxbuf,
.txbuf = g_spi3_txbuf,
.buflen = SPI3_DMABUFSIZE_ADJUSTED,
@ -543,7 +543,7 @@ static struct stm32_spidev_s g_spi4dev =
{
.spidev =
{
&g_sp4iops
.ops = &g_sp4iops,
},
.spibase = STM32_SPI4_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
@ -554,7 +554,7 @@ static struct stm32_spidev_s g_spi4dev =
# ifdef CONFIG_STM32F7_SPI4_DMA
.rxch = DMAMAP_SPI4_RX,
.txch = DMAMAP_SPI4_TX,
#if defined(SPI4_DMABUFSIZE_ADJUSTED)
# ifdef SPI4_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi4_rxbuf,
.txbuf = g_spi4_txbuf,
.buflen = SPI4_DMABUFSIZE_ADJUSTED,
@ -614,7 +614,7 @@ static struct stm32_spidev_s g_spi5dev =
{
.spidev =
{
&g_sp5iops
.ops = &g_sp5iops,
},
.spibase = STM32_SPI5_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
@ -625,7 +625,7 @@ static struct stm32_spidev_s g_spi5dev =
# ifdef CONFIG_STM32F7_SPI5_DMA
.rxch = DMAMAP_SPI5_RX,
.txch = DMAMAP_SPI5_TX,
#if defined(SPI5_DMABUFSIZE_ADJUSTED)
# ifdef SPI5_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi5_rxbuf,
.txbuf = g_spi5_txbuf,
.buflen = SPI5_DMABUFSIZE_ADJUSTED,
@ -685,7 +685,7 @@ static struct stm32_spidev_s g_spi6dev =
{
.spidev =
{
&g_sp6iops
.ops = &g_sp6iops,
},
.spibase = STM32_SPI6_BASE,
.spiclock = STM32_PCLK2_FREQUENCY,
@ -696,7 +696,7 @@ static struct stm32_spidev_s g_spi6dev =
# ifdef CONFIG_STM32F7_SPI6_DMA
.rxch = DMAMAP_SPI6_RX,
.txch = DMAMAP_SPI6_TX,
#if defined(SPI6_DMABUFSIZE_ADJUSTED)
# ifdef SPI6_DMABUFSIZE_ADJUSTED
.rxbuf = g_spi6_rxbuf,
.txbuf = g_spi6_txbuf,
.buflen = SPI6_DMABUFSIZE_ADJUSTED,

9
arch/arm/src/stm32h7/stm32_i2c.c
View File

@ -2469,11 +2469,18 @@ static int stm32_i2c_process(struct i2c_master_s *dev,
static int stm32_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count)
{
struct stm32_i2c_priv_s *priv;
int ret;
DEBUGASSERT(dev);
/* Get I2C private structure */
priv = ((struct stm32_i2c_inst_s *)dev)->priv;
/* Ensure that address or flags don't change meanwhile */
ret = nxmutex_lock(&((struct stm32_i2c_inst_s *)dev)->priv->lock);
ret = nxmutex_lock(&priv->lock);
if (ret >= 0)
{
ret = stm32_i2c_process(dev, msgs, count);

8
arch/arm/src/stm32h7/stm32_serial.c
View File

@ -2274,7 +2274,7 @@ static int up_dma_setup(struct uart_dev_s *dev)
* worth of time to claim bytes before they are overwritten.
*/
stm32_dmastart(priv->rxdma, up_dma_rxcallback, (void *)priv, true);
stm32_dmastart(priv->rxdma, up_dma_rxcallback, priv, true);
}
#endif
@ -3253,7 +3253,7 @@ static void up_dma_reenable(struct up_dev_s *priv)
* worth of time to claim bytes before they are overwritten.
*/
stm32_dmastart(priv->rxdma, up_dma_rxcallback, (void *)priv, true);
stm32_dmastart(priv->rxdma, up_dma_rxcallback, priv, true);
/* Clear DMA suspended flag. */
@ -3352,7 +3352,7 @@ static void up_dma_txcallback(DMA_HANDLE handle, uint8_t status, void *arg)
/* Start transmission with the callback on DMA completion */
stm32_dmastart(priv->txdma, up_dma_txcallback,
(void *)priv, false);
priv, false);
return;
}
@ -3438,7 +3438,7 @@ static void up_dma_send(struct uart_dev_s *dev)
/* Start transmission with the callback on DMA completion */
stm32_dmastart(priv->txdma, up_dma_txcallback, (void *)priv, false);
stm32_dmastart(priv->txdma, up_dma_txcallback, priv, false);
}
#endif

12
arch/arm/src/stm32h7/stm32_spi.c
View File

@ -396,7 +396,7 @@ static struct stm32_spidev_s g_spi1dev =
{
.spidev =
{
&g_sp1iops
.ops = &g_sp1iops,
},
.spibase = STM32_SPI1_BASE,
.spiclock = SPI123_KERNEL_CLOCK_FREQ,
@ -468,7 +468,7 @@ static struct stm32_spidev_s g_spi2dev =
{
.spidev =
{
&g_sp2iops
.ops = &g_sp2iops,
},
.spibase = STM32_SPI2_BASE,
.spiclock = SPI123_KERNEL_CLOCK_FREQ,
@ -540,7 +540,7 @@ static struct stm32_spidev_s g_spi3dev =
{
.spidev =
{
&g_sp3iops
.ops = &g_sp3iops,
},
.spibase = STM32_SPI3_BASE,
.spiclock = SPI123_KERNEL_CLOCK_FREQ,
@ -612,7 +612,7 @@ static struct stm32_spidev_s g_spi4dev =
{
.spidev =
{
&g_sp4iops
.ops = &g_sp4iops,
},
.spibase = STM32_SPI4_BASE,
.spiclock = SPI45_KERNEL_CLOCK_FREQ,
@ -684,7 +684,7 @@ static struct stm32_spidev_s g_spi5dev =
{
.spidev =
{
&g_sp5iops
.ops = &g_sp5iops,
},
.spibase = STM32_SPI5_BASE,
.spiclock = SPI45_KERNEL_CLOCK_FREQ,
@ -757,7 +757,7 @@ static struct stm32_spidev_s g_spi6dev =
{
.spidev =
{
&g_sp6iops
.ops = &g_sp6iops,
},
.spibase = STM32_SPI6_BASE,
.spiclock = SPI6_KERNEL_CLOCK_FREQ,

6
arch/arm/src/stm32l4/stm32l4_spi.c
View File

@ -281,7 +281,7 @@ static struct stm32l4_spidev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.spibase = STM32L4_SPI1_BASE,
.spiclock = STM32L4_PCLK2_FREQUENCY,
@ -339,7 +339,7 @@ static struct stm32l4_spidev_s g_spi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.spibase = STM32L4_SPI2_BASE,
.spiclock = STM32L4_PCLK1_FREQUENCY,
@ -395,7 +395,7 @@ static struct stm32l4_spidev_s g_spi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.spibase = STM32L4_SPI3_BASE,
.spiclock = STM32L4_PCLK1_FREQUENCY,

6
arch/arm/src/stm32l5/stm32l5_spi.c
View File

@ -281,7 +281,7 @@ static struct stm32l5_spidev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.spibase = STM32L5_SPI1_BASE,
.spiclock = STM32L5_PCLK2_FREQUENCY,
@ -339,7 +339,7 @@ static struct stm32l5_spidev_s g_spi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.spibase = STM32L5_SPI2_BASE,
.spiclock = STM32L5_PCLK1_FREQUENCY,
@ -395,7 +395,7 @@ static struct stm32l5_spidev_s g_spi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.spibase = STM32L5_SPI3_BASE,
.spiclock = STM32L5_PCLK1_FREQUENCY,

6
arch/arm/src/stm32u5/stm32_spi.c
View File

@ -348,7 +348,7 @@ static struct stm32_spidev_s g_spi1dev =
{
.spidev =
{
&g_sp1iops
.ops = &g_sp1iops,
},
.spibase = STM32_SPI1_BASE,
.spiclock = SPI1_KERNEL_CLOCK_FREQ,
@ -420,7 +420,7 @@ static struct stm32_spidev_s g_spi2dev =
{
.spidev =
{
&g_sp2iops
.ops = &g_sp2iops,
},
.spibase = STM32_SPI2_BASE,
.spiclock = SPI2_KERNEL_CLOCK_FREQ,
@ -492,7 +492,7 @@ static struct stm32_spidev_s g_spi3dev =
{
.spidev =
{
&g_sp3iops
.ops = &g_sp3iops,
},
.spibase = STM32_SPI3_BASE,
.spiclock = SPI3_KERNEL_CLOCK_FREQ,

4
arch/arm/src/stm32wb/stm32wb_spi.c
View File

@ -277,7 +277,7 @@ static struct stm32wb_spidev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.spibase = STM32WB_SPI1_BASE,
.spiclock = STM32WB_PCLK2_FREQUENCY,
@ -335,7 +335,7 @@ static struct stm32wb_spidev_s g_spi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.spibase = STM32WB_SPI2_BASE,
.spiclock = STM32WB_PCLK1_FREQUENCY,

2
arch/arm/src/stm32wl5/stm32wl5_spi.c
View File

@ -312,7 +312,7 @@ static struct stm32wl5_spidev_s g_spi1dev =
{
.spidev =
{
&g_sp1iops
.ops = &g_sp1iops,
},
.spibase = STM32WL5_SPI1_BASE,
.spiclock = STM32WL5_PCLK2_FREQUENCY,

2
arch/avr/src/avr/up_spi.c
View File

@ -106,7 +106,7 @@ static struct avr_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
.ops = &g_spiops,
},
.lock = NXMUTEX_INITIALIZER,
};

8
arch/mips/src/pic32mx/pic32mx_spi.c
View File

@ -138,7 +138,7 @@ static struct pic32mx_dev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.base = PIC32MX_SPI1_K1BASE,
#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
@ -177,7 +177,7 @@ static struct pic32mx_dev_s g_spi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.base = PIC32MX_SPI2_K1BASE,
#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
@ -216,7 +216,7 @@ static struct pic32mx_dev_s g_spi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.base = PIC32MX_SPI3_K1BASE,
#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS
@ -255,7 +255,7 @@ static struct pic32mx_dev_s g_spi4dev =
{
.spidev =
{
&g_spi4ops
.ops = &g_spi4ops,
},
.base = PIC32MX_SPI4_K1BASE,
#ifdef CONFIG_PIC32MX_SPI_INTERRUPTS

16
arch/mips/src/pic32mz/pic32mz_spi.c
View File

@ -281,7 +281,7 @@ static struct pic32mz_dev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.config = &g_spi1config,
.lock = NXMUTEX_INITIALIZER,
@ -334,7 +334,7 @@ static struct pic32mz_dev_s g_spi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.config = &g_spi2config,
.lock = NXMUTEX_INITIALIZER,
@ -387,7 +387,7 @@ static struct pic32mz_dev_s g_spi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.config = &g_spi3config,
.lock = NXMUTEX_INITIALIZER,
@ -440,7 +440,7 @@ static struct pic32mz_dev_s g_spi4dev =
{
.spidev =
{
&g_spi4ops
.ops = &g_spi4ops,
},
.config = &g_spi4config,
.lock = NXMUTEX_INITIALIZER,
@ -493,7 +493,7 @@ static struct pic32mz_dev_s g_spi5dev =
{
.spidev =
{
&g_spi5ops
.ops = &g_spi5ops,
},
.config = &g_spi5config,
.lock = NXMUTEX_INITIALIZER,
@ -546,7 +546,7 @@ static struct pic32mz_dev_s g_spi6dev =
{
.spidev =
{
&g_spi6ops
.ops = &g_spi6ops,
},
.config = &g_spi6config,
.lock = NXMUTEX_INITIALIZER,
@ -1752,7 +1752,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
priv->result = -EBUSY;
ret = pic32mz_dma_start(priv->rxdma, spi_dmarxcallback, (void *)priv);
ret = pic32mz_dma_start(priv->rxdma, spi_dmarxcallback, priv);
if (ret < 0)
{
spierr("ERROR: RX DMA start failed: %d\n", ret);
@ -1761,7 +1761,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
spi_rxdma_sample(priv, DMA_AFTER_START);
ret = pic32mz_dma_start(priv->txdma, spi_dmatxcallback, (void *)priv);
ret = pic32mz_dma_start(priv->txdma, spi_dmatxcallback, priv);
if (ret < 0)
{
spierr("ERROR: TX DMA start failed: %d\n", ret);

10
arch/renesas/src/rx65n/rx65n_rspi.c
View File

@ -296,7 +296,7 @@ static struct rx65n_rspidev_s g_rspi0dev =
{
.rspidev =
{
&g_rspi0ops
.ops = &g_rspi0ops,
},
.rspibase = RX65N_RSPI0_BASE,
.rspiclock = RX65N_PCLK_FREQUENCY,
@ -362,7 +362,7 @@ static struct rx65n_rspidev_s g_rspi1dev =
{
.rspidev =
{
&g_rspi1ops
.ops = &g_rspi1ops,
},
.rspibase = RX65N_RSPI1_BASE,
.rspiclock = RX65N_PCLK_FREQUENCY,
@ -428,7 +428,7 @@ static struct rx65n_rspidev_s g_rspi2dev =
{
.rspidev =
{
&g_rspi2ops
.ops = &g_rspi2ops,
},
.rspibase = RX65N_RSPI2_BASE,
.rspiclock = RX65N_PCLK_FREQUENCY,
@ -1018,8 +1018,8 @@ static void rspi_startxfr(struct rx65n_rspidev_s *priv)
#ifdef CONFIG_RX65N_RSPI_DTC_DT_MODE
static dtc_err_t rspi_dtctxsetup(FAR struct rx65n_rspidev_s *priv,
FAR const void *txbuffer, FAR const void *txdummy,
size_t nwords)
FAR const void *txbuffer,
FAR const void *txdummy, size_t nwords)
{
dtc_err_t ret = DTC_SUCCESS;
dtc_dynamic_transfer_data_cfg_t dcfg;

6
arch/renesas/src/rx65n/rx65n_rspi_sw.c
View File

@ -279,7 +279,7 @@ static struct rx65n_rspidev_s g_rspi0dev =
{
.rspidev =
{
&g_rspi0ops
.ops = &g_rspi0ops,
},
.rspibase = RX65N_RSPI0_BASE,
.rspiclock = RX65N_PCLK_FREQUENCY,
@ -333,7 +333,7 @@ static struct rx65n_rspidev_s g_rspi1dev =
{
.rspidev =
{
&g_rspi1ops
.ops = &g_rspi1ops,
},
.rspibase = RX65N_RSPI1_BASE,
.rspiclock = RX65N_PCLK_FREQUENCY,
@ -387,7 +387,7 @@ static struct rx65n_rspidev_s g_rspi2dev =
{
.rspidev =
{
&g_rspi2ops
.ops = &g_rspi2ops,
},
.rspibase = RX65N_RSPI2_BASE,
.rspiclock = RX65N_PCLK_FREQUENCY,

283
arch/renesas/src/rx65n/rx65n_usbhost.c
View File

@ -970,7 +970,7 @@ void hw_usb_hmodule_init (void)
uint16_t hw_usb_read_syscfg(void)
{
return (rx65n_usbhost_getreg(RX65N_USB_SYSCFG));
return rx65n_usbhost_getreg(RX65N_USB_SYSCFG);
}
/****************************************************************************
@ -1007,7 +1007,7 @@ void hw_usb_clear_usbe (void)
static uint16_t hw_usb_read_syssts(void)
{
return (rx65n_usbhost_getreg(RX65N_USB_SYSSTS0));
return rx65n_usbhost_getreg(RX65N_USB_SYSSTS0);
}
/****************************************************************************
@ -1019,7 +1019,7 @@ static uint16_t hw_usb_read_syssts (void)
static uint16_t hw_usb_read_dvstctr(void)
{
return (rx65n_usbhost_getreg(RX65N_USB_DVSTCTR0));
return rx65n_usbhost_getreg(RX65N_USB_DVSTCTR0);
}
/****************************************************************************
@ -1694,7 +1694,7 @@ static uint16_t hw_usb_read_pipectr (uint16_t pipeno)
p_reg = (uint16_t *)(RX65N_USB_PIPE1CTR + (pipeno - 1));
}
return (rx65n_usbhost_getreg (p_reg));
return rx65n_usbhost_getreg(p_reg);
}
/****************************************************************************
@ -2123,8 +2123,8 @@ uint16_t usb_hstd_write_data_control_pipe (uint8_t * buf_add,
uint16_t end_flag;
buffer = usb_cstd_is_set_frdy(USB_PIPE0,
(uint16_t) RX65N_USB_USING_CFIFO,
(uint16_t) RX65N_USB_CFIFOSEL_ISEL);
RX65N_USB_USING_CFIFO,
RX65N_USB_CFIFOSEL_ISEL);
/* Check error */
@ -2132,7 +2132,7 @@ uint16_t usb_hstd_write_data_control_pipe (uint8_t * buf_add,
{
/* FIFO access error */
return (USB_FIFOERROR);
return USB_FIFOERROR;
}
/* Data buffer size */
@ -2225,7 +2225,7 @@ uint16_t pipe, uint16_t pipemode)
/* Changes FIFO port by the pipe. */
buffer = usb_cstd_is_set_frdy(pipe, (uint16_t) pipemode, USB_FALSE);
buffer = usb_cstd_is_set_frdy(pipe, pipemode, USB_FALSE);
/* Check error */
@ -2233,7 +2233,7 @@ uint16_t pipe, uint16_t pipemode)
{
/* FIFO access error */
return (USB_FIFOERROR);
return USB_FIFOERROR;
}
/* Data buffer size */
@ -2329,7 +2329,7 @@ void usb_hstd_receive_start (uint8_t *buffer, size_t buflen, uint8_t pipe)
/* Ignore count clear */
hw_usb_clear_status_bemp((uint16_t) pipe); /* BEMP Status Clear */
hw_usb_clear_status_bemp(pipe); /* BEMP Status Clear */
hw_usb_clear_sts_brdy(pipe); /* BRDY Status Clear */
hw_usb_clear_status_nrdy(pipe); /* NRDY Status Clear */
nrdy_retries[pipe] = 0; /* Initialize theh NRDY retries to 0 */
@ -2342,22 +2342,21 @@ void usb_hstd_receive_start (uint8_t *buffer, size_t buflen, uint8_t pipe)
length = buflen;
if ((uint32_t) 0u != length)
if (0u != length)
{
/* Data length check */
if ((uint32_t) 0u == (length % mxps))
if ((0u == (length % mxps))
{
/* Set Transaction counter */
usb_cstd_set_transaction_counter(pipe, (uint16_t) (length / mxps));
usb_cstd_set_transaction_counter(pipe, length / mxps);
}
else
{
/* Set Transaction counter */
usb_cstd_set_transaction_counter(pipe, (uint16_t) ((length / mxps)
+ (uint32_t) 1u));
usb_cstd_set_transaction_counter(pipe, length / mxps + 1u));
}
}
@ -2488,17 +2487,17 @@ uint16_t usb_hstd_read_data_control_pipe (void)
/* Changes FIFO port by the pipe. */
buffer = usb_cstd_is_set_frdy(USB_PIPE0, (uint16_t) USB_CUSE, USB_FALSE);
buffer = usb_cstd_is_set_frdy(USB_PIPE0, USB_CUSE, USB_FALSE);
if (USB_FIFOERROR == buffer)
{
/* FIFO access error */
return (USB_FIFOERROR);
return USB_FIFOERROR;
syslog(LOG_INFO, "FIFO ERROR");
}
dtln = (uint16_t) (buffer & RX65N_USB_FIFOCTR_DTLN);
dtln = buffer & RX65N_USB_FIFOCTR_DTLN;
/* Max Packet Size */
@ -2559,7 +2558,7 @@ uint16_t usb_hstd_read_data_control_pipe (void)
g_rx65n_tdlist[USB_PIPE0].ed->xfrinfo->xfrd += count;
return (end_flag);
return end_flag;
}
/****************************************************************************
@ -2586,14 +2585,14 @@ uint16_t usb_hstd_read_data (uint16_t pipe, uint16_t pipemode)
if (pipe != 0) /* Data transfer for non CTRL pipe */
{
buffer = usb_cstd_is_set_frdy(pipe, (uint16_t) pipemode, USB_FALSE);
buffer = usb_cstd_is_set_frdy(pipe, pipemode, USB_FALSE);
if (USB_FIFOERROR == buffer)
{
return (USB_FIFOERROR);
return USB_FIFOERROR;
}
dtln = (uint16_t) (buffer & RX65N_USB_FIFOCTR_DTLN);
dtln = buffer & RX65N_USB_FIFOCTR_DTLN;
mxps = usb_cstd_get_maxpacket_size(pipe);
/* now calculate the count */
@ -2656,7 +2655,7 @@ uint16_t usb_hstd_read_data (uint16_t pipe, uint16_t pipemode)
}
}
return (end_flag);
return end_flag;
}
/****************************************************************************
@ -2766,11 +2765,11 @@ void usb_hstd_buf_to_fifo (uint8_t *buffer, size_t buflen, uint16_t pipe,
/* FIFO access error */
syslog(LOG_INFO, "### FIFO access error\n");
usb_hstd_forced_termination(pipe, (uint16_t) USB_DATA_ERR);
usb_hstd_forced_termination(pipe, USB_DATA_ERR);
break;
default:
usb_hstd_forced_termination(pipe, (uint16_t) USB_DATA_ERR);
usb_hstd_forced_termination(pipe, USB_DATA_ERR);
break;
}
}
@ -2817,8 +2816,7 @@ void usb_hstd_brdy_pipe_process (uint16_t bitsts)
RX65N_USB_DCPCTR_PIDSTALL))
{
syslog(LOG_INFO, "### STALL Pipe %d\n", i);
usb_hstd_forced_termination(i,
(uint16_t) USB_DATA_STALL);
usb_hstd_forced_termination(i, USB_DATA_STALL);
}
else
{
@ -2862,7 +2860,7 @@ void usb_hstd_brdy_pipe_process (uint16_t bitsts)
else
{
usb_hstd_data_end(i, (uint16_t) USB_DATA_OK);
usb_hstd_data_end(i, USB_DATA_OK);
g_rx65n_edlist[i].xfrinfo->tdstatus =
TD_CC_NOERROR;
@ -2870,8 +2868,7 @@ void usb_hstd_brdy_pipe_process (uint16_t bitsts)
if ((g_rx65n_edlist[i].xfrinfo != 0)
&& (g_rx65n_edlist[i].xfrinfo->callback))
{
hw_usb_write_dcpmxps((uint16_t) (USB_DEFPACKET
+ USB_DEVICE_1));
hw_usb_write_dcpmxps(USB_DEFPACKET + USB_DEVICE_1);
rx65n_usbhost_asynch_completion(priv,
&g_rx65n_edlist[i]);
}
@ -2950,13 +2947,13 @@ void usb_hstd_bemp_pipe_process (uint16_t bitsts)
RX65N_USB_DCPCTR_PIDSTALL))
{
syslog(LOG_INFO, "### STALL Pipe %d\n", i);
usb_hstd_forced_termination(i, (uint16_t) USB_DATA_STALL);
usb_hstd_forced_termination(i, USB_DATA_STALL);
}
else
{
if (data_len == 0)
{
usb_hstd_data_end(i, (uint16_t) USB_DATA_OK);
usb_hstd_data_end(i, USB_DATA_OK);
g_rx65n_edlist[i].xfrinfo->tdstatus = TD_CC_NOERROR;
/* Release the semaphore for this pipe */
@ -2966,8 +2963,9 @@ void usb_hstd_bemp_pipe_process (uint16_t bitsts)
else
{
syslog (LOG_INFO, "BEMP can NOT be with %d len data \
for pipe\n", data_len, i);
syslog(LOG_INFO,
"BEMP can NOT be with %d len data for pipe\n",
data_len, i);
}
}
}
@ -3005,14 +3003,14 @@ uint16_t usb_hstd_get_pipe_peri_value (uint8_t binterval)
work2 = 0;
for (; work1 != 0; work2++ )
{
work1 = (uint16_t)(work1 >> 1);
work1 >>= 1;
}
if (0 != work2)
{
/* Interval time */
pipe_peri |= (uint16_t)(work2 - 1);
pipe_peri |= (work2 - 1);
}
}
@ -3034,7 +3032,7 @@ uint16_t usb_hstd_chk_attach (void)
uint16_t buf[3];
usb_hstd_read_lnst(buf);
if (0 == (uint16_t) (buf[1] & RX65N_USB_DVSTCTR0_RHST))
if (0 == (buf[1] & RX65N_USB_DVSTCTR0_RHST))
{
if (RX65N_USB_SYSSTS0_LNST_FS_JSTS == (buf[0] & 3))
{
@ -3117,7 +3115,7 @@ uint16_t usb_hstd_detach_process (void)
{
/* End of data transfer (IN/OUT) */
usb_hstd_forced_termination(USB_PIPE0, (uint16_t) USB_DATA_STOP);
usb_hstd_forced_termination(USB_PIPE0, USB_DATA_STOP);
}
usb_cstd_clr_pipe_cnfg(USB_PIPE0);
@ -3138,7 +3136,7 @@ uint16_t usb_hstd_detach_process (void)
{
/* End of data transfer (IN/OUT) */
usb_hstd_forced_termination(i, (uint16_t) USB_DATA_STOP);
usb_hstd_forced_termination(i, USB_DATA_STOP);
}
usb_cstd_clr_pipe_cnfg(i);
@ -3166,7 +3164,7 @@ uint16_t usb_hstd_detach_process (void)
/* Check clock */
usb_hstd_chk_clk((uint16_t) USB_DETACH);
usb_hstd_chk_clk(USB_DETACH);
break;
default:
@ -3177,7 +3175,7 @@ uint16_t usb_hstd_detach_process (void)
/* Check clock */
usb_hstd_chk_clk((uint16_t) USB_DETACH);
usb_hstd_chk_clk(USB_DETACH);
break;
}
@ -3293,11 +3291,11 @@ uint16_t usb_hstd_attach_process (void)
/* Check clock */
usb_hstd_chk_clk((uint16_t) USB_DETACH);
usb_hstd_chk_clk(USB_DETACH);
break;
default:
usb_hstd_attach((uint16_t) USB_ATTACHF);
usb_hstd_attach(USB_ATTACHF);
break;
}
@ -3335,7 +3333,7 @@ void usb_hstd_bus_reset (void)
/* Wait 50ms */
up_mdelay(50); /* usb_cpu_delay_xms((uint16_t) 50); */
up_mdelay(50); /* usb_cpu_delay_xms(50); */
/* USBRST=0, RESUME=0, UACT=1 */
@ -3343,7 +3341,7 @@ void usb_hstd_bus_reset (void)
/* Wait 10ms or more (USB reset recovery) */
up_mdelay(20); /* usb_cpu_delay_xms((uint16_t) 20); */
up_mdelay(20); /* usb_cpu_delay_xms(20); */
/* WAIT_LOOP */
@ -3355,8 +3353,7 @@ void usb_hstd_bus_reset (void)
{
/* DeviceStateControlRegister - ResetHandshakeStatusCheck */
buf = hw_usb_read_dvstctr();
buf = (uint16_t) (buf & RX65N_USB_DVSTCTR0_RHST);
buf = hw_usb_read_dvstctr() & RX65N_USB_DVSTCTR0_RHST;
if (0x04 == buf)
{
/* Wait */
@ -3386,7 +3383,7 @@ uint8_t *usb_hstd_write_fifo (uint16_t count, uint16_t pipemode,
{
/* WAIT_LOOP */
for (even = (uint16_t) (count >> 1); (0 != even); --even)
for (even = count >> 1; 0 != even; --even)
{
/* 16bit access */
@ -3397,7 +3394,7 @@ uint8_t *usb_hstd_write_fifo (uint16_t count, uint16_t pipemode,
write_p += sizeof(uint16_t);
}
if ((count & (uint16_t) 0x0001u) != 0u)
if ((count & 0x0001u) != 0u)
{
/* count == odd */
@ -3441,7 +3438,7 @@ uint8_t *usb_hstd_read_fifo (uint16_t count, uint16_t pipemode,
/* WAIT_LOOP */
for (even = (uint16_t) (count >> 1); (0 != even); --even)
for (even = count >> 1; 0 != even; --even)
{
/* 16bit FIFO access */
@ -3452,7 +3449,7 @@ uint8_t *usb_hstd_read_fifo (uint16_t count, uint16_t pipemode,
read_p += sizeof(uint16_t);
}
if ((count & (uint16_t) 0x0001) != 0)
if ((count & 0x0001) != 0)
{
/* 16bit FIFO access */
@ -3511,8 +3508,7 @@ void usb_hstd_forced_termination (uint16_t pipe, uint16_t status)
{
/* Changes the FIFO port by the pipe. */
usb_cstd_chg_curpipe((uint16_t) USB_PIPE0,
(uint16_t) USB_CUSE, USB_FALSE);
usb_cstd_chg_curpipe(USB_PIPE0, USB_CUSE, USB_FALSE);
}
#ifdef DMA_DTC_NOT_ENABLED
@ -3525,8 +3521,7 @@ void usb_hstd_forced_termination (uint16_t pipe, uint16_t status)
{
/* Changes the FIFO port by the pipe. */
usb_cstd_chg_curpipe(ptr, (uint16_t) USB_PIPE0,
(uint16_t) USB_D0USE, USB_FALSE);
usb_cstd_chg_curpipe(ptr, USB_PIPE0, USB_D0USE, USB_FALSE);
}
/* Clear D1FIFO-port */
@ -3536,8 +3531,7 @@ void usb_hstd_forced_termination (uint16_t pipe, uint16_t status)
{
/* Changes the FIFO port by the pipe. */
usb_cstd_chg_curpipe(ptr, (uint16_t) USB_PIPE0,
(uint16_t) USB_D1USE, USB_FALSE);
usb_cstd_chg_curpipe(ptr, USB_PIPE0, USB_D1USE, USB_FALSE);
}
#endif /* ((USB_CFG_DTC==USB_CFG_ENABLE)||(USB_CFG_DMA==USB_CFG_ENABLE)) */
@ -3603,7 +3597,7 @@ void usb_hstd_nrdy_endprocess (uint16_t pipe)
/* PIPEx Data Retry */
usb_hstd_data_end(pipe, (uint16_t) USB_DATA_TMO);
usb_hstd_data_end(pipe, USB_DATA_TMO);
hw_usb_set_bclr(USB_CUSE); /* Clear Buffer on CPU side */
g_rx65n_edlist[pipe].xfrinfo->tdstatus = TD_CC_DEVNOTRESPONDING;
@ -3674,10 +3668,10 @@ void usb_hstd_detach (void)
{
/* DVSTCTR clear */
hw_usb_clear_dvstctr((uint16_t) (RX65N_USB_DVSTCTR0_RWUPE |
hw_usb_clear_dvstctr(RX65N_USB_DVSTCTR0_RWUPE |
RX65N_USB_DVSTCTR0_USBRST |
RX65N_USB_DVSTCTR0_RESUME |
RX65N_USB_DVSTCTR0_UACT));
RX65N_USB_DVSTCTR0_UACT);
/* ATTCH interrupt enable */
@ -3705,7 +3699,7 @@ static uint16_t usb_cstd_get_buf_size (uint16_t pipe)
/* Max Packet Size */
size = (uint16_t) (buffer & RX65N_USB_DCPMAXP_MXPS_MASK);
size = buffer & RX65N_USB_DCPMAXP_MXPS_MASK;
}
else
{
@ -3719,7 +3713,7 @@ static uint16_t usb_cstd_get_buf_size (uint16_t pipe)
/* Max Packet Size */
size = (uint16_t) (buffer & RX65N_USB_PIPEMAXP_MXPSMASK);
size = buffer & RX65N_USB_PIPEMAXP_MXPSMASK;
}
return size;
@ -3821,8 +3815,7 @@ static void usb_cstd_clr_pipe_cnfg (uint16_t pipe_no)
/* PIPE Configuration */
usb_cstd_chg_curpipe((uint16_t) USB_PIPE0,
(uint16_t) USB_CUSE, USB_FALSE);
usb_cstd_chg_curpipe(USB_PIPE0, USB_CUSE, USB_FALSE);
hw_usb_write_pipesel(pipe_no);
hw_usb_write_pipecfg(0);
@ -3887,7 +3880,7 @@ static void usb_cstd_set_nak (uint16_t pipe)
/* PIPE control reg read */
buf = hw_usb_read_pipectr(pipe);
if (0 == (uint16_t) (buf & RX65N_USB_DCPCTR_PID_MASK))
if (0 == (buf & RX65N_USB_DCPCTR_PID_MASK))
{
n = 0xfffeu;
}
@ -3919,10 +3912,10 @@ static uint16_t usb_cstd_is_set_frdy (uint16_t pipe, uint16_t fifosel,
{
buffer = hw_usb_read_fifoctr(fifosel);
if (RX65N_USB_FIFOCTR_FRDY == (uint16_t) (buffer &
if (RX65N_USB_FIFOCTR_FRDY == (buffer &
RX65N_USB_FIFOCTR_FRDY))
{
return (buffer);
return buffer;
}
buffer = hw_usb_read_syscfg();
@ -3930,7 +3923,7 @@ static uint16_t usb_cstd_is_set_frdy (uint16_t pipe, uint16_t fifosel,
nxsig_usleep(1);
}
return (RX65N_USB_FIFO_ERROR);
return RX65N_USB_FIFO_ERROR;
}
/****************************************************************************
@ -3967,8 +3960,7 @@ void usb_cstd_chg_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel)
buffer = hw_usb_read_fifosel(USB_CUSE);
}
while ((buffer & (uint16_t) (USB_ISEL | USB_CURPIPE)) !=
(uint16_t) (isel | pipe));
while ((buffer & (USB_ISEL | USB_CURPIPE)) != (isel | pipe));
break;
#ifdef DTC_DMA_ENABLED
@ -3992,7 +3984,7 @@ void usb_cstd_chg_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel)
{
buffer = hw_usb_read_fifosel(fifosel);
}
while ((uint16_t)(buffer & USB_CURPIPE) != pipe);
while ((buffer & USB_CURPIPE) != pipe);
break;
#endif /* ((USB_CFG_DTC==USB_CFG_ENABLE||(USB_CFG_DMA==USB_CFG_ENABLE))*/
@ -4070,7 +4062,7 @@ static uint16_t usb_cstd_get_pid (uint16_t pipe)
/* PIPE control reg read */
buf = hw_usb_read_pipectr(pipe);
return (uint16_t) (buf & RX65N_USB_DCPCTR_PID_MASK);
return buf & RX65N_USB_DCPCTR_PID_MASK;
}
/****************************************************************************
@ -4104,7 +4096,7 @@ static uint16_t usb_cstd_get_maxpacket_size (uint16_t pipe)
/* Max Packet Size */
size = (uint16_t) (buffer & RX65N_USB_DCPMAXP_MXPS_MASK);
size = (buffer & RX65N_USB_DCPMAXP_MXPS_MASK);
return size;
}
@ -4132,7 +4124,7 @@ static uint16_t usb_cstd_get_pipe_dir (uint16_t pipe)
/* Read Pipe direction */
buffer = hw_usb_read_pipecfg();
return (uint16_t) (buffer & RX65N_USB_PIPECFG_DIR);
return buffer & RX65N_USB_PIPECFG_DIR;
}
/****************************************************************************
@ -4216,7 +4208,7 @@ uint16_t usb_hstd_ctrl_write_start (uint8_t * buf_add, size_t buf_size)
/* PID=NAK & clear STALL */
usb_cstd_clr_stall((uint16_t) USB_PIPE0);
usb_cstd_clr_stall(USB_PIPE0);
/* DCP Configuration Register (0x5c) */
@ -4238,15 +4230,15 @@ uint16_t usb_hstd_ctrl_write_start (uint8_t * buf_add, size_t buf_size)
/* Enable Empty Interrupt */
hw_usb_set_bempenb((uint16_t) USB_PIPE0);
hw_usb_set_bempenb(USB_PIPE0);
/* Enable Not Ready Interrupt */
usb_cstd_nrdy_enable((uint16_t) USB_PIPE0);
usb_cstd_nrdy_enable(USB_PIPE0);
/* Set BUF */
usb_cstd_set_buf((uint16_t) USB_PIPE0);
usb_cstd_set_buf(USB_PIPE0);
break;
/* End of data write (not null) */
@ -4261,15 +4253,15 @@ uint16_t usb_hstd_ctrl_write_start (uint8_t * buf_add, size_t buf_size)
/* Enable Empty Interrupt */
hw_usb_set_bempenb((uint16_t) USB_PIPE0);
hw_usb_set_bempenb(USB_PIPE0);
/* Enable Not Ready Interrupt */
usb_cstd_nrdy_enable((uint16_t) USB_PIPE0);
usb_cstd_nrdy_enable(USB_PIPE0);
/* Set BUF */
usb_cstd_set_buf((uint16_t) USB_PIPE0);
usb_cstd_set_buf(USB_PIPE0);
break;
/* FIFO access error */
@ -4283,7 +4275,7 @@ uint16_t usb_hstd_ctrl_write_start (uint8_t * buf_add, size_t buf_size)
/* End or Err or Continue */
return (end_flag);
return end_flag;
}
/****************************************************************************
@ -4297,7 +4289,7 @@ void usb_hstd_ctrl_read_start (void)
{
/* PID=NAK & clear STALL */
usb_cstd_clr_stall((uint16_t) USB_PIPE0);
usb_cstd_clr_stall(USB_PIPE0);
/* DCP Configuration Register (0x5c) */
@ -4311,12 +4303,12 @@ void usb_hstd_ctrl_read_start (void)
/* Enable Ready Interrupt */
hw_usb_set_brdyenb((uint16_t) USB_PIPE0);
hw_usb_set_brdyenb(USB_PIPE0);
/* Enable Not Ready Interrupt */
usb_cstd_nrdy_enable((uint16_t) USB_PIPE0);
usb_cstd_set_buf((uint16_t) USB_PIPE0); /* Set BUF */
usb_cstd_nrdy_enable(USB_PIPE0);
usb_cstd_set_buf(USB_PIPE0); /* Set BUF */
}
/****************************************************************************
@ -4334,7 +4326,7 @@ void usb_host_read_pipe_start (uint16_t pipe)
/* PID=NAK & clear STALL */
usb_cstd_clr_stall((uint16_t) pipe);
usb_cstd_clr_stall(pipe);
config_reg = hw_usb_read_pipecfg();
@ -4357,15 +4349,15 @@ void usb_host_read_pipe_start (uint16_t pipe)
/* Enable Ready Interrupt */
hw_usb_set_brdyenb((uint16_t) pipe);
hw_usb_set_brdyenb(pipe);
/* Enable Not Ready Interrupt */
usb_cstd_nrdy_enable((uint16_t) pipe);
usb_cstd_nrdy_enable(pipe);
/* Set BUF */
usb_cstd_set_buf((uint16_t) pipe);
usb_cstd_set_buf(pipe);
}
/****************************************************************************
@ -4380,11 +4372,11 @@ void usb_hstd_status_start (void)
/* BEMP0 Disable */
hw_usb_clear_bempenb((uint16_t) USB_PIPE0);
hw_usb_clear_bempenb(USB_PIPE0);
/* BRDY0 Disable */
hw_usb_clear_brdyenb((uint16_t) USB_PIPE0);
hw_usb_clear_brdyenb(USB_PIPE0);
}
/****************************************************************************
@ -4399,24 +4391,22 @@ void usb_hstd_ctrl_end (uint16_t status)
{
/* Interrupt Disable */
hw_usb_clear_bempenb((uint16_t) USB_PIPE0); /* BEMP0 Disable */
hw_usb_clear_brdyenb((uint16_t) USB_PIPE0); /* BRDY0 Disable */
hw_usb_clear_nrdyenb((uint16_t) USB_PIPE0); /* NRDY0 Disable */
hw_usb_clear_bempenb(USB_PIPE0); /* BEMP0 Disable */
hw_usb_clear_brdyenb(USB_PIPE0); /* BRDY0 Disable */
hw_usb_clear_nrdyenb(USB_PIPE0); /* NRDY0 Disable */
usb_cstd_clr_stall((uint16_t) USB_PIPE0); /* PID=NAK & clear STALL */
usb_cstd_clr_stall(USB_PIPE0); /* PID=NAK & clear STALL */
hw_usb_set_mbw(USB_CUSE, USB0_CFIFO_MBW);
/* SUREQ=1, SQCLR=1, PID=NAK */
hw_usb_hwrite_dcpctr((uint16_t) (USB_SUREQCLR | USB_SQCLR));
hw_usb_hwrite_dcpctr((USB_SUREQCLR | USB_SQCLR);
/* CFIFO buffer clear */
usb_cstd_chg_curpipe((uint16_t) USB_PIPE0,
(uint16_t) USB_CUSE, USB_FALSE);
usb_cstd_chg_curpipe(USB_PIPE0, USB_CUSE, USB_FALSE);
hw_usb_set_bclr(USB_CUSE); /* Clear BVAL */
usb_cstd_chg_curpipe((uint16_t) USB_PIPE0,
(uint16_t) USB_CUSE, (uint16_t) USB_ISEL);
usb_cstd_chg_curpipe((USB_PIPE0, USB_CUSE, USB_ISEL);
hw_usb_set_bclr(USB_CUSE); /* Clear BVAL */
}
@ -4454,7 +4444,7 @@ void usb_hstd_brdy_pipe (void)
/* Control Read/Write End */
usb_hstd_ctrl_end((uint16_t) USB_CTRL_END);
usb_hstd_ctrl_end(USB_CTRL_END);
nxsem_post(&EDCTRL->wdhsem);
return; /* Nothing else to do here... as of now... */
@ -4495,14 +4485,14 @@ void usb_hstd_brdy_pipe (void)
/* Control Read/Write End */
usb_hstd_ctrl_end((uint16_t) USB_DATA_OVR);
usb_hstd_ctrl_end(USB_DATA_OVR);
break;
case USB_FIFOERROR: /* FIFO access error */
/* Control Read/Write End */
usb_hstd_ctrl_end((uint16_t) USB_DATA_ERR);
usb_hstd_ctrl_end(USB_DATA_ERR);
syslog(LOG_INFO, "ERROR");
break;
@ -4521,7 +4511,7 @@ void usb_hstd_brdy_pipe (void)
/* Control Read/Write End */
usb_hstd_ctrl_end((uint16_t) USB_CTRL_READING);
usb_hstd_ctrl_end(USB_CTRL_READING);
break;
case USB_READSHRT: /* End of data read */
@ -4544,14 +4534,14 @@ void usb_hstd_brdy_pipe (void)
/* Control Read/Write End */
usb_hstd_ctrl_end((uint16_t) USB_DATA_OVR);
usb_hstd_ctrl_end(USB_DATA_OVR);
break;
case USB_FIFOERROR: /* FIFO access error */
/* Control Read/Write End */
usb_hstd_ctrl_end((uint16_t) USB_DATA_ERR);
usb_hstd_ctrl_end(USB_DATA_ERR);
syslog(LOG_INFO, "ERROR");
break;
@ -4566,7 +4556,7 @@ void usb_hstd_brdy_pipe (void)
/* Control Read/Write End */
usb_hstd_ctrl_end((uint16_t) USB_CTRL_END);
usb_hstd_ctrl_end(USB_CTRL_END);
break;
default:
@ -4615,7 +4605,7 @@ void usb_hstd_nrdy_pipe (void)
/* Get Pipe PID from pipe number */
buffer = usb_cstd_get_pid((uint16_t) USB_PIPE0);
buffer = usb_cstd_get_pid(USB_PIPE0);
/* STALL ? */
@ -4624,13 +4614,13 @@ void usb_hstd_nrdy_pipe (void)
{
/* PIPE0 STALL call back */
usb_hstd_ctrl_end((uint16_t) USB_DATA_STALL);
usb_hstd_ctrl_end(USB_DATA_STALL);
}
else
{
/* Control Data Stage Device Ignore X 3 call back */
usb_hstd_ctrl_end((uint16_t) USB_DATA_ERR);
usb_hstd_ctrl_end(USB_DATA_ERR);
}
}
@ -4670,17 +4660,17 @@ void usb_hstd_bemp_pipe (void)
/* BEMP0 Disable */
hw_usb_clear_bempenb((uint16_t) USB_PIPE0);
hw_usb_clear_bempenb(USB_PIPE0);
/* BRDY0 Disable */
hw_usb_clear_brdyenb((uint16_t) USB_PIPE0);
hw_usb_clear_brdyenb(USB_PIPE0);
/* Call this to end the setup packet */
/* Control Read/Write End */
usb_hstd_ctrl_end((uint16_t) USB_CTRL_END);
usb_hstd_ctrl_end(USB_CTRL_END);
nxsem_post(&EDCTRL->wdhsem);
return; /* As of now, Nothing else to do here... */
@ -4688,7 +4678,7 @@ void usb_hstd_bemp_pipe (void)
/* Get Pipe PID from pipe number */
buffer = usb_cstd_get_pid((uint16_t) USB_PIPE0);
buffer = usb_cstd_get_pid(USB_PIPE0);
/* MAX packet size error ? */
@ -4696,7 +4686,7 @@ void usb_hstd_bemp_pipe (void)
{
/* PIPE0 STALL call back */
usb_hstd_ctrl_end((uint16_t) USB_DATA_STALL);
usb_hstd_ctrl_end(USB_DATA_STALL);
}
else
{
@ -4718,11 +4708,11 @@ void usb_hstd_bemp_pipe (void)
case USB_WRITESHRT:
hw_usb_set_bempenb((uint16_t) USB_PIPE0);
hw_usb_set_bempenb(USB_PIPE0);
/* Enable Not Ready Interrupt */
usb_cstd_nrdy_enable((uint16_t) USB_PIPE0);
usb_cstd_nrdy_enable(USB_PIPE0);
break;
/* End of data write (not null) */
@ -4737,11 +4727,11 @@ void usb_hstd_bemp_pipe (void)
/* Enable Empty Interrupt */
hw_usb_set_bempenb((uint16_t) USB_PIPE0);
hw_usb_set_bempenb(USB_PIPE0);
/* Enable Not Ready Interrupt */
usb_cstd_nrdy_enable((uint16_t) USB_PIPE0);
usb_cstd_nrdy_enable(USB_PIPE0);
break;
/* FIFO access error */
@ -4750,7 +4740,7 @@ void usb_hstd_bemp_pipe (void)
/* Control Read/Write End */
usb_hstd_ctrl_end((uint16_t) USB_DATA_ERR);
usb_hstd_ctrl_end(USB_DATA_ERR);
break;
default:
@ -4772,11 +4762,11 @@ void usb_hstd_bemp_pipe (void)
case USB_WRITESHRT:
hw_usb_set_bempenb((uint16_t) USB_PIPE0);
hw_usb_set_bempenb(USB_PIPE0);
/* Enable Not Ready Interrupt */
usb_cstd_nrdy_enable((uint16_t) USB_PIPE0);
usb_cstd_nrdy_enable(USB_PIPE0);
break;
/* End of data write (not null) */
@ -4785,7 +4775,7 @@ void usb_hstd_bemp_pipe (void)
/* Control Read/Write End */
usb_hstd_ctrl_end((uint16_t) USB_CTRL_WRITING);
usb_hstd_ctrl_end(USB_CTRL_WRITING);
break;
/* Continue of data write */
@ -4794,11 +4784,11 @@ void usb_hstd_bemp_pipe (void)
/* Enable Empty Interrupt */
hw_usb_set_bempenb((uint16_t) USB_PIPE0);
hw_usb_set_bempenb(USB_PIPE0);
/* Enable Not Ready Interrupt */
usb_cstd_nrdy_enable((uint16_t) USB_PIPE0);
usb_cstd_nrdy_enable(USB_PIPE0);
break;
/* FIFO access error */
@ -4807,7 +4797,7 @@ void usb_hstd_bemp_pipe (void)
/* Control Read/Write End */
usb_hstd_ctrl_end((uint16_t) USB_DATA_ERR);
usb_hstd_ctrl_end(USB_DATA_ERR);
break;
default:
@ -4825,7 +4815,7 @@ void usb_hstd_bemp_pipe (void)
/* Control Read/Write End */
usb_hstd_ctrl_end((uint16_t) USB_CTRL_END);
usb_hstd_ctrl_end(USB_CTRL_END);
break;
default:
@ -4969,7 +4959,7 @@ static void rx65n_usbhost_putreg(uint16_t val, uint32_t addr)
static inline uint16_t rx65n_usbhost_getle16(const uint8_t *val)
{
return (uint16_t)val[1] << 8 | (uint16_t)val[0];
return val[1] << 8 | val[0];
}
/****************************************************************************
@ -5649,9 +5639,9 @@ static inline int rx65n_usbhost_remisoced(struct rx65n_usbhost_s *priv,
****************************************************************************/
static int rx65n_usbhost_enqueuetd(struct rx65n_usbhost_s *priv,
struct rx65n_usbhost_ed_s *ed, uint32_t dirpid,
uint32_t toggle, volatile uint8_t *buffer,
size_t buflen)
struct rx65n_usbhost_ed_s *ed,
uint32_t dirpid, uint32_t toggle,
volatile uint8_t *buffer, size_t buflen)
{
struct rx65n_usbhost_gtd_s *td;
int ret = -ENOMEM;
@ -5748,7 +5738,8 @@ static int rx65n_usbhost_wdhwait(struct rx65n_usbhost_s *priv,
static int rx65n_usbhost_ctrltd(struct rx65n_usbhost_s *priv,
struct rx65n_usbhost_ed_s *ed,
uint32_t dirpid, uint8_t *buffer, size_t buflen)
uint32_t dirpid, uint8_t *buffer,
size_t buflen)
{
struct rx65n_usbhost_xfrinfo_s *xfrinfo;
uint32_t toggle;
@ -5876,11 +5867,11 @@ static int rx65n_usbhost_ctrltd(struct rx65n_usbhost_s *priv,
/* BEMP0 Disable */
hw_usb_clear_bempenb((uint16_t) USB_PIPE0);
hw_usb_clear_bempenb(USB_PIPE0);
/* BRDY0 Disable */
hw_usb_clear_brdyenb((uint16_t) USB_PIPE0);
hw_usb_clear_brdyenb(USB_PIPE0);
usb_hstd_ctrl_read_start();
@ -5913,11 +5904,11 @@ static int rx65n_usbhost_ctrltd(struct rx65n_usbhost_s *priv,
/* Disable Empty Interrupt */
hw_usb_clear_bempenb((uint16_t) USB_PIPE0);
hw_usb_clear_bempenb(USB_PIPE0);
/* Disable Not Ready Interrupt */
hw_usb_clear_nrdyenb((uint16_t) USB_PIPE0);
hw_usb_clear_nrdyenb(USB_PIPE0);
}
/* Check the TD completion status bits */
@ -7157,7 +7148,7 @@ static int rx65n_usbhost_ctrlin(struct usbhost_driver_s *drvr,
/* for read does the calculation correctly */
g_rx65n_edlist[kbd_interrupt_in_pipe].xfrinfo->xfrd = 0;
usb_cstd_set_buf((uint16_t) kbd_interrupt_in_pipe); /* Set BUF */
usb_cstd_set_buf(kbd_interrupt_in_pipe); /* Set BUF */
}
return ret;
@ -7250,8 +7241,7 @@ static int rx65n_usbhost_ctrlout(struct usbhost_driver_s *drvr,
static int rx65n_usbhost_transfer_common(struct rx65n_usbhost_s *priv,
struct rx65n_usbhost_ed_s *ed,
uint8_t *buffer,
size_t buflen)
uint8_t *buffer, size_t buflen)
{
struct rx65n_usbhost_xfrinfo_s *xfrinfo;
uint32_t dirpid;
@ -7341,8 +7331,8 @@ static int rx65n_usbhost_transfer_common(struct rx65n_usbhost_s *priv,
#if RX65N_USBHOST_IOBUFFERS > 0
static int rx65n_usbhost_dma_alloc(struct rx65n_usbhost_s *priv,
struct rx65n_usbhost_ed_s *ed,
uint8_t *userbuffer,
size_t buflen, uint8_t **alloc)
uint8_t *userbuffer, size_t buflen,
uint8_t **alloc)
{
syslog(LOG_INFO, "Debug : %s(): Line : %d\n", __func__, __LINE__);
@ -7378,8 +7368,8 @@ static int rx65n_usbhost_dma_alloc(struct rx65n_usbhost_s *priv,
static void rx65n_usbhost_dma_free(struct rx65n_usbhost_s *priv,
struct rx65n_usbhost_ed_s *ed,
uint8_t *userbuffer,
size_t buflen, uint8_t *newbuffer)
uint8_t *userbuffer, size_t buflen,
uint8_t *newbuffer)
{
syslog(LOG_INFO, "Debug : %s(): Line : %d\n", __func__, __LINE__);
}
@ -7425,7 +7415,8 @@ static void rx65n_usbhost_dma_free(struct rx65n_usbhost_s *priv,
****************************************************************************/
static ssize_t rx65n_usbhost_transfer(struct usbhost_driver_s *drvr,
usbhost_ep_t ep, uint8_t *buffer, size_t buflen)
usbhost_ep_t ep,
uint8_t *buffer, size_t buflen)
{
struct rx65n_usbhost_s *priv = (struct rx65n_usbhost_s *)drvr;
struct rx65n_usbhost_ed_s *ed = (struct rx65n_usbhost_ed_s *)ep;
@ -8014,7 +8005,7 @@ static int rx65n_usbhost_connect(FAR struct usbhost_driver_s *drvr,
syslog(LOG_INFO, "Enumeration failed with %d", ret);
}
hw_usb_write_dcpmxps((uint16_t) (USB_DEFPACKET + USB_DEVICE_1));
hw_usb_write_dcpmxps(USB_DEFPACKET + USB_DEVICE_1);
if (hport->speed == USB_SPEED_LOW)
{

4
arch/risc-v/src/bl602/bl602_netdev.c
View File

@ -1673,7 +1673,7 @@ bl602_net_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
}
#endif
priv->wlan = wifi_mgmr_sta_enable((void *)priv);
priv->wlan = wifi_mgmr_sta_enable(priv);
memcpy(priv->wlan->mac,
priv->net_dev.d_mac.ether.ether_addr_octet,
@ -1694,7 +1694,7 @@ bl602_net_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
}
#endif
priv->wlan = wifi_mgmr_ap_enable((void *)priv);
priv->wlan = wifi_mgmr_ap_enable(priv);
memcpy(priv->wlan->mac,
priv->net_dev.d_mac.ether.ether_addr_octet,
6);

5
arch/risc-v/src/bl602/bl602_spi.c
View File

@ -38,6 +38,7 @@
#include <nuttx/irq.h>
#include <nuttx/kmalloc.h>
#include <nuttx/mutex.h>
#include <nuttx/semaphore.h>
#include <nuttx/signal.h>
#include <nuttx/spi/spi.h>
@ -1480,7 +1481,7 @@ void bl602_spi_dma_init(struct spi_dev_s *dev)
/* Request a DMA channel for SPI peripheral */
priv->dma_rxchan = bl602_dma_channel_request(bl602_dma_rx_callback,
(void *)priv);
priv);
if (priv->dma_rxchan < 0)
{
spierr("Failed to allocate GDMA channel\n");
@ -1490,7 +1491,7 @@ void bl602_spi_dma_init(struct spi_dev_s *dev)
}
priv->dma_txchan = bl602_dma_channel_request(bl602_dma_tx_callback,
(void *)priv);
priv);
if (priv->dma_txchan < 0)
{
spierr("Failed to allocate GDMA channel\n");

8
arch/xtensa/src/esp32/esp32_i2s.c
View File

@ -411,7 +411,7 @@ static struct esp32_i2s_s esp32_i2s0_priv =
{
.dev =
{
.ops = &g_i2sops
.ops = &g_i2sops,
},
.lock = NXMUTEX_INITIALIZER,
.config = &esp32_i2s0_config,
@ -472,7 +472,7 @@ static struct esp32_i2s_s esp32_i2s1_priv =
{
.dev =
{
.ops = &g_i2sops
.ops = &g_i2sops,
},
.lock = NXMUTEX_INITIALIZER,
.config = &esp32_i2s1_config,
@ -614,8 +614,6 @@ static void i2s_buf_free(struct esp32_i2s_s *priv,
static int i2s_buf_initialize(struct esp32_i2s_s *priv)
{
int ret;
priv->tx.carry.bytes = 0;
priv->tx.carry.value = 0;
@ -1786,7 +1784,6 @@ static int esp32_i2s_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
bfcontainer->result = -EBUSY;
ret = i2s_txdma_setup(priv, bfcontainer);
if (ret != OK)
{
goto errout_with_buf;
@ -1797,7 +1794,6 @@ static int esp32_i2s_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
apb->nbytes - apb->curbyte);
nxmutex_unlock(&priv->lock);
return OK;
errout_with_buf:

2
arch/z80/src/ez80/ez80_i2c.c
View File

@ -92,7 +92,7 @@ static int ez80_i2c_transfer(FAR struct i2c_master_s *dev,
static bool g_initialized; /* true:I2C has been initialized */
static mutex_t g_i2clock = NXMUTEX_INITIALIZER; /* Serialize I2C transfers */
const struct i2c_ops_s g_ops =
static const struct i2c_ops_s g_ops =
{
ez80_i2c_transfer
};

3
boards/arm/stm32/mikroe-stm32f4/src/stm32_touchscreen.c
View File

@ -1347,8 +1347,7 @@ static int tc_ioctl(struct file *filep, int cmd, unsigned long arg)
* Name: tc_poll
****************************************************************************/
static int tc_poll(struct file *filep, struct pollfd *fds,
bool setup)
static int tc_poll(struct file *filep, struct pollfd *fds, bool setup)
{
struct inode *inode;
struct tc_dev_s *priv;

3
boards/mips/pic32mx/pic32mx7mmb/src/pic32_touchscreen.c
View File

@ -1224,8 +1224,7 @@ static int tc_ioctl(struct file *filep, int cmd, unsigned long arg)
* Name: tc_poll
****************************************************************************/
static int tc_poll(struct file *filep, struct pollfd *fds,
bool setup)
static int tc_poll(struct file *filep, struct pollfd *fds, bool setup)
{
struct inode *inode;
struct tc_dev_s *priv;

6
drivers/usbhost/usbhost_hidkbd.c
View File

@ -284,7 +284,7 @@ static inline int usbhost_tdfree(FAR struct usbhost_state_s *priv);
/* struct usbhost_registry_s methods */
static struct usbhost_class_s *usbhost_create(
static FAR struct usbhost_class_s *usbhost_create(
FAR struct usbhost_hubport_s *hport,
FAR const struct usbhost_id_s *id);
@ -355,7 +355,7 @@ static uint32_t g_devinuse;
static mutex_t g_lock = NXMUTEX_INITIALIZER;
static sem_t g_syncsem = SEM_INITIALIZER(0);
static struct usbhost_state_s *g_priv; /* Data passed to thread */
static FAR struct usbhost_state_s *g_priv;
/* The following tables map keyboard scan codes to printable ASIC
* characters. There is no support here for function keys or cursor
@ -1978,7 +1978,7 @@ static int usbhost_connect(FAR struct usbhost_class_s *usbclass,
*
****************************************************************************/
static int usbhost_disconnected(struct usbhost_class_s *usbclass)
static int usbhost_disconnected(FAR struct usbhost_class_s *usbclass)
{
FAR struct usbhost_state_s *priv = (FAR struct usbhost_state_s *)usbclass;

6
drivers/usbhost/usbhost_hidmouse.c
View File

@ -334,7 +334,7 @@ static inline int usbhost_tdfree(FAR struct usbhost_state_s *priv);
/* struct usbhost_registry_s methods */
static struct usbhost_class_s *
static FAR struct usbhost_class_s *
usbhost_create(FAR struct usbhost_hubport_s *hport,
FAR const struct usbhost_id_s *id);
@ -405,7 +405,7 @@ static uint32_t g_devinuse;
static mutex_t g_lock = NXMUTEX_INITIALIZER;
static sem_t g_syncsem = SEM_INITIALIZER(0);
static struct usbhost_state_s *g_priv; /* Data passed to thread */
static FAR struct usbhost_state_s *g_priv;
/****************************************************************************
* Private Functions
@ -1913,7 +1913,7 @@ static int usbhost_connect(FAR struct usbhost_class_s *usbclass,
*
****************************************************************************/
static int usbhost_disconnected(struct usbhost_class_s *usbclass)
static int usbhost_disconnected(FAR struct usbhost_class_s *usbclass)
{
FAR struct usbhost_state_s *priv = (FAR struct usbhost_state_s *)usbclass;
int i;

10
drivers/usbhost/usbhost_xboxcontroller.c
View File

@ -163,7 +163,7 @@ struct usbhost_state_s
mutex_t lock; /* Used to maintain mutual exclusive access */
struct work_s work; /* For interacting with the worker thread */
FAR uint8_t *tbuffer; /* The allocated transfer buffer */
FAR uint8_t obuffer[20]; /* The fixed output transfer buffer */
uint8_t obuffer[20]; /* The fixed output transfer buffer */
size_t tbuflen; /* Size of the allocated transfer buffer */
usbhost_ep_t epin; /* IN endpoint */
usbhost_ep_t epout; /* OUT endpoint */
@ -223,7 +223,7 @@ static inline int usbhost_tfree(FAR struct usbhost_state_s *priv);
/* struct usbhost_registry_s methods */
static struct usbhost_class_s *
static FAR struct usbhost_class_s *
usbhost_create(FAR struct usbhost_hubport_s *hport,
FAR const struct usbhost_id_s *id);
@ -310,7 +310,7 @@ static uint32_t g_devinuse;
static mutex_t g_lock = NXMUTEX_INITIALIZER;
static sem_t g_syncsem = SEM_INITIALIZER(0);
static struct usbhost_state_s *g_priv; /* Data passed to thread */
static FAR struct usbhost_state_s *g_priv;
/****************************************************************************
* Private Functions
@ -1651,7 +1651,7 @@ static int usbhost_connect(FAR struct usbhost_class_s *usbclass,
*
****************************************************************************/
static int usbhost_disconnected(struct usbhost_class_s *usbclass)
static int usbhost_disconnected(FAR struct usbhost_class_s *usbclass)
{
FAR struct usbhost_state_s *priv = (FAR struct usbhost_state_s *)usbclass;
int i;
@ -1903,7 +1903,7 @@ static ssize_t usbhost_read(FAR struct file *filep, FAR char *buffer,
{
FAR struct inode *inode;
FAR struct usbhost_state_s *priv;
FAR struct xbox_controller_buttonstate_s sample;
struct xbox_controller_buttonstate_s sample;
int ret;
DEBUGASSERT(filep && filep->f_inode && buffer);

2
include/nuttx/mutex.h
View File

@ -528,7 +528,7 @@ static inline int nxrmutex_breaklock(FAR rmutex_t *rmutex,
rmutex->count = 0;
rmutex->holder = NXRMUTEX_NO_HOLDER;
nxmutex_unlock(&rmutex->mutex);
ret = 0;
ret = OK;
}
return ret;

6
wireless/bluetooth/bt_ioctl.c
View File

@ -70,7 +70,7 @@ struct btnet_discoverstate_s
{
struct bt_gatt_discover_params_s bd_params;
struct bt_uuid_s bd_uuid; /* Discovery UUID */
sem_t bd_donesem; /* Manages exclusive access */
sem_t bd_donesem; /* Done notification */
};
/* GATT read state variables. */
@ -79,7 +79,7 @@ struct btnet_rdstate_s
{
struct btreq_s *rd_btreq;
uint8_t rd_result; /* The result of the read */
sem_t rd_donesem; /* Manages exclusive access */
sem_t rd_donesem; /* Done notification */
};
/* GATT write state variables. */
@ -88,7 +88,7 @@ struct btnet_wrstate_s
{
struct btreq_s *wr_btreq;
uint8_t wr_result; /* The result of the read */
sem_t wr_donesem; /* Manages exclusive access */
sem_t wr_donesem; /* Done notification */
};
/****************************************************************************