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Add UTMI register definitions

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This commit is contained in:
Gregory Nutt 2015-03-25 18:09:41 -06:00
parent 0253741178
commit a4b9e89e4e
2 changed files with 47 additions and 0 deletions
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25
arch/arm/src/samv7/chip/sam_usbhs.h
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@ -126,6 +126,10 @@
#define SAM_USBHS_SCR_OFFSET 0x0808 /* General Status Clear Register */
#define SAM_USBHS_SFR_OFFSET 0x080c /* General Status Set Register */
/* 0x0810-0x082c: Reserved */
/* UTMI Registers */
#define SAM_UTMI_OHCIICR_OFFSET 0x0010 /* OHCI Interrupt Configuration Register */
#define SAM_UTMI_CKTRIM_OFFSET 0x0030 /* UTMI Clock Trimming Register */
/* Register addresses ***************************************************************************************/
@ -191,6 +195,11 @@
#define SAM_USBHS_SCR (SAM_USBHS_BASE+SAM_USBHS_SCR_OFFSET)
#define SAM_USBHS_SFR (SAM_USBHS_BASE+SAM_USBHS_SFR_OFFSET)
/* UTMI Registers */
#define SAM_UTMI_OHCIICR (SAM_UTMI_BASE+SAM_UTMI_OHCIICR_OFFSET)
#define SAM_UTMI_CKTRIM (SAM_UTMI_BASE+SAM_UTMI_CKTRIM_OFFSET)
/* Register bit-field definitions ***************************************************************************/
/* USBHS Device Controller Register Bit Field Definitions */
@ -770,6 +779,22 @@
#define USBHS_SFR_RDERRIS (1 << 4) /* Bit 4: Remote Device Connection Error Interrupt Set */
/* UTMI Registers */
/* OHCI Interrupt Configuration Register */
#define UTMI_OHCIICR_RES0 (1 << 0) /* Bit 0: USB PORT0 Reset */
#define UTMI_OHCIICR_ARIE (1 << 4) /* Bit 4: OHCI Asynchronous Resume Interrupt Enable */
#define UTMI_OHCIICR_APPSTART (0 << 5) /* Bit 5: Reserved, must be zero */
#define UTMI_OHCIICR_UDPPUDIS (1 << 23) /* Bit 23: USB Device Pull-up Disable */
/* UTMI Clock Trimming Register */
#define UTMI_CKTRIM_FREQ_SHIFT (0) /* Bits 0-1: UTMI Reference Clock Frequency */
#define UTMI_CKTRIM_FREQ_MASK (3 << UTMI_CKTRIM_FREQ_SHIFT)
# define UTMI_CKTRIM_FREQ_XTAL12 (0 << UTMI_CKTRIM_FREQ_SHIFT) /* 12 MHz reference clock */
# define UTMI_CKTRIM_FREQ_XTAL16 (1 << UTMI_CKTRIM_FREQ_SHIFT) /* 16 MHz reference clock */
/************************************************************************************************************
* Public Types
************************************************************************************************************/

22
arch/arm/src/samv7/sam_usbdevhs.c
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@ -66,6 +66,7 @@
#include <nuttx/usb/usbdev_trace.h>
#include <arch/irq.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "up_internal.h"
@ -4324,10 +4325,31 @@ static void sam_hw_setup(struct sam_usbdev_s *priv)
regval |= USBHS_CTRL_UIMOD_DEVICE;
sam_putreg(regval, SAM_USBHS_CTRL);
/* UTMI configuration: Enable port0, select 12/16 MHz MAINOSC crystal source */
#if 0 /* REVISIT: Does this apply only to OHCI? */
sam_putreg(UTMI_OHCIICR_RES0, SAM_UTMI_OHCIICR);
#endif
#if BOARD_MAINOSC_FREQUENCY == 12000000
sam_putreg(UTMI_CKTRIM_FREQ_XTAL12, SAM_UTMI_CKTRIM);
#elif BOARD_MAINOSC_FREQUENCY == 12000000
sam_putreg(UTMI_CKTRIM_FREQ_XTAL16, SAM_UTMI_CKTRIM);
#else
# error ERROR: Unrecognized MAINSOSC frequency
#endif
/* UTMI parallel mode, High/Full/Low Speed */
#if 1 /* REVISIT */
/* Disable 48MHz USB FS Clock. It is not used in this configuration */
sam_putreg(PMC_USBCLK, SAM_PMC_SCDR);
#else
/* UTMI Full/Low Speed mode */
sam_putreg(PMC_USBCLK, SAM_PMC_SCER);
#endif
/* Select the UTMI PLL as the USB clock input with divider = 1. */