Add low-level console support for LM3S3918
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1770 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
460e952ac0
commit
a4fd9ce320
@ -46,7 +46,7 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
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up_undefinedinsn.c up_usestack.c
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CHIP_ASRCS =
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CHIP_CSRCS = lm3s_start.c lm3s_syscontrol.c lm3s_irq.c
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CHIP_CSRCS = lm3s_start.c lm3s_syscontrol.c lm3s_irq.c lm3s_lowputc.c
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ifdef CONFIG_NET
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CHIP_CSRCS += lm3s_ethernet.c
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@ -354,14 +354,20 @@
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/* Bit-encoded input to lm3s_configgpio() *******************************************/
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#define GPIO_FUNC_SHIFT 30 /* Bit 31-30: GPIO function */
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#define GPIO_FUNC_MASK (3 << GPIO_FUNC_SHIFT)
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#define GPIO_FUNC_INPUT (0 << GPIO_FUNC_SHIFT) /* Normal GPIO input */
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#define GPIO_FUNC_OUTPUT (1 << GPIO_FUNC_SHIFT) /* Normal GPIO output */
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#define GPIO_FUNC_PERIPHERAL (2 << GPIO_FUNC_SHIFT) /* Peripheral function */
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#define GPIO_FUNC_INTERRUPT (3 << GPIO_FUNC_SHIFT) /* Interrupt function */
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#define GPIO_FUNC_SHIFT 29 /* Bit 31-29: GPIO function */
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#define GPIO_FUNC_MASK (7 << GPIO_FUNC_SHIFT) /* (See table 9-1 in data sheet) */
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#define GPIO_FUNC_INPUT (0 << GPIO_FUNC_SHIFT) /* Digital GPIO input */
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#define GPIO_FUNC_OUTPUT (1 << GPIO_FUNC_SHIFT) /* Digital GPIO output */
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#define GPIO_FUNC_ODINPUT (2 << GPIO_FUNC_SHIFT) /* Open-drain GPIO input */
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#define GPIO_FUNC_ODOUTPUT (3 << GPIO_FUNC_SHIFT) /* Open-drain GPIO output */
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#define GPIO_FUNC_PFODIO (4 << GPIO_FUNC_SHIFT) /* Open-drain input/output (I2C) */
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#define GPIO_FUNC_PFINPUT (5 << GPIO_FUNC_SHIFT) /* Digital input (Timer, CCP) */
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#define GPIO_FUNC_PFOUTPUT (5 << GPIO_FUNC_SHIFT) /* Digital output (Timer, PWM, Comparator) */
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#define GPIO_FUNC_PFIO (5 << GPIO_FUNC_SHIFT) /* Digital input/output (SSI, UART) */
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#define GPIO_FUNC_ANINPUT (6 << GPIO_FUNC_SHIFT) /* Analog input (Comparator) */
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#define GPIO_FUNC_INTERRUPT (7 << GPIO_FUNC_SHIFT) /* Interrupt function */
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#define GPIO_INT_SHIFT 27 /* Bits 29-27: Interrupt type */
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#define GPIO_INT_SHIFT 26 /* Bits 28-26: Interrupt type */
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#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT)
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#define GPIO_INT_FALLINGEDGE (0 << GPIO_INT_SHIFT) /* Interrupt on falling edge */
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#define GPIO_INT_RISINGEDGE (1 << GPIO_INT_SHIFT) /* Interrupt on rising edge */
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@ -369,22 +375,22 @@
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#define GPIO_INT_LOWLEVEL (3 << GPIO_INT_SHIFT) /* Interrupt on low level */
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#define GPIO_INT_HIGHLEVEL (4 << GPIO_INT_SHIFT) /* Interrupt on high level */
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#define GPIO_STRENGTH_SHIFT 25 /* Bits 26-25: Pad drive strength */
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#define GPIO_STRENGTH_SHIFT 24 /* Bits 25-24: Pad drive strength */
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#define GPIO_STRENGTH_MASK (3 << GPIO_STRENGTH_SHIFT)
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#define GPIO_STRENGTH_2MA (0 << GPIO_STRENGTH_SHIFT) /* 2mA pad drive strength */
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#define GPIO_STRENGTH_4MA (1 << GPIO_STRENGTH_SHIFT) /* 4mA pad drive strength */
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#define GPIO_STRENGTH_8MA (2 << GPIO_STRENGTH_SHIFT) /* 8mA pad drive strength */
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#define GPIO_STRENGTH_8MASC (3 << GPIO_STRENGTH_SHIFT) /* 8mA Pad drive with slew rate control */
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#define GPIO_PADTYPE_SHIFT 22 /* Bits 22-24: Pad type */
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#define GPIO_PADTYPE_MASK (0 << GPIO_PADTYPE_SHIFT)
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#define GPIO_PADTYPE_STD (1 << GPIO_PADTYPE_SHIFT) /* Push-pull */
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#define GPIO_PADTYPE_STDWPU (2 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-up */
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#define GPIO_PADTYPE_STDWPD (3 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-down */
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#define GPIO_PADTYPE_OD (4 << GPIO_PADTYPE_SHIFT) /* Open-drain */
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#define GPIO_PADTYPE_ODWPU (5 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-up */
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#define GPIO_PADTYPE_ODWPD (6 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-down */
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#define GPIO_PADTYPE_ANALOG (7 << GPIO_PADTYPE_SHIFT) /* Analog comparator */
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#define GPIO_PADTYPE_SHIFT 21 /* Bits 21-23: Pad type */
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#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT)
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#define GPIO_PADTYPE_STD (0 << GPIO_PADTYPE_SHIFT) /* Push-pull */
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#define GPIO_PADTYPE_STDWPU (1 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-up */
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#define GPIO_PADTYPE_STDWPD (2 << GPIO_PADTYPE_SHIFT) /* Push-pull with weak pull-down */
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#define GPIO_PADTYPE_OD (3 << GPIO_PADTYPE_SHIFT) /* Open-drain */
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#define GPIO_PADTYPE_ODWPU (4 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-up */
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#define GPIO_PADTYPE_ODWPD (5 << GPIO_PADTYPE_SHIFT) /* Open-drain with weak pull-down */
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#define GPIO_PADTYPE_ANALOG (6 << GPIO_PADTYPE_SHIFT) /* Analog comparator */
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#define GPIO_VALUE_SHIFT 6 /* Bit 6: If output, inital value of output */
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#define GPIO_VALUE_MASK (1 << GPIO_VALUE_SHIFT)
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@ -403,7 +409,49 @@
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#define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
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#define GPIO_NUMBER_SHIFT 0 /* Bits 0-2: GPIO number: 0-7 */
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#define GPIO_NUMBER_MASK (0x07 << GPIO_NUMBER_SHIFT)
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#define GPIO_NUMBER_MASK (7 << GPIO_NUMBER_SHIFT)
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/* The following lists the input value to lm3s_configgpio to setup the alternate,
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* hardware function for each pin.
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*/
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#define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */
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#define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
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#define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */
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#define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */
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#define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */
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#define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
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#define GPIO_PWM1_CCP (GPIO_FUNC_PFIO | GPIO_PORTA | 6) /* PA6: Capture/Compare/PWM1 (CCP1) */
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#define GPIO_I2C1_SDA (GPIO_FUNC_PFODIO | GPIO_PORTA | 7) /* PA7: I2C1 data (I2C1SDA) */
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#define GPIO_PWM0_CCP (GPIO_FUNC_PFIO | GPIO_PORTB | 0) /* PB0: Capture/Compare/PWM0 (CCP0) */
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#define GPIO_PWM2_CCP (GPIO_FUNC_PFIO | GPIO_PORTB | 1) /* PB1: Capture/Compare/PWM2 (CCP2) */
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#define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
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#define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */
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#define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */
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#define GPIO_CMP1_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 1 negative input (C1-) */
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#define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */
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#define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */
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#define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */
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#define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */
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#define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */
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#define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */
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#define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */
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#define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
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#define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
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#define GPIO_PWM5_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 4) /* PC4: Capture/Compare/PWM5 (CCP5) */
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#define GPIO_CMP1_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 1 positive input (C1+) */
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#define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 5) /* PC5: Analog comparator 0 output (C0o) */
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#define GPIO_PWM3_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 6) /* PC6: Capture/Compare/PWM3 (CCP3) */
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#define GPIO_PWM4_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 7) /* PC7: Capture/Compare/PWM4 (CCP4) */
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#define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */
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#define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
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#define GPIO_SSI1_CLK (GPIO_FUNC_PFIO1 | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */
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#define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */
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#define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */
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#define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
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#define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
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#define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
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#define GPIO_I2C1_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 0) /* PG0: I2C1 clock (I2C1SCL) */
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/************************************************************************************
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* Public Types
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265
arch/arm/src/lm3s/lm3s_lowputc.c
Normal file
265
arch/arm/src/lm3s/lm3s_lowputc.c
Normal file
@ -0,0 +1,265 @@
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/**************************************************************************
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* arch/arm/src/lm3s/lm3s_lowputc.c
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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**************************************************************************/
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/**************************************************************************
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* Included Files
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**************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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/**************************************************************************
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* Private Definitions
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**************************************************************************/
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/* Configuration **********************************************************/
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/* Is there a serial console? */
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#if defined(CONFIG_UART0_SERIAL_CONSOLE) && !defined(CONFIG_UART0_DISABLE)
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# undef CONFIG_UART1_SERIAL_CONSOLE
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# define HAVE_CONSOLE 1
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#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && !defined(CONFIG_UART1_DISABLE)
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# undef CONFIG_UART0_SERIAL_CONSOLE
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# define HAVE_CONSOLE 1
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#else
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# undef CONFIG_UART0_SERIAL_CONSOLE
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# undef CONFIG_UART1_SERIAL_CONSOLE
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# undef HAVE_CONSOLE
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#endif
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/* Select UART parameters for the selected console */
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#if defined(CONFIG_UART0_SERIAL_CONSOLE)
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# define LM3S_CONSOLE_BASE LM3S_UART0_BASE
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# define LM3S_CONSOLE_BAUD CONFIG_UART0_BAUD
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# define LM3S_CONSOLE_BITS CONFIG_UART0_BITS
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# define LM3S_CONSOLE_PARITY CONFIG_UART0_PARITY
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# define LM3S_CONSOLE_2STOP CONFIG_UART0_2STOP
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#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
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# define LM3S_CONSOLE_BASE LM3S_UART1_BASE
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# define LM3S_CONSOLE_BAUD CONFIG_UART1_BAUD
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# define LM3S_CONSOLE_BITS CONFIG_UART1_BITS
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# define LM3S_CONSOLE_PARITY CONFIG_UART1_PARITY
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# define LM3S_CONSOLE_2STOP CONFIG_UART1_2STOP
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#else
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# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
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#endif
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/* Get LCRH settings */
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#if LM3S_CONSOLE_BITS == 5
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# define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS
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#elif LM3S_CONSOLE_BITS == 6
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# define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS
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#elif LM3S_CONSOLE_BITS == 7
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# define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS
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#elif LM3S_CONSOLE_BITS == 8
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# define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS
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#else
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# error "Number of bits not supported"
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#endif
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#if LM3S_CONSOLE_PARITY == 0
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# define UART_LCRH_PARITY (0)
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#elif LM3S_CONSOLE_PARITY == 1
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# define UART_LCRH_PARITY UART_LCRH_PEN
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#elif LM3S_CONSOLE_PARITY == 2
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# define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS)
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#else
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# error "Invalid parity selection"
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#endif
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#if LM3S_CONSOLE_2STOP != 0
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# define UART_LCRH_NSTOP UART_LCRH_STP2
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#else
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# define UART_LCRH_NSTOP (0)
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#endif
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#define UART_LCRH_VALUE (UART_LCRH_NBITS|UART_LCRH_PARITY|UART_LCRH_NSTOP|UART_LCRH_FEN)
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/* Calculate BAUD rate from PCLK1:
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*
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* "The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit
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* fractional part. The number formed by these two values is used by the baud-rate generator
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* to determine the bit period. Having a fractional baud-rate divider allows the UART to
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* generate all the standard baud rates.
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*
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* "The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD)
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* register ... and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate
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* Divisor (UARTFBRD) register... The baud-rate divisor (BRD) has the following relationship
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* to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional
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* part, separated by a decimal place.):
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*
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* "BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
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*
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* "where UARTSysClk is the system clock connected to the UART. The 6-bit fractional number
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* (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated
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* by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5
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* to account for rounding errors:
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*
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* "UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
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*
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* "The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred
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* to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is
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* used for error detection during receive operations.
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*
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* "Along with the UART Line Control, High Byte (UARTLCRH) register ..., the UARTIBRD and
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* UARTFBRD registers form an internal 30-bit register. This internal register is only
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* updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate
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* divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..."
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*/
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#define LM3S_BRDDEN (16 * LM3S_CONSOLE_BAUD)
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#define LM3S_BRDI (SYSCLK_FREQUENCY / LM3S_BRDDEN)
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#define LM3S_REMAINDER (SYSCLK_FREQUENCY - LM3S_BRDDEN * LM3S_BRDI)
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#define LM3S_DIVFRAC ((LM3S_REMAINDER * 64 + (LM3S_BRDDEN/2)) / LM3S_BRDDEN)
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/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 20,000,000:
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*
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* LM3S_BRDDEN = (16 * 115,200) = 1,843,200
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* LM3S_BRDI = 20,000,000 / 1,843,200 = 10
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* LM3S_REMAINDER = 20,000,000 - 1,843,200 * 10 = 1,568,000
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* LM3S_DIVFRAC = (1,568,000 * 64 + 921,600) / 1,843,200 = 54
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*
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* Which should yied BAUD = 20,000,000 / (16 * (10 + 54/64)) = 115273.8
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*/
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/**************************************************************************
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* Private Types
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**************************************************************************/
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/**************************************************************************
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* Private Function Prototypes
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**************************************************************************/
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/**************************************************************************
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* Global Variables
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**************************************************************************/
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/**************************************************************************
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* Private Variables
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**************************************************************************/
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/**************************************************************************
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* Private Functions
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**************************************************************************/
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/**************************************************************************
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* Public Functions
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**************************************************************************/
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/**************************************************************************
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* Name: up_lowputc
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*
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* Description:
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* Output one byte on the serial console
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*
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**************************************************************************/
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void up_lowputc(char ch)
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{
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#ifdef HAVE_CONSOLE
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/* Wait until the TX FIFO is not full */
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while ((getreg32(LM3S_CONSOLE_BASE+LM3S_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
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/* Then send the character */
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putreg32((uint32)ch, LM3S_CONSOLE_BASE+LM3S_UART_DR_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
* Name: up_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* This performs basic initialization of the UART used for the serial
|
||||
* console. Its purpose is to get the console output availabe as soon
|
||||
* as possible.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
void up_lowsetup(void)
|
||||
{
|
||||
#ifdef HAVE_CONSOLE
|
||||
uint16 ctl;
|
||||
|
||||
/* Enable the selected console device */
|
||||
/* 1. Disable the UART by clearing the UARTEN bit in the UART CTL register */
|
||||
|
||||
ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
|
||||
ctl &= ~UART_CTL_UARTEN;
|
||||
putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
|
||||
|
||||
/* 2. Write the integer portion of the BRD to the UART IBRD register */
|
||||
|
||||
putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET);
|
||||
|
||||
/* 3. Write the fractional portion of the BRD to the UART FBRD register */
|
||||
|
||||
putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET);
|
||||
|
||||
/* 4. Write the desired serial parameters to the UART LCRH register */
|
||||
|
||||
putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET);
|
||||
|
||||
/* 5. Enable the UART by setting the UARTEN bit in the UART CTL register */
|
||||
|
||||
ctl |= UART_CTL_UARTEN;
|
||||
putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
|
||||
#endif
|
||||
|
||||
/* Configure GPIO pins to enable all UARTs in the configuration
|
||||
* (the serial driver later depends on this configuration)
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_UART0_DISABLE
|
||||
lm3x_configgpio(GPIO_UART0_RX);
|
||||
lm3x_configgpio(GPIO_UART0_TX);
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_UART1_DISABLE
|
||||
lm3x_configgpio(GPIO_UART1_RX);
|
||||
lm3x_configgpio(GPIO_UART1_TX);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@ -86,7 +86,7 @@
|
||||
# define STR71X_UART0_GPIO0_PC2BITS (0)
|
||||
#endif
|
||||
|
||||
#if CONFIG_STR71X_UART0
|
||||
#if CONFIG_STR71X_UART1
|
||||
# define STR71X_UART1_GPIO0_MASK (0x0c00) /* P0,10->U1.RX, P0.11->U1.TX */
|
||||
# define STR71X_UART1_GPIO0_PC0BITS (0x0c00)
|
||||
# define STR71X_UART1_GPIO0_PC1BITS (0x0800)
|
||||
@ -98,7 +98,7 @@
|
||||
# define STR71X_UART1_GPIO0_PC2BITS (0)
|
||||
#endif
|
||||
|
||||
#if CONFIG_STR71X_UART0
|
||||
#if CONFIG_STR71X_UART2
|
||||
# define STR71X_UART2_GPIO0_MASK (0x6000) /* P0.13->U2.RX, P0.14>U2.TX */
|
||||
# define STR71X_UART2_GPIO0_PC0BITS (0x6000)
|
||||
# define STR71X_UART2_GPIO0_PC1BITS (0x4000)
|
||||
@ -110,7 +110,7 @@
|
||||
# define STR71X_UART2_GPIO0_PC2BITS (0)
|
||||
#endif
|
||||
|
||||
#if CONFIG_STR71X_UART0
|
||||
#if CONFIG_STR71X_UART3
|
||||
# define STR71X_UART3_GPIO0_MASK (0x0003) /* P0.0->U3.TX, P0.1->U3.RX */
|
||||
# define STR71X_UART3_GPIO0_PC0BITS (0x0003)
|
||||
# define STR71X_UART3_GPIO0_PC1BITS (0x0001)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user