From a5024a707d3bd5109eb29750ffbe67ec3b14b66f Mon Sep 17 00:00:00 2001 From: Gustavo Henrique Nihei Date: Thu, 24 Feb 2022 12:27:49 -0300 Subject: [PATCH] xtensa/esp32s3: Use the running CPU ID for enabling internal interrupts Signed-off-by: Gustavo Henrique Nihei --- arch/xtensa/src/esp32s3/esp32s3_irq.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/xtensa/src/esp32s3/esp32s3_irq.c b/arch/xtensa/src/esp32s3/esp32s3_irq.c index 53e2c18ea7..7b45bf771c 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_irq.c +++ b/arch/xtensa/src/esp32s3/esp32s3_irq.c @@ -414,20 +414,38 @@ void up_disable_irq(int irq) void up_enable_irq(int irq) { - int cpu = IRQ_GETCPU(g_irqmap[irq]); int cpuint = IRQ_GETCPUINT(g_irqmap[irq]); DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX); - DEBUGASSERT(cpu == 0); if (irq < XTENSA_NIRQ_INTERNAL) { + /* For internal interrupts, use the current CPU. We can't enable other + * CPUs' internal interrupts. + * The CPU interrupt can still be taken from the map as internal + * interrupts have the same number for all CPUs. In this case then + * we are just overwriting the cpu part of the map. + */ + + int cpu = up_cpu_index(); + /* Enable the CPU interrupt now for internal CPU. */ - xtensa_enable_cpuint(&g_intenable[cpu], 1ul << cpuint); + xtensa_enable_cpuint(&g_intenable[cpu], (1ul << cpuint)); } else { + /* Retrieve the CPU that enabled this interrupt from the IRQ map. + * + * For peripheral interrupts we rely on the interrupt matrix to manage + * interrupts. The interrupt matrix registers are available for both + * CPUs. + */ + + int cpu = IRQ_GETCPU(g_irqmap[irq]); + + DEBUGASSERT(cpu == 0); + /* For peripheral interrupts, attach the interrupt to the peripheral; * the CPU interrupt was already enabled when allocated. */