Add special register definitions needed for z80181 and z80182
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5434 42af7a65-404d-4744-a932-0658087f49c3
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@ -93,6 +93,9 @@
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defined(CONFIG_ARCH_CHIP_Z8018006VEG) /* 68-pin PLCC */
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# undef HAVE_Z8S180 /* Not Z8S180 (5V) or Z8L180 (3.3V) core */
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# define HAVE_Z8X180 1 /* Z8x180 registers */
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# undef HAVE_Z8X181 /* Z8x181 registers */
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# undef HAVE_Z8X182 /* Z8x182 registers */
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# define HAVE ROM 0 /* No on-chip ROM */
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# define HAVE_SERIALIO 1 /* Have clocked serial I/O */
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# undef HAVE_WDT /* No Watchdog timer */
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@ -117,6 +120,9 @@
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defined(CONFIG_ARCH_CHIP_Z8018006FSG) /* 80-pin QFP (11 pins N/C) 6MHz 5V */
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# undef HAVE_Z8S180 /* Not Z8S180 (5V) or Z8L180 (3.3V) core */
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# define HAVE_Z8X180 1 /* Z8x180 registers */
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# undef HAVE_Z8X181 /* Z8x181 registers */
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# undef HAVE_Z8X182 /* Z8x182 registers */
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# define HAVE ROM 0 /* No on-chip ROM */
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# undef HAVE_SERIALIO /* No clocked serial I/O ? */
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# undef HAVE_WDT /* No Watchdog timer */
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@ -137,6 +143,9 @@
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defined(CONFIG_ARCH_CHIP_Z8018008PEG)
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# undef HAVE_Z8S180 /* Not Z8S180 (5V) or Z8L180 (3.3V) core */
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# define HAVE_Z8X180 1 /* Z8x180 registers */
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# undef HAVE_Z8X181 /* Z8x181 registers */
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# undef HAVE_Z8X182 /* Z8x182 registers */
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# define HAVE ROM 0 /* No on-chip ROM */
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# define HAVE_SERIALIO 1 /* Have clocked serial I/O */
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# undef HAVE_WDT /* No Watchdog timer */
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@ -175,6 +184,9 @@
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#elif defined(CONFIG_ARCH_CHIP_Z8018110FEG) /* 100-pin QFP */
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# undef HAVE_Z8S180 /* Not Z8S180 (5V) or Z8L180 (3.3V) core */
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# undef HAVE_Z8X180 /* Z8x180 registers */
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# define HAVE_Z8X181 1 /* Z8x181 registers */
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# undef HAVE_Z8X182 /* Z8x182 registers */
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# define HAVE ROM 0 /* No on-chip ROM */
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# define HAVE_SERIALIO 1 /* Have clocked serial I/O */
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# undef HAVE_WDT /* No Watchdog timer */
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@ -220,6 +232,9 @@
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defined(CONFIG_ARCH_CHIP_Z8018233ASG) /* 100-pin LQFP 33MHz 5V */
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# undef HAVE_Z8S180 /* Not Z8S180 (5V) or Z8L180 (3.3V) core */
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# undef HAVE_Z8X180 /* Z8x180 registers */
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# undef HAVE_Z8X181 /* Z8x181 registers */
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# define HAVE_Z8X182 1 /* Z8x182 registers */
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# define HAVE ROM 0 /* No on-chip ROM */
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# define HAVE_SERIALIO 1 /* Have clocked serial I/O */
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# undef HAVE_WDT /* No Watchdog timer */
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@ -304,6 +319,9 @@
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defined(CONFIG_ARCH_CHIP_Z8L18020PSG)
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# define HAVE_Z8S180 1 /* Uses Z8S180 (5V) or Z8L180 (3.3V) core */
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# define HAVE_Z8X180 1 /* Z8x180 registers */
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# undef HAVE_Z8X181 /* Z8x181 registers */
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# undef HAVE_Z8X182 /* Z8x182 registers */
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# define HAVE ROM 0 /* No on-chip ROM */
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# define HAVE_SERIALIO 1 /* Have clocked serial I/O */
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# undef HAVE_WDT /* No Watchdog timer */
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@ -348,6 +366,9 @@
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defined(CONFIG_ARCH_CHIP_Z8L18220AEG)
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# define HAVE_Z8S180 1 /* Uses Z8S180 (5V) or Z8L180 (3.3V) core */
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# undef HAVE_Z8X180 /* Z8x180 registers */
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# undef HAVE_Z8X181 /* Z8x181 registers */
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# define HAVE_Z8X182 1 /* Z8x182 registers */
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# define HAVE ROM 0 /* No on-chip ROM */
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# define HAVE_SERIALIO 1 /* Have clocked serial I/O */
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# undef HAVE_WDT /* No Watchdog timer */
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@ -405,6 +426,9 @@
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defined(CONFIG_ARCH_CHIP_Z8S18010FEG)
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# define HAVE_Z8S180 1 /* Uses Z8S180 (5V) or Z8L180 (3.3V) core */
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# define HAVE_Z8X180 1 /* Z8x180 registers */
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# undef HAVE_Z8X181 /* Z8x181 registers */
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# undef HAVE_Z8X182 /* Z8x182 registers */
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# define HAVE ROM 0 /* No on-chip ROM */
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# define HAVE_SERIALIO 1 /* Have clocked serial I/O */
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# undef HAVE_WDT /* No Watchdog timer */
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@ -1,4 +1,4 @@
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/****************************************************************************
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/************************************************************************************
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* arch/z80/src/z180/z180_iomap.h
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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@ -31,101 +31,260 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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************************************************************************************/
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#ifndef __ARCH_Z80_SRC_Z180_Z180_IOMAP_H
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#define __ARCH_Z80_SRC_Z180_Z180_IOMAP_H
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/****************************************************************************
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/************************************************************************************
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* Included Files
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****************************************************************************/
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************************************************************************************/
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#include <arch/z180/chip.h>
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/****************************************************************************
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/************************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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************************************************************************************/
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/* Configuration ********************************************************************/
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/* Z180 Register Bit addresses **********************************************/
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/* These registers may be relocated to multiples of 0x40 by setting the IO Control
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* Register (ICR). Relocatable to 0x40-0x7f, or 0x80-0xbf. The configuration setting,
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* CONFIG_Z180_SFROFFSET, indicates that offset (but is not fully supported yet!)
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*/
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#define Z180_ASCI0_CNTLA 0x00 /* ASCI Control Register A Ch 0 */
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#define Z180_ASCI1_CNTLA 0x01 /* ASCI Control Register A Ch 1 */
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#define Z180_ASCI0_CNTLB 0x02 /* ASCI Control Register B Ch 0 */
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#define Z180_ASCI1_CNTLB 0x03 /* ASCI Control Register B Ch 1 */
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#define Z180_ASCI0_STAT 0x04 /* ASCI Status Register Ch 0 */
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#define Z180_ASCI1_STAT 0x05 /* ASCI Status Register Ch 1 */
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#define Z180_ASCI0_TDR 0x06 /* ASCI Transmit Data Register Ch 0 */
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#define Z180_ASCI1_TDR 0x07 /* ASCI Transmit Data Register Ch 1 */
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#define Z180_ASCI0_RDR 0x08 /* ASCI Receive Data Register Ch 0 */
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#define Z180_ASCI1_RDR 0x09 /* ASCI Receive Data Register Ch 1 */
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#define Z180_CSIO_CNTR 0x0a /* CSI/O Control Register */
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#define Z180_CSIO_TRD 0x0b /* Transmit/Receive Data Register */
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#define Z180_TMR0_DRL 0x0c /* Timer Data Register Ch 0 L */
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#define Z180_TMR0_DRH 0x0d /* Data Register Ch 0 H */
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#define Z180_TMR0_RLDRL 0x0e /* Reload Register Ch 0 L */
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#define Z180_TMR0_RLDRH 0x0f /* Reload Register Ch 0 H */
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#define Z180_TMR_TCR 0x10 /* Timer Control Register */
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#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
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# define Z180_ASCI0_ASEXT 0x12 /* ASCI Extension Control Register */
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# define Z180_ASCI1_ASEXT 0x13 /* ASCI Extension Control Register */
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#ifdef CONFIG_Z180_SFROFFSET
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# define SFR_OFFSET CONFIG_Z180_SFROFFSET
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#else
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# define SFR_OFFSET 0
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#endif
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#define Z180_TMR1_DRL 0x14 /* Data Register Ch 1 L */
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#define Z180_TMR1_DRH 0x15 /* Data Register Ch 1 H */
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#define Z180_TMR1_RLDRL 0x16 /* Reload Register Ch 1 L */
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#define Z180_TMR1_RLDRH 0x17 /* Reload Register Ch 1 H */
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/* Z180 Register Bit addresses ******************************************************/
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/* ASCI Registers */
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#define Z180_FRC 0x18 /* Free Running Counter */
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#define Z180_ASCI0_CNTLA (SFR_OFFSET+0x00) /* ASCI Control Register A Ch 0 */
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#define Z180_ASCI1_CNTLA (SFR_OFFSET+0x01) /* ASCI Control Register A Ch 1 */
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#define Z180_ASCI0_CNTLB (SFR_OFFSET+0x02) /* ASCI Control Register B Ch 0 */
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#define Z180_ASCI1_CNTLB (SFR_OFFSET+0x03) /* ASCI Control Register B Ch 1 */
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#define Z180_ASCI0_STAT (SFR_OFFSET+0x04) /* ASCI Status Register Ch 0 */
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#define Z180_ASCI1_STAT (SFR_OFFSET+0x05) /* ASCI Status Register Ch 1 */
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#define Z180_ASCI0_TDR (SFR_OFFSET+0x06) /* ASCI Transmit Data Register Ch 0 */
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#define Z180_ASCI1_TDR (SFR_OFFSET+0x07) /* ASCI Transmit Data Register Ch 1 */
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#define Z180_ASCI0_RDR (SFR_OFFSET+0x08) /* ASCI Receive Data Register Ch 0 */
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#define Z180_ASCI1_RDR (SFR_OFFSET+0x09) /* ASCI Receive Data Register Ch 1 */
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#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
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# define Z180_ASCI0_ASTCL 0x1a /* ASCI Time Constant Low */
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# define Z180_ASCI0_ASTCH 0x1b /* ASCI Time Constant High */
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# define Z180_ASCI1_ASTCL 0x1c /* ASCI Time Constant Low */
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# define Z180_ASCI1_ASTCH 0x1d /* ASCI Time Constant High */
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# define Z180_CMR 0x1e /* Clock Multiplier Register */
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# define Z180_CCR 0x1f /* CPU Control Register */
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# define Z180_ASCI0_ASEXT (SFR_OFFSET+0x12) /* ASCI Extension Control Register */
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# define Z180_ASCI1_ASEXT (SFR_OFFSET+0x13) /* ASCI Extension Control Register */
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#endif
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#define Z180_DMA_SAR0L 0x20 /* DMA Source Address Register Ch 0L */
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#define Z180_DMA_SAR0H 0x21 /* DMA Source Address Register Ch 0H */
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#define Z180_DMA_SAR0B 0x22 /* DMA Source Address Register Ch 0B */
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#define Z180_DMA_DAR0L 0x23 /* DMA Destination Address Register Ch 0L */
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#define Z180_DMA_DAR0H 0x24 /* DMA Destination Address Register Ch 0H */
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#define Z180_DMA_DAR0B 0x25 /* DMA Destination Address Register Ch 0B */
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#define Z180_DMA_BCR0L 0x26 /* DMA Byte Count Register Ch 0L */
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#define Z180_DMA_BCR0H 0x27 /* DMA Byte Count Register Ch 0H */
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#define Z180_DMA_MAR1L 0x28 /* DMA Memory Address Register Ch 1L */
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#define Z180_DMA_MAR1H 0x29 /* DMA Memory Address Register Ch 1H */
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#define Z180_DMA_MAR1B 0x2a /* DMA Memory Address Register Ch 1B */
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#define Z180_DMA_IAR1L 0x2b /* DMA I/0 Address Register Ch 1L */
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#define Z180_DMA_IAR1H 0x2c /* DMA I/0 Address Register Ch 1H */
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#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
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# define Z180_DMA_IAR1B 0x2d /* DMA I/O Address Register Ch 1B */
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# define Z180_ASCI0_ASTCL (SFR_OFFSET+0x1a) /* ASCI Time Constant Low */
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# define Z180_ASCI0_ASTCH (SFR_OFFSET+0x1b) /* ASCI Time Constant High */
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# define Z180_ASCI1_ASTCL (SFR_OFFSET+0x1c) /* ASCI Time Constant Low */
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# define Z180_ASCI1_ASTCH (SFR_OFFSET+0x1d) /* ASCI Time Constant High */
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#endif
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#define Z180_DMA_BCR1L 0x2e /* DMA Byte Count Register Ch 1L */
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#define Z180_DMA_BCR1H 0x2f /* DMA Byte Count Register Ch 1H */
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#define Z180_DMA_DSTAT 0x30 /* DMA Status Register */
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#define Z180_DMA_DMODE 0x31 /* DMA Mode Register */
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#define Z180_DMA_DCNTL 0x32 /* DMA/WAIT Control Register */
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#define Z180_INT_IL 0x33 /* IL Register (Interrupt Vector Low Register) */
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#define Z180_INT_ITC 0x34 /* INT/TRAP Control Register */
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/* CSI/O Registers */
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#define Z180_RCR 0x36 /* Refresh Control Register */
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#define Z180_CSIO_CNTR (SFR_OFFSET+0x0a) /* CSI/O Control Register */
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#define Z180_CSIO_TRD (SFR_OFFSET+0x0b) /* Transmit/Receive Data Register */
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#define Z180_MMU_CBR 0x38 /* MMU Common Base Register */
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#define Z180_MMU_BBR 0x39 /* MMU Bank Base Register */
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#define Z180_MMU_CBAR 0x3a /* MMU Common/Bank Area Register */
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/* Timer Registers */
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#define Z180_OMCR 0x3e /* Operation Mode Control Register */
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#define Z180_ICR 0x3f /* I/O Control Register */
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#define Z180_TMR0_DRL (SFR_OFFSET+0x0c) /* Timer Data Register Ch 0 L */
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#define Z180_TMR0_DRH (SFR_OFFSET+0x0d) /* Data Register Ch 0 H */
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#define Z180_TMR0_RLDRL (SFR_OFFSET+0x0e) /* Reload Register Ch 0 L */
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#define Z180_TMR0_RLDRH (SFR_OFFSET+0x0f) /* Reload Register Ch 0 H */
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#define Z180_TMR_TCR (SFR_OFFSET+0x10) /* Timer Control Register */
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/* Z180 Register Bit definitions ********************************************/
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#define Z180_TMR1_DRL (SFR_OFFSET+0x14) /* Data Register Ch 1 L */
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#define Z180_TMR1_DRH (SFR_OFFSET+0x15) /* Data Register Ch 1 H */
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#define Z180_TMR1_RLDRL (SFR_OFFSET+0x16) /* Reload Register Ch 1 L */
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#define Z180_TMR1_RLDRH (SFR_OFFSET+0x17) /* Reload Register Ch 1 H */
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#define Z180_FRC (SFR_OFFSET+0x18) /* Free Running Counter */
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/* DMA Registers */
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#define Z180_DMA_SAR0L (SFR_OFFSET+0x20) /* DMA Source Address Register Ch 0L */
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#define Z180_DMA_SAR0H (SFR_OFFSET+0x21) /* DMA Source Address Register Ch 0H */
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#define Z180_DMA_SAR0B (SFR_OFFSET+0x22) /* DMA Source Address Register Ch 0B */
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#define Z180_DMA_DAR0L (SFR_OFFSET+0x23) /* DMA Destination Address Register Ch 0L */
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#define Z180_DMA_DAR0H (SFR_OFFSET+0x24) /* DMA Destination Address Register Ch 0H */
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#define Z180_DMA_DAR0B (SFR_OFFSET+0x25) /* DMA Destination Address Register Ch 0B */
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#define Z180_DMA_BCR0L (SFR_OFFSET+0x26) /* DMA Byte Count Register Ch 0L */
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#define Z180_DMA_BCR0H (SFR_OFFSET+0x27) /* DMA Byte Count Register Ch 0H */
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#define Z180_DMA_MAR1L (SFR_OFFSET+0x28) /* DMA Memory Address Register Ch 1L */
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#define Z180_DMA_MAR1H (SFR_OFFSET+0x29) /* DMA Memory Address Register Ch 1H */
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#define Z180_DMA_MAR1B (SFR_OFFSET+0x2a) /* DMA Memory Address Register Ch 1B */
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#define Z180_DMA_IAR1L (SFR_OFFSET+0x2b) /* DMA I/0 Address Register Ch 1L */
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#define Z180_DMA_IAR1H (SFR_OFFSET+0x2c) /* DMA I/0 Address Register Ch 1H */
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#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
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# define Z180_DMA_IAR1B (SFR_OFFSET+0x2d) /* DMA I/O Address Register Ch 1B */
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#endif
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#define Z180_DMA_BCR1L (SFR_OFFSET+0x2e) /* DMA Byte Count Register Ch 1L */
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#define Z180_DMA_BCR1H (SFR_OFFSET+0x2f) /* DMA Byte Count Register Ch 1H */
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#define Z180_DMA_DSTAT (SFR_OFFSET+0x30) /* DMA Status Register */
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#define Z180_DMA_DMODE (SFR_OFFSET+0x31) /* DMA Mode Register */
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#define Z180_DMA_DCNTL (SFR_OFFSET+0x32) /* DMA/WAIT Control Register */
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/* System Control Registers */
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#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
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# define Z180_CMR (SFR_OFFSET+0x1e) /* Clock Multiplier Register */
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#endif
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#if defined(HAVE_Z8S180) || defined(HAVE_Z8X182)
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# define Z180_CCR (SFR_OFFSET+0x1f) /* CPU Control Register */
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#endif
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#define Z180_INT_IL (SFR_OFFSET+0x33) /* IL Register (Interrupt Vector Low Register) */
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#define Z180_INT_ITC (SFR_OFFSET+0x34) /* INT/TRAP Control Register */
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#define Z180_RCR (SFR_OFFSET+0x36) /* Refresh Control Register */
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#define Z180_MMU_CBR (SFR_OFFSET+0x38) /* MMU Common Base Register */
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#define Z180_MMU_BBR (SFR_OFFSET+0x39) /* MMU Bank Base Register */
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#define Z180_MMU_CBAR (SFR_OFFSET+0x3a) /* MMU Common/Bank Area Register */
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#define Z180_OMCR (SFR_OFFSET+0x3e) /* Operation Mode Control Register */
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#define Z180_ICR (SFR_OFFSET+0x3f) /* I/O Control Register */
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/* The following registers are not relocatable */
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/* Registers unique to Z8x181 class CPUs */
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#ifdef HAVE_Z8X181
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/* PIA Registers */
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# define Z181_PIA1_DDR 0xe0 /* PIA1 Data Direction Register */
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# define Z181_PIA1_DP 0xe1 /* PIA1 Data Port */
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# define Z181_PIA2_DDR 0xe2 /* PIA2 Data Direction Register */
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# define Z181_PIA1_DP 0xe3 /* PIA2 Data Register */
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/* CTC Registers */
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# define Z181_CTC0 0xe4 /* CTC Channel 0 Control Register */
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# define Z181_CTC1 0xe5 /* CTC Channel 1 Control Register */
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# define Z181_CTC2 0xe6 /* CTC Channel 2 Control Register */
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# define Z181_CTC3 0xe7 /* CTC Channel 3 Control Register */
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/* SCC Registers */
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# define Z181_SCC_CR 0xe8 /* SCC Control Register */
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# define Z181_SCC_DR 0xe9 /* SCC Data Register */
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/* System Control Registers */
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# define Z181_RAM_UBR 0xea /* RAM Upper Boundary Address Register */
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# define Z181_RAM_LBR 0xeb /* RAM Lower Boundary Address Register*/
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# define Z181_ROM_BR 0xec /* ROM Address Boundary Register */
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# define Z181_SCR 0xed /* System Configuration Register */
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#endif
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/* Registers unique to Z8x182 class CPUs */
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#ifdef HAVE_Z8X182
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# define Z182_WSGCS 0xd8 /* WSG Chip Select Register */
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# define Z182_ENH182 0xd9 /* Z80182 Enhancements Register */
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# define Z182_INTEDGE 0xdf /* Interrupt Edge/Pin MUX Control */
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# define Z182_PINMUX 0xdf /* Interrupt Edge/Pin MUX Control */
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/* PIA Registers */
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# define Z182_PA_DDR 0xed /* PA Data Direction Register */
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# define Z182_PA_DR 0xee /* PA Data Register */
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# define Z182_PB_DDR 0xe4 /* PB Data Direction Register */
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# define Z182_PB_DR 0xe5 /* PB Data Register */
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# define Z182_PC_DDR 0xdd /* PC Data Direction Register */
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# define Z182_PC_DR 0xde /* PC Data Register */
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/* ESCC Registers */
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# define Z182_ESCCA_CR 0xe0 /* ESCC Chan A Control Register */
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# define Z182_ESCCA_DR 0xe1 /* ESCC Chan A Data Register */
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# define Z182_ESCCB_CR 0xe2 /* ESCC Chan B Control Register */
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# define Z182_ESCCB_DR 0xe3 /* ESCC Chan B Data Register */
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||||
|
||||
/* System Control Registers */
|
||||
|
||||
# define Z182_RAM_UBR 0xe6 /* RAMUBR RAM Upper Boundary Register */
|
||||
# define Z182_RAM_LBR 0xe7 /* RAMLBR RAM Lower Boundary Register */
|
||||
# define Z182_ROM_BR 0xe8 /* ROM Address Boundary Register */
|
||||
# define Z182_SCR 0xef /* System Configuration Register */
|
||||
|
||||
/* 16550 MIMIC Registers */
|
||||
|
||||
# define Z182_MIMIC_FCR 0xe9 /* FIFO Control Register */
|
||||
# define Z182_MIMIC_MM 0xe9 /* MM register */
|
||||
# define Z182_MIMIC_RTTC 0xea /* Receive Timeout Time Constant */
|
||||
# define Z182_MIMIC_TTTC 0xeb /* Transmit Timeout Time Constant */
|
||||
# define Z182_MIMIC_FSCR 0xec /* FIFO Status and Control */
|
||||
# define Z182_MIMIC_RBR 0xf0 /* Receive Buffer Register */
|
||||
# define Z182_MIMIC_THR 0xf0 /* Transmit Holding Register */
|
||||
# define Z182_MIMIC_IER 0xf1 /* Interrupt Enable Register */
|
||||
# define Z182_MIMIC_LCR 0xf3 /* Line Control Register */
|
||||
# define Z182_MIMIC_MCR 0xf4 /* Modem Control Register */
|
||||
# define Z182_MIMIC_LSR 0xf5 /* Line Status Register */
|
||||
# define Z182_MIMIC_MSR 0xf6 /* Modem Status Register */
|
||||
# define Z182_MIMIC_SCR 0xf7 /* Scratch Register */
|
||||
# define Z182_MIMIC_DLL 0xf8 /* Divisor Latch (LSByte) */
|
||||
# define Z182_MIMIC_DLM 0xf9 /* Divisor Latch (MSByte) */
|
||||
# define Z182_MIMIC_TTCR 0xfa /* Transmit Time Constant */
|
||||
# define Z182_MIMIC_RTCR 0xfb /* Receive Time Constant */
|
||||
# define Z182_MIMIC_IVEC 0xfc /* Interrupt Vector */
|
||||
# define Z182_MIMIC_IE 0xfd /* Interrupt Enable */
|
||||
|
||||
# define Z182_MIMIC_IUSIP 0xfe /* Interrupt Under-Service/Interrupt Pending */
|
||||
# define Z182_MIMIC_MMC 0xff /* MIMIC Master Control Register */
|
||||
|
||||
/* Some of the MIMIC registers are accessible to memory-mapped addresses */
|
||||
|
||||
# define Z182_MIMIC_RBR_ADDR 0x0000 /* Receive Buffer Register */
|
||||
# define Z182_MIMIC_DLL_ADDR 0x0000 /* Divisor Latch (LSByte) */
|
||||
# define Z182_MIMIC_THR_ADDR 0x0000 /* Transmit Holding Register */
|
||||
# define Z182_MIMIC_DLM_ADDR 0x0001 /* Divisor Latch (MSByte) */
|
||||
# define Z182_MIMIC_IER_ADDR 0x0001 /* Interrupt Enable Register */
|
||||
# define Z182_MIMIC_IIR_ADDR 0x0002 /* Interrupt Identification */
|
||||
# define Z182_MIMIC_FCR_ADDR 0x0002 /* FIFO Control Register */
|
||||
# define Z182_MIMIC_LCR_ADDR 0x0003 /* Line Control Register */
|
||||
# define Z182_MIMIC_MCR_ADDR 0x0004 /* Modem Control Register */
|
||||
# define Z182_MIMIC_LSR_ADDR 0x0005 /* Line Status Register */
|
||||
# define Z182_MIMIC_MSR_ADDR 0x0006 /* Modem Status Register */
|
||||
# define Z182_MIMIC_SCR_ADDR 0x0007 /* Scratch Register */
|
||||
#endif
|
||||
|
||||
/* [E]SCC Internal Register Definitions */
|
||||
|
||||
#define Z18X_SCC_RR0 0x00
|
||||
#define Z18X_SCC_RR1 0x01
|
||||
#define Z18X_SCC_RR2 0x02
|
||||
#define Z18X_SCC_RR3 0x03
|
||||
#define Z18X_SCC_RR6 0x06
|
||||
#define Z18X_SCC_RR7 0x07
|
||||
#define Z18X_SCC_RR10 0x0a
|
||||
#define Z18X_SCC_RR12 0x0c
|
||||
#define Z18X_SCC_RR13 0x0d
|
||||
#define Z18X_SCC_RR15 0x0f
|
||||
|
||||
#define Z18X_SCC_WR0 0x00
|
||||
#define Z18X_SCC_WR1 0x01
|
||||
#define Z18X_SCC_WR2 0x02
|
||||
#define Z18X_SCC_WR3 0x03
|
||||
#define Z18X_SCC_WR4 0x04
|
||||
#define Z18X_SCC_WR5 0x05
|
||||
#define Z18X_SCC_WR6 0x06
|
||||
#define Z18X_SCC_WR7 0x07
|
||||
#define Z18X_SCC_WR9 0x09
|
||||
#define Z18X_SCC_WR10 0x0a
|
||||
#define Z18X_SCC_WR11 0x0b
|
||||
#define Z18X_SCC_WR12 0x0c
|
||||
#define Z18X_SCC_WR13 0x0d
|
||||
#define Z18X_SCC_WR14 0x0e
|
||||
#define Z18X_SCC_WR15 0x0f
|
||||
|
||||
/* Z180 Register Bit definitions ****************************************************/
|
||||
/* ASCI Registers *******************************************************************/
|
||||
/* ASCI Control Register A 0 (CNTLA0: 0x00) */
|
||||
/* ASCI Control Register A 1 (CNTLA1: 0x01) */
|
||||
|
||||
@ -179,6 +338,26 @@
|
||||
/* ASCI Receive Data Register Ch. 0 (RDR0: 0x08) - 8-bit data */
|
||||
/* ASCI Receive Data Register Ch. 1 (RDR0: 0x09) - 8-bit data */
|
||||
|
||||
/* ASCI0 Extension Control Register (I/O Address: 0x12) (Z8S180/L180-Class Processors Only) */
|
||||
/* ASCI1 Extension Control Register (I/O Address: 0x13) (Z8S180/L180-Class Processors Only) */
|
||||
|
||||
#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
|
||||
# define ASCI_ASEXT_RDRF (0x80) /* Bit 7: RDRF Interrupt Inhibit */
|
||||
# define ASCI0_ASEXT_DCD0 (0x80) /* Bit 6: DCD0 advisory to SW (ASCI0 only) */
|
||||
# define ASCI0_ASEXT_CTS0 (0x80) /* Bit 5: CTS0 advisory to SW (ASCI0 only) */
|
||||
# define ASCI_ASEXT_X1BC (0x80) /* Bit 4: CKA0 is bit clock */
|
||||
# define ASCI_ASEXT_BRG (0x80) /* Bit 3: Enable 16-bit BRG counter */
|
||||
# define ASCI_ASEXT_BRKEN (0x80) /* Bit 2: Break Feature Enable */
|
||||
# define ASCI_ASEXT_BRKDET (0x80) /* Bit 1: Break Detect */
|
||||
# define ASCI_ASEXT_SNDBRK (0x80) /* Bit 0: Send Break */
|
||||
#endif
|
||||
|
||||
/* ASCI0 Time Constant Low Register (I/O Address: 0x1a) (Z8S180/L180-Class Processors Only) -- 8-bit data */
|
||||
/* ASCI0 Time Constant High Register (I/O Address: 0x1b) (Z8S180/L180-Class Processors Only) -- 8-bit data */
|
||||
/* ASCI1 Time Constant Low Register (I/O Address: 0x1c) (Z8S180/L180-Class Processors Only) -- 8-bit data */
|
||||
/* ASCI1 Time Constant High Register (I/O Address: 0x1d) (Z8S180/L180-Class Processors Only) -- 8-bit data */
|
||||
|
||||
/* CSI/O Registers ******************************************************************/
|
||||
/* CSI/O Control/Status Register (CNTR: 0x0a) */
|
||||
|
||||
#define CSIO_CNTR_EF (0x80) /* Bit 7: End Flag */
|
||||
@ -196,8 +375,9 @@
|
||||
# define CSIO_CNTR_DIV1280 (6 << CSIO_CNTR_SS_SHIFT) /* Divide Ratio: 1280 Baud: 3125 */
|
||||
# define CSIO_CNTR_EXT (7 << CSIO_CNTR_SS_SHIFT) /* External Clock input (less than 20) */
|
||||
/* Baud at Phi = 4 MHz */
|
||||
|
||||
/* CSI/O Transmit/Receive Register (TRDR: 0x0b) -- 8-bit data */
|
||||
|
||||
/* Timer Registers ******************************************************************/
|
||||
/* Timer Data Register 0L (TMDR0L: 0x0c) -- 8-bit data */
|
||||
/* Timer Data Register 0H (TMDR0H: 0x0d) -- 8-bit data */
|
||||
/* Timer Reload Register Channel 0L (RLDR0L: 0x0e) -- 8-bit data */
|
||||
@ -214,55 +394,15 @@
|
||||
#define TMR_TCR_TDE1 (0x02) /* Bit 1: Timer 1 Down Count Enable */
|
||||
#define TMR_TCR_TDE0 (0x01) /* Bit 0: Timer 0 Down Count Enable */
|
||||
|
||||
/* ASCI0 Extension Control Register (I/O Address: 0x12) (Z8S180/L180-Class Processors Only) */
|
||||
/* ASCI1 Extension Control Register (I/O Address: 0x13) (Z8S180/L180-Class Processors Only) */
|
||||
|
||||
#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
|
||||
# define ASCI_ASEXT_RDRF (0x80) /* Bit 7: RDRF Interrupt Inhibit */
|
||||
# define ASCI0_ASEXT_DCD0 (0x80) /* Bit 6: DCD0 advisory to SW (ASCI0 only) */
|
||||
# define ASCI0_ASEXT_CTS0 (0x80) /* Bit 5: CTS0 advisory to SW (ASCI0 only) */
|
||||
# define ASCI_ASEXT_X1BC (0x80) /* Bit 4: CKA0 is bit clock */
|
||||
# define ASCI_ASEXT_BRG (0x80) /* Bit 3: Enable 16-bit BRG counter */
|
||||
# define ASCI_ASEXT_BRKEN (0x80) /* Bit 2: Break Feature Enable */
|
||||
# define ASCI_ASEXT_BRKDET (0x80) /* Bit 1: Break Detect */
|
||||
# define ASCI_ASEXT_SNDBRK (0x80) /* Bit 0: Send Break */
|
||||
#endif
|
||||
|
||||
/* Timer Data Register 1L (TMDR1L: 0x14) -- 8-bit data */
|
||||
/* Timer Data Register 1H (TMDR1H: 0x15) -- 8-bit data */
|
||||
/* Timer Reload Register Channel 1L (RLDR1L: 0x16) -- 8-bit data */
|
||||
/* Timer Reload Register Channel 1H (RLDR1H: 0x17) -- 8-bit data */
|
||||
/* Free Running counter (FRC: 0x18) -- 8-bit data */
|
||||
|
||||
/* ASCI0 Time Constant Low Register (I/O Address: 0x1a) (Z8S180/L180-Class Processors Only) -- 8-bit data */
|
||||
/* ASCI0 Time Constant High Register (I/O Address: 0x1b) (Z8S180/L180-Class Processors Only) -- 8-bit data */
|
||||
/* ASCI1 Time Constant Low Register (I/O Address: 0x1c) (Z8S180/L180-Class Processors Only) -- 8-bit data */
|
||||
/* ASCI1 Time Constant High Register (I/O Address: 0x1d) (Z8S180/L180-Class Processors Only) -- 8-bit data */
|
||||
|
||||
/* Clock Multiplier Register (CMR: 0x1e) (Z8S180/L180-Class Processors Only) */
|
||||
|
||||
#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
|
||||
# define CMR_CMM (0x80) /* Bit 7: X2 Clock Multiplier Mode */
|
||||
#endif
|
||||
|
||||
/* CPU Control Register (CCR: 0x1f) (Z8S180/L180-Class Processors Only) */
|
||||
|
||||
#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
|
||||
# define CCR_XTAL_DIV (0x80) /* Bit 7: Clock Divide */
|
||||
# define CCR_STBYIDLE (0x48) /* Bits 3 & 6: STANDBY/IDLE mode */
|
||||
# define CCR_NOSTDBY (0x00) /* No STANDBY */
|
||||
# define CCR_IDLE (0x08) /* IDLE after SLEEP */
|
||||
# define CCR_STBY (0x40) /* STANDBY after SLEEP */
|
||||
# define CCR_STBY64 (0x48) /* STANDBY after SLEEP 64 Cycle Exit */
|
||||
# define CCR_BREXT (0x20) /* Bit 5: STANDBY/IDLE exit on BUSREQ */
|
||||
# define CCR_LNPHI (0x10) /* Bit 4: 33% Drive on EXTPHI Clock */
|
||||
# define CCR_LNIO (0x04) /* Bit 2: 33% Drive on certain external I/O */
|
||||
# define CCR_LNCPUCTLR (0x02) /* Bit 1: 33% Drive on CPU control signals */
|
||||
# define LNADDATA (0x01) /* Bit 0: 33% drive on A10–A0, D7–D0 */
|
||||
#endif
|
||||
|
||||
/* DMA Registers ********************************************************************/
|
||||
/* DMA Destination Address Register Channel 0 (DAR0 I/O Address 0x23 to 0x25) -- 8-bit data */
|
||||
/*DMA Byte Count Register Channel 0 (BCR0 I/O Address = 0x26 to 0x27) -- 8-bit data */
|
||||
/* DMA Byte Count Register Channel 0 (BCR0 I/O Address = 0x26 to 0x27) -- 8-bit data */
|
||||
/* DMA Memory Address Register Channel 1 (MAR1: I/O Address = 0x28 to 0x2a) -- 8-bit data */
|
||||
/* DMA I/O Address Register Channel 1 (IAR1: I/O Address = 0x2b to 0x2c) -- 8-bit data */
|
||||
|
||||
@ -327,6 +467,29 @@
|
||||
# define DCNTL_DIM_IO2MI (2 << DCNTL_DIM_SHIFT) /* I/O to memory, increment MARI */
|
||||
# define DCNTL_DIM_IO2MD (3 << DCNTL_DIM_SHIFT) /* I/O to memory, decrement MARI */
|
||||
|
||||
/* System Control Registers *********************************************************/
|
||||
/* Clock Multiplier Register (CMR: 0x1e) (Z8S180/L180-Class Processors Only) */
|
||||
|
||||
#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
|
||||
# define CMR_CMM (0x80) /* Bit 7: X2 Clock Multiplier Mode */
|
||||
#endif
|
||||
|
||||
/* CPU Control Register (CCR: 0x1f) (Z8S180/L180-Class Processors Only) */
|
||||
|
||||
#ifdef HAVE_Z8S180 /* Z8S180/Z8L180 class processors */
|
||||
# define CCR_XTAL_DIV (0x80) /* Bit 7: Clock Divide */
|
||||
# define CCR_STBYIDLE (0x48) /* Bits 3 & 6: STANDBY/IDLE mode */
|
||||
# define CCR_NOSTDBY (0x00) /* No STANDBY */
|
||||
# define CCR_IDLE (0x08) /* IDLE after SLEEP */
|
||||
# define CCR_STBY (0x40) /* STANDBY after SLEEP */
|
||||
# define CCR_STBY64 (0x48) /* STANDBY after SLEEP 64 Cycle Exit */
|
||||
# define CCR_BREXT (0x20) /* Bit 5: STANDBY/IDLE exit on BUSREQ */
|
||||
# define CCR_LNPHI (0x10) /* Bit 4: 33% Drive on EXTPHI Clock */
|
||||
# define CCR_LNIO (0x04) /* Bit 2: 33% Drive on certain external I/O */
|
||||
# define CCR_LNCPUCTLR (0x02) /* Bit 1: 33% Drive on CPU control signals */
|
||||
# define LNADDATA (0x01) /* Bit 0: 33% drive on A10-A0, D7-D0 */
|
||||
#endif
|
||||
|
||||
/* Interrupt Vector Low Register (IL: 0x33) */
|
||||
|
||||
#define IL_SHIFT (5) /* Bits 5-7: 3-bits of vector interrupt table address */
|
||||
@ -375,4 +538,34 @@
|
||||
# define ICR_IOA7 (2 << ICR_IOA_SHIFT)
|
||||
#define ICR_IOSTP (0x20) /* Bit 5: Enable I/O stop mode */
|
||||
|
||||
/* Registers unique to Z8x181 class CPUs ********************************************/
|
||||
|
||||
#ifdef HAVE_Z8X181
|
||||
/* To be provided */
|
||||
|
||||
/* PIA Registers */
|
||||
|
||||
/* CTC Registers */
|
||||
|
||||
/* SCC Registers */
|
||||
|
||||
/* System Control Registers */
|
||||
|
||||
#endif
|
||||
|
||||
/* Registers unique to Z8x182 class CPUs ********************************************/
|
||||
|
||||
#ifdef HAVE_Z8X182
|
||||
/* To be provided */
|
||||
|
||||
/* PIA Registers */
|
||||
|
||||
/* ESCC Registers */
|
||||
|
||||
/* System Control Registers */
|
||||
|
||||
/* 16550 MIMIC Registers */
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_Z80_SRC_Z180_Z180_IOMAP_H */
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user