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SAMA5D3/4: UPLL divisor to generate 48MHz for OHCI is different from the two families. No idea why.

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This commit is contained in:
Gregory Nutt 2014-07-03 12:28:11 -06:00
parent d5d12d6e55
commit a5538e3431
11 changed files with 45 additions and 8 deletions
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12
arch/arm/src/sama5/sam_clockconfig.c
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@ -492,15 +492,13 @@ static inline void sam_usbclockconfig(void)
* PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is
* selected.
*
* REVISIT: The divisor of 10 produces a rate that is too high. Division
* by 5, however, seems to work just fine. No idea why?
* REVISIT: The divisor of 10 produces a rate that is too high with
* SAMA5D3. A divisor of 5, however, seems to work just fine for the
* SAMA5D3. The SAMA5D4, on the other hand, needs the divisor of 10.
* No idea why? Let the board.h file decide which to use.
*/
#if 1 /* REVISIT */
regval |= PMC_USB_USBDIV(4); /* Division by 5 */
#else
regval |= PMC_USB_USBDIV(9); /* Division by 10 */
#endif
regval |= PMC_USB_USBDIV(BOARD_UPLL_OHCI_DIV-1);
putreg32(regval, SAM_PMC_USB);
#else /* BOARD_USE_UPLL */

2
arch/arm/src/sama5/sam_ohci.c
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@ -1880,7 +1880,7 @@ static void sam_wdh_bottomhalf(void)
/* Invalidate D-cache to force re-reading of the Done Head */
# if 0 /* Apparently insufficient */
#if 0 /* Apparently insufficient */
cp15_invalidate_dcache((uintptr_t)&g_hcca.donehead,
(uintptr_t)&g_hcca.donehead + sizeof(uint32_t));
#else

6
configs/sama5d3-xplained/include/board_396mhz.h
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@ -162,6 +162,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
/* REVISIT: The divisor of 10 produces a rate that is too high. Division
* by 5, however, seems to work just fine. No idea why?
*/
# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* HSMCI clocking

6
configs/sama5d3-xplained/include/board_528mhz.h
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@ -161,6 +161,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
/* REVISIT: The divisor of 10 produces a rate that is too high. Division
* by 5, however, seems to work just fine. No idea why?
*/
# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* HSMCI clocking

6
configs/sama5d3-xplained/include/board_sdram.h
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@ -100,6 +100,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
/* REVISIT: The divisor of 10 produces a rate that is too high. Division
* by 5, however, seems to work just fine. No idea why?
*/
# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* ADC Configuration

6
configs/sama5d3x-ek/include/board_396mhz.h
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@ -162,6 +162,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
/* REVISIT: The divisor of 10 produces a rate that is too high. Division
* by 5, however, seems to work just fine. No idea why?
*/
# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* HSMCI clocking

6
configs/sama5d3x-ek/include/board_528mhz.h
View File

@ -160,6 +160,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
/* REVISIT: The divisor of 10 produces a rate that is too high. Division
* by 5, however, seems to work just fine. No idea why?
*/
# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* HSMCI clocking

6
configs/sama5d3x-ek/include/board_sdram.h
View File

@ -100,6 +100,12 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
/* REVISIT: The divisor of 10 produces a rate that is too high. Division
* by 5, however, seems to work just fine. No idea why?
*/
# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
#endif
/* ADC Configuration

1
configs/sama5d4-ek/include/board_396mhz.h
View File

@ -161,6 +161,7 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
# define BOARD_UPLL_OHCI_DIV (10) /* Divide by 10 */
#endif
/* HSMCI clocking

1
configs/sama5d4-ek/include/board_528mhz.h
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@ -160,6 +160,7 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
# define BOARD_UPLL_OHCI_DIV (10) /* Divide by 10 */
#endif
/* HSMCI clocking

1
configs/sama5d4-ek/include/board_sdram.h
View File

@ -101,6 +101,7 @@
# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
# define BOARD_UPLL_OHCI_DIV (10) /* Divide by 10 */
#endif
/* ADC Configuration