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arch/arm/Make.defs: unify common source include

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Signed-off-by: chao.an <anchao@xiaomi.com>
This commit is contained in:
chao.an 2022-04-27 20:28:49 +08:00 committed by Xiang Xiao
parent 2a95be5086
commit a560eb5f8d
53 changed files with 509 additions and 1034 deletions
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38
arch/arm/src/a1x/Make.defs
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@ -18,6 +18,8 @@
#
############################################################################
include armv7-a/Make.defs
# The vector table is the "head" object, i.e., the one that must forced into
# the link in order to draw in all of the other components
@ -34,50 +36,30 @@ endif
# debug.
ifeq ($(CONFIG_PAGING),y)
CMN_ASRCS = arm_pghead.S
CMN_ASRCS += arm_pghead.S
else
CMN_ASRCS = arm_head.S
CMN_ASRCS += arm_head.S
endif
# Common assembly language files
CMN_ASRCS += arm_vectors.S arm_vectoraddrexcptn.S vfork.S
CMN_ASRCS += arm_fpuconfig.S arm_testset.S arm_fetchadd.S
CMN_ASRCS += arm_vectors.S arm_vectoraddrexcptn.S arm_fpuconfig.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
CMN_ASRCS += cp15_clean_dcache_all.S cp15_flush_dcache_all.S cp15_cache_size.S
# Common C source files
CMN_CSRCS = arm_initialize.c arm_interruptcontext.c arm_exit.c arm_createstack.c
CMN_CSRCS += arm_releasestack.c arm_usestack.c arm_vfork.c arm_puts.c arm_mdelay.c
CMN_CSRCS += arm_stackframe.c arm_udelay.c arm_modifyreg8.c arm_modifyreg16.c
CMN_CSRCS += arm_modifyreg32.c arm_assert.c arm_blocktask.c arm_dataabort.c
CMN_CSRCS += arm_doirq.c arm_initialstate.c arm_mmu.c arm_prefetchabort.c
CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_syscall.c arm_unblocktask.c arm_undefinedinsn.c
CMN_CSRCS += arm_switchcontext.c arm_saveusercontext.c arm_fullcontextrestore.c
CMN_CSRCS += arm_dataabort.c arm_doirq.c arm_initialstate.c arm_mmu.c
CMN_CSRCS += arm_prefetchabort.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_syscall.c arm_undefinedinsn.c
CMN_CSRCS += arm_cache.c arm_tcbinfo.c
# Use common heap allocation for now (may need to be customized later)
CMN_CSRCS += arm_allocateheap.c
# Configuration dependent C and assembly language files
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
ifeq ($(CONFIG_PAGING),y)
CMN_CSRCS += arm_allocpage.c arm_checkmapping.c arm_pginitialize.c
CMN_CSRCS += arm_va2pte.c
endif
ifeq ($(CONFIG_BUILD_KERNEL),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c arm_signal_dispatch.c
endif
ifeq ($(CONFIG_ARCH_ADDRENV),y)
CMN_CSRCS += arm_addrenv.c arm_addrenv_utils.c arm_pgalloc.c
ifeq ($(CONFIG_ARCH_STACK_DYNAMIC),y)
@ -102,10 +84,6 @@ ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# A1x-specific C source files
CHIP_CSRCS = a1x_boot.c a1x_irq.c a1x_pio.c a1x_lowputc.c a1x_serial.c

31
arch/arm/src/am335x/Make.defs
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@ -18,6 +18,8 @@
#
############################################################################
include armv7-a/Make.defs
# The vector table is the "head" object, i.e., the one that must forced into
# the link in order to draw in all of the other components
@ -34,36 +36,25 @@ endif
# debug.
ifeq ($(CONFIG_PAGING),y)
CMN_ASRCS = arm_pghead.S
CMN_ASRCS += arm_pghead.S
else
CMN_ASRCS = arm_head.S
CMN_ASRCS += arm_head.S
endif
# Common assembly language files
CMN_ASRCS += arm_vectors.S arm_vectoraddrexcptn.S
CMN_ASRCS += arm_fpuconfig.S arm_testset.S vfork.S
CMN_ASRCS += arm_vectors.S arm_vectoraddrexcptn.S arm_fpuconfig.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
CMN_ASRCS += cp15_clean_dcache_all.S cp15_flush_dcache_all.S cp15_cache_size.S
# Common C source files
CMN_CSRCS = arm_initialize.c arm_idle.c arm_interruptcontext.c arm_exit.c
CMN_CSRCS += arm_createstack.c arm_releasestack.c arm_usestack.c arm_vfork.c
CMN_CSRCS += arm_puts.c arm_mdelay.c arm_stackframe.c arm_udelay.c
CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_assert.c arm_blocktask.c arm_dataabort.c
CMN_CSRCS += arm_doirq.c arm_initialstate.c arm_mmu.c arm_prefetchabort.c
CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_syscall.c arm_unblocktask.c arm_undefinedinsn.c
CMN_CSRCS += arm_switchcontext.c arm_saveusercontext.c arm_fullcontextrestore.c
CMN_CSRCS += arm_schedulesigaction.c arm_dataabort.c
CMN_CSRCS += arm_sigdeliver.c arm_syscall.c arm_undefinedinsn.c
CMN_CSRCS += arm_cache.c arm_tcbinfo.c
# Use common heap allocation for now (may need to be customized later)
CMN_CSRCS += arm_allocateheap.c
# Configuration dependent C and assembly language files
ifeq ($(CONFIG_PAGING),y)
@ -71,10 +62,6 @@ CMN_CSRCS += arm_allocpage.c arm_checkmapping.c arm_pginitialize.c
CMN_CSRCS += arm_va2pte.c
endif
ifeq ($(CONFIG_BUILD_KERNEL),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c arm_signal_dispatch.c
endif
ifeq ($(CONFIG_ARCH_ADDRENV),y)
CMN_CSRCS += arm_addrenv.c arm_addrenv_utils.c arm_pgalloc.c
ifeq ($(CONFIG_ARCH_STACK_DYNAMIC),y)
@ -99,10 +86,6 @@ ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# AM335x-specific C source files
CHIP_CSRCS = am335x_boot.c am335x_clockconfig.c am335x_pinmux.c am335x_irq.c

23
arch/arm/src/arm/Make.defs Normal file
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@ -0,0 +1,23 @@
############################################################################
# arch/arm/src/arm/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# Common ARM files
include common/Make.defs

23
arch/arm/src/armv6-m/Make.defs Normal file
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@ -0,0 +1,23 @@
############################################################################
# arch/arm/src/armv6-m/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# Common ARM files
include common/Make.defs

23
arch/arm/src/armv7-a/Make.defs Normal file
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@ -0,0 +1,23 @@
############################################################################
# arch/arm/src/armv7-a/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# Common ARM files
include common/Make.defs

23
arch/arm/src/armv7-m/Make.defs Normal file
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@ -0,0 +1,23 @@
############################################################################
# arch/arm/src/armv7-m/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# Common ARM files
include common/Make.defs

23
arch/arm/src/armv7-r/Make.defs Normal file
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@ -0,0 +1,23 @@
############################################################################
# arch/arm/src/armv7-r/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# Common ARM files
include common/Make.defs

23
arch/arm/src/armv8-m/Make.defs Normal file
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@ -0,0 +1,23 @@
############################################################################
# arch/arm/src/armv8-m/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# Common ARM files
include common/Make.defs

22
arch/arm/src/c5471/Make.defs
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@ -18,25 +18,13 @@
#
############################################################################
include arm/Make.defs
HEAD_ASRC = arm_nommuhead.S
CMN_ASRCS = vfork.S
CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_dataabort.c arm_mdelay.c arm_udelay.c arm_doirq.c
CMN_CSRCS += arm_exit.c arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_prefetchabort.c arm_releasepending.c arm_releasestack.c
CMN_CSRCS += arm_reprioritizertr.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_stackframe.c arm_syscall.c arm_unblocktask.c arm_undefinedinsn.c
CMN_CSRCS += arm_switchcontext.c arm_saveusercontext.c arm_fullcontextrestore.c
CMN_CSRCS += arm_usestack.c arm_vfork.c arm_puts.c arm_tcbinfo.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
CMN_CSRCS += arm_dataabort.c arm_doirq.c arm_initialstate.c
CMN_CSRCS += arm_prefetchabort.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_syscall.c arm_undefinedinsn.c arm_tcbinfo.c
CHIP_ASRCS = c5471_lowputc.S c5471_vectors.S
CHIP_CSRCS = c5471_irq.c c5471_serial.c c5471_watchdog.c c5471_ethernet.c

86
arch/arm/src/common/Make.defs Normal file
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@ -0,0 +1,86 @@
############################################################################
# arch/arm/src/common/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# Common ARM files
CMN_CSRCS += arm_allocateheap.c arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_exit.c arm_fullcontextrestore.c
CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_lowputs.c
CMN_CSRCS += arm_mdelay.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_modifyreg8.c arm_puts.c arm_releasepending.c
CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_saveusercontext.c
CMN_CSRCS += arm_stackframe.c arm_switchcontext.c arm_udelay.c
CMN_CSRCS += arm_vfork.c arm_unblocktask.c arm_usestack.c
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED)$(CONFIG_BUILD_KERNEL),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_UASRCS += arm_signal_handler.S
endif
endif
ifeq ($(CONFIG_ARM_SEMIHOSTING_SYSLOG),y)
CMN_CSRCS += arm_semi_syslog.c
endif
ifeq ($(CONFIG_ARM_SEMIHOSTING_HOSTFS),y)
CMN_CSRCS += arm_hostfs.c
endif
ifeq ($(CONFIG_SCHED_THREAD_LOCAL),y)
CMN_CSRCS += arm_tls.c
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
ifeq ($(CONFIG_FRAME_POINTER),y)
CMN_CSRCS += arm_backtrace_fp.c
else
CMN_CSRCS += arm_backtrace_thumb.c
endif
endif
CMN_ASRCS += vfork.S
ifeq ($(CONFIG_ARCH_HAVE_TESTSET),y)
ifeq ($(CONFIG_ARCH_ARMV6M),)
CMN_ASRCS += arm_testset.S
endif
endif
ifeq ($(CONFIG_ARCH_HAVE_FETCHADD),y)
CMN_ASRCS += arm_fetchadd.S
endif
# Use of common/arm_etherstub.c is deprecated. The preferred mechanism is to
# use CONFIG_NETDEV_LATEINIT=y to suppress the call to arm_netinitialize() in
# up_initialize(). Then this stub would not be needed.
ifeq ($(CONFIG_NET),y)
ifneq ($(CONFIG_ARCH_HAVE_PHY),y)
CMN_CSRCS += arm_etherstub.c
endif
endif

2
arch/arm/src/common/arm_etherstub.c
View File

@ -50,6 +50,8 @@
*
****************************************************************************/
#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT)
void arm_netinitialize(void)
{
}
#endif

25
arch/arm/src/cxd56xx/Make.defs
View File

@ -18,20 +18,13 @@
#
############################################################################
CMN_ASRCS = vfork.S arm_exception.S
include armv7-m/Make.defs
ifneq ($(CONFIG_CXD56_TESTSET),y)
CMN_ASRCS += arm_testset.S
endif
CMN_ASRCS += arm_exception.S
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_exit.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_unblocktask.c arm_usestack.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_svcall.c arm_vfork.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c arm_vectors.c
CMN_CSRCS += arm_initialstate.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_doirq.c arm_hardfault.c arm_svcall.c
CMN_CSRCS += arm_tcbinfo.c arm_vectors.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
@ -42,13 +35,7 @@ CMN_ASRCS += up_memcpy.S
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)

25
arch/arm/src/dm320/Make.defs
View File

@ -18,27 +18,16 @@
#
############################################################################
include arm/Make.defs
HEAD_ASRC = arm_head.S
CMN_ASRCS = arm_cache.S arm_vectors.S
CMN_ASRCS += arm_vectoraddrexcptn.S arm_vectortab.S vfork.S
CMN_ASRCS += arm_cache.S arm_vectors.S
CMN_ASRCS += arm_vectoraddrexcptn.S arm_vectortab.S
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c
CMN_CSRCS += arm_dataabort.c arm_mdelay.c arm_udelay.c arm_exit.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_prefetchabort.c arm_releasepending.c arm_releasestack.c
CMN_CSRCS += arm_reprioritizertr.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_stackframe.c arm_syscall.c arm_unblocktask.c
CMN_CSRCS += arm_undefinedinsn.c arm_usestack.c arm_vfork.c arm_switchcontext.c
CMN_CSRCS += arm_saveusercontext.c arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
CMN_CSRCS += arm_dataabort.c arm_initialstate.c arm_prefetchabort.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c
CMN_CSRCS += arm_undefinedinsn.c arm_tcbinfo.c
CHIP_ASRCS = dm320_lowputc.S dm320_restart.S

30
arch/arm/src/efm32/Make.defs
View File

@ -18,35 +18,21 @@
#
############################################################################
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_vectors.c arm_allocateheap.c arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_doirq.c arm_exit.c arm_hardfault.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_itm.c arm_mdelay.c arm_memfault.c arm_modifyreg8.c
CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasepending.c
CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_stackframe.c arm_svcall.c arm_systemreset.c
CMN_CSRCS += arm_trigger_irq.c arm_udelay.c arm_unblocktask.c arm_usestack.c
CMN_CSRCS += arm_vfork.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_itm.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_svcall.c arm_systemreset.c
CMN_CSRCS += arm_trigger_irq.c arm_tcbinfo.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)

32
arch/arm/src/eoss3/Make.defs
View File

@ -18,37 +18,19 @@
#
############################################################################
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_vectors.c arm_allocateheap.c arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_doirq.c arm_exit.c arm_hardfault.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_itm.c arm_mdelay.c arm_memfault.c arm_modifyreg8.c
CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasepending.c
CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_stackframe.c arm_svcall.c arm_systemreset.c
CMN_CSRCS += arm_trigger_irq.c arm_udelay.c arm_unblocktask.c arm_usestack.c
CMN_CSRCS += arm_vfork.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_initialstate.c arm_itm.c arm_memfault.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_svcall.c
CMN_CSRCS += arm_systemreset.c arm_trigger_irq.c arm_tcbinfo.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c

25
arch/arm/src/imx1/Make.defs
View File

@ -18,27 +18,16 @@
#
############################################################################
include arm/Make.defs
HEAD_ASRC = arm_head.S
CMN_ASRCS = arm_cache.S
CMN_ASRCS += arm_vectors.S arm_vectoraddrexcptn.S arm_vectortab.S vfork.S
CMN_ASRCS += arm_cache.S
CMN_ASRCS += arm_vectors.S arm_vectoraddrexcptn.S arm_vectortab.S
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c
CMN_CSRCS += arm_dataabort.c arm_mdelay.c arm_udelay.c arm_exit.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_prefetchabort.c arm_releasepending.c arm_releasestack.c
CMN_CSRCS += arm_reprioritizertr.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_stackframe.c arm_syscall.c arm_unblocktask.c arm_undefinedinsn.c
CMN_CSRCS += arm_usestack.c arm_vfork.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
CMN_CSRCS += arm_dataabort.c arm_initialstate.c arm_prefetchabort.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c
CMN_CSRCS += arm_undefinedinsn.c arm_tcbinfo.c
CHIP_ASRCS = imx_lowputc.S
CHIP_CSRCS = imx_boot.c imx_gpio.c imx_allocateheap.c imx_irq.c

37
arch/arm/src/imx6/Make.defs
View File

@ -18,6 +18,8 @@
#
############################################################################
include armv7-a/Make.defs
# The vector table is the "head" object, i.e., the one that must forced into
# the link in order to draw in all of the other components
@ -34,9 +36,9 @@ endif
# debug.
ifeq ($(CONFIG_PAGING),y)
CMN_ASRCS = arm_pghead.S
CMN_ASRCS += arm_pghead.S
else
CMN_ASRCS = arm_head.S
CMN_ASRCS += arm_head.S
ifeq ($(CONFIG_SMP),y)
CMN_ASRCS += arm_cpuhead.S
endif
@ -45,26 +47,17 @@ endif
# Common assembly language files
CMN_ASRCS += arm_vectors.S arm_fpuconfig.S
CMN_ASRCS += arm_vectoraddrexcptn.S arm_testset.S arm_fetchadd.S vfork.S
CMN_ASRCS += arm_vectoraddrexcptn.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
CMN_ASRCS += cp15_clean_dcache_all.S cp15_flush_dcache_all.S cp15_cache_size.S
# Common C source files
CMN_CSRCS = arm_initialize.c arm_interruptcontext.c arm_exit.c arm_createstack.c
CMN_CSRCS += arm_releasestack.c arm_usestack.c arm_vfork.c arm_puts.c arm_mdelay.c
CMN_CSRCS += arm_stackframe.c arm_udelay.c arm_modifyreg8.c arm_modifyreg16.c
CMN_CSRCS += arm_modifyreg32.c arm_assert.c arm_blocktask.c arm_dataabort.c
CMN_CSRCS += arm_doirq.c arm_gicv2.c arm_initialstate.c arm_mmu.c
CMN_CSRCS += arm_prefetchabort.c arm_releasepending.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c
CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c arm_switchcontext.c
CMN_CSRCS += arm_saveusercontext.c arm_fullcontextrestore.c arm_cache.c arm_tcbinfo.c
ifeq ($(CONFIG_ARM_SEMIHOSTING_HOSTFS),y)
CMN_CSRCS += arm_hostfs.c
endif
CMN_CSRCS += arm_dataabort.c arm_doirq.c arm_gicv2.c arm_initialstate.c
CMN_CSRCS += arm_mmu.c arm_prefetchabort.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_syscall.c arm_undefinedinsn.c
CMN_CSRCS += arm_cache.c arm_tcbinfo.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += imx_idle.c
@ -79,10 +72,6 @@ ifeq ($(CONFIG_DEBUG_IRQ_INFO),y)
CMN_CSRCS += arm_gicv2_dump.c
endif
# Use common heap allocation for now (may need to be customized later)
CMN_CSRCS += arm_allocateheap.c
# Configuration dependent C and assembly language files
ifeq ($(CONFIG_PAGING),y)
@ -90,10 +79,6 @@ CMN_CSRCS += arm_allocpage.c arm_checkmapping.c arm_pginitialize.c
CMN_CSRCS += arm_va2pte.c
endif
ifeq ($(CONFIG_BUILD_KERNEL),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c arm_signal_dispatch.c
endif
ifeq ($(CONFIG_ARCH_ADDRENV),y)
CMN_CSRCS += arm_addrenv.c arm_addrenv_utils.c arm_pgalloc.c
ifeq ($(CONFIG_ARCH_STACK_DYNAMIC),y)
@ -122,10 +107,6 @@ ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# i.MX6-specific C source files
CHIP_CSRCS = imx_boot.c imx_memorymap.c imx_clockconfig.c imx_irq.c

30
arch/arm/src/imxrt/Make.defs
View File

@ -20,22 +20,14 @@
# Common ARM and Cortex-M7 files
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_mdelay.c arm_udelay.c arm_exit.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_unblocktask.c arm_usestack.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_svcall.c arm_vfork.c arm_trigger_irq.c arm_systemreset.c
CMN_CSRCS += arm_switchcontext.c arm_saveusercontext.c arm_fullcontextrestore.c
CMN_CSRCS += arm_puts.c arm_tcbinfo.c arm_vectors.c
CMN_ASRCS += arm_exception.S
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
CMN_CSRCS += arm_initialstate.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_systemreset.c
CMN_CSRCS += arm_tcbinfo.c arm_vectors.c
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
@ -49,16 +41,6 @@ ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
CMN_CSRCS += arm_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)

40
arch/arm/src/kinetis/Make.defs
View File

@ -18,22 +18,14 @@
#
############################################################################
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c
CMN_CSRCS += arm_mdelay.c arm_udelay.c arm_exit.c arm_initialize.c arm_memfault.c
CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_modifyreg8.c
CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasestack.c
CMN_CSRCS += arm_reprioritizertr.c arm_schedulesigaction.c arm_releasepending.c
CMN_CSRCS += arm_sigdeliver.c arm_stackframe.c arm_unblocktask.c arm_usestack.c
CMN_CSRCS += arm_doirq.c arm_hardfault.c arm_svcall.c arm_vfork.c
CMN_CSRCS += arm_systemreset.c arm_trigger_irq.c arm_switchcontext.c
CMN_CSRCS += arm_saveusercontext.c arm_fullcontextrestore.c arm_puts.c
CMN_CSRCS += arm_tcbinfo.c
CMN_ASRCS += arm_exception.S
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
CMN_CSRCS += arm_vectors.c arm_memfault.c arm_initialstate.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_doirq.c arm_hardfault.c arm_svcall.c
CMN_CSRCS += arm_systemreset.c arm_trigger_irq.c arm_tcbinfo.c
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
@ -47,26 +39,6 @@ ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# Use of common/arm_etherstub.c is deprecated. The preferred mechanism is to
# use CONFIG_NETDEV_LATEINIT=y to suppress the call to arm_netinitialize() in
# up_initialize(). Then this stub would not be needed.
ifeq ($(CONFIG_NET),y)
ifneq ($(CONFIG_KINETIS_ENET),y)
CMN_CSRCS += arm_etherstub.c
endif
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c

29
arch/arm/src/kl/Make.defs
View File

@ -18,32 +18,13 @@
#
############################################################################
CMN_ASRCS = arm_exception.S vfork.S
include armv6-m/Make.defs
CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_mdelay.c arm_udelay.c arm_exit.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_puts.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_systemreset.c arm_unblocktask.c arm_usestack.c arm_doirq.c
CMN_CSRCS += arm_hardfault.c arm_svcall.c arm_vectors.c arm_vfork.c
CMN_CSRCS += arm_switchcontext.c arm_saveusercontext.c arm_fullcontextrestore.c
CMN_CSRCS += arm_tcbinfo.c
CMN_ASRCS += arm_exception.S
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
CMN_CSRCS += arm_initialstate.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_systemreset.c arm_doirq.c arm_hardfault.c arm_svcall.c
CMN_CSRCS += arm_vectors.c arm_tcbinfo.c
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += arm_dumpnvic.c

30
arch/arm/src/lc823450/Make.defs
View File

@ -18,33 +18,19 @@
#
############################################################################
CMN_ASRCS = vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_mdelay.c arm_udelay.c arm_exit.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_initialstate.c arm_memfault.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_systemreset.c
CMN_CSRCS += arm_unblocktask.c arm_usestack.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_svcall.c arm_vfork.c arm_trigger_irq.c arm_switchcontext.c
CMN_CSRCS += arm_saveusercontext.c arm_fullcontextrestore.c
CMN_CSRCS += arm_puts.c arm_tcbinfo.c arm_stackframe.c arm_vectors.c
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
CMN_CSRCS += arm_doirq.c arm_hardfault.c arm_svcall.c arm_trigger_irq.c
CMN_CSRCS += arm_tcbinfo.c arm_vectors.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += memcpy-armv7m.S
endif
@ -53,10 +39,6 @@ ifeq ($(CONFIG_ARCH_MEMMOVE),y)
CMN_CSRCS += up_memmove.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
CHIP_CSRCS = lc823450_allocateheap2.c lc823450_start.c lc823450_irq.c lc823450_timer.c
CHIP_CSRCS += lc823450_lowputc.c lc823450_serial.c lc823450_clockconfig.c
CHIP_CSRCS += lc823450_syscontrol.c lc823450_gpio.c

36
arch/arm/src/lpc17xx_40xx/Make.defs
View File

@ -20,22 +20,14 @@
# Common ARM and Cortex-M3 files
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c
CMN_CSRCS += arm_mdelay.c arm_udelay.c arm_exit.c arm_initialize.c arm_memfault.c
CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_modifyreg8.c
CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasepending.c
CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_stackframe.c arm_trigger_irq.c
CMN_CSRCS += arm_unblocktask.c arm_usestack.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_svcall.c arm_checkstack.c arm_vfork.c arm_switchcontext.c
CMN_CSRCS += arm_saveusercontext.c arm_fullcontextrestore.c arm_systemreset.c
CMN_CSRCS += arm_puts.c arm_tcbinfo.c arm_perf.c
CMN_ASRCS += arm_exception.S
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
CMN_CSRCS += arm_vectors.c arm_memfault.c arm_initialstate.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_trigger_irq.c
CMN_CSRCS += arm_doirq.c arm_hardfault.c arm_svcall.c arm_systemreset.c
CMN_CSRCS += arm_tcbinfo.c arm_perf.c
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
@ -49,22 +41,6 @@ ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
# Use of common/arm_etherstub.c is deprecated. The preferred mechanism is to
# use CONFIG_NETDEV_LATEINIT=y to suppress the call to arm_netinitialize() in
# up_initialize(). Then this stub would not be needed.
ifeq ($(CONFIG_NET),y)
ifneq ($(CONFIG_LPC17_40_ETHERNET),y)
CMN_CSRCS += arm_etherstub.c
endif
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c

24
arch/arm/src/lpc214x/Make.defs
View File

@ -18,26 +18,14 @@
#
##############################################################################
HEAD_ASRC = lpc214x_head.S
CMN_ASRCS = arm_vectors.S vfork.S
include arm/Make.defs
CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_dataabort.c arm_mdelay.c arm_udelay.c
CMN_CSRCS += arm_exit.c arm_initialize.c arm_initialstate.c
CMN_CSRCS += arm_interruptcontext.c arm_prefetchabort.c arm_releasepending.c
CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_stackframe.c
CMN_CSRCS += arm_syscall.c arm_unblocktask.c arm_undefinedinsn.c arm_usestack.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_lowputs.c arm_vfork.c
CMN_CSRCS += arm_switchcontext.c arm_saveusercontext.c arm_fullcontextrestore.c
CMN_CSRCS += arm_puts.c arm_tcbinfo.c
HEAD_ASRC = lpc214x_head.S
CMN_ASRCS += arm_vectors.S
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
CMN_CSRCS += arm_dataabort.c arm_initialstate.c arm_prefetchabort.c
CMN_CSRCS += arm_syscall.c arm_undefinedinsn.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_tcbinfo.c
CHIP_ASRCS = lpc214x_lowputc.S
CHIP_CSRCS = lpc214x_decodeirq.c lpc214x_irq.c lpc214x_serial.c

24
arch/arm/src/lpc2378/Make.defs
View File

@ -18,26 +18,14 @@
#
##############################################################################
HEAD_ASRC = lpc23xx_head.S
CMN_ASRCS = arm_vectors.S vfork.S
include arm/Make.defs
CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_dataabort.c arm_mdelay.c arm_udelay.c
CMN_CSRCS += arm_exit.c arm_initialize.c arm_initialstate.c
CMN_CSRCS += arm_interruptcontext.c arm_prefetchabort.c arm_releasepending.c
CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_stackframe.c
CMN_CSRCS += arm_syscall.c arm_unblocktask.c arm_undefinedinsn.c
CMN_CSRCS += arm_usestack.c arm_lowputs.c arm_vfork.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c
HEAD_ASRC = lpc23xx_head.S
CMN_ASRCS += arm_vectors.S
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
CMN_CSRCS += arm_dataabort.c arm_initialstate.c arm_prefetchabort.c
CMN_CSRCS += arm_syscall.c arm_undefinedinsn.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_tcbinfo.c
CHIP_ASRCS = lpc23xx_lowputc.S
CHIP_CSRCS += lpc23xx_pllsetup.c lpc23xx_decodeirq.c lpc23xx_irq.c

26
arch/arm/src/lpc31xx/Make.defs
View File

@ -18,33 +18,21 @@
#
############################################################################
include arm/Make.defs
HEAD_ASRC = arm_head.S
CMN_ASRCS = arm_cache.S
CMN_ASRCS += arm_vectors.S arm_vectoraddrexcptn.S arm_vectortab.S vfork.S
CMN_ASRCS += arm_cache.S
CMN_ASRCS += arm_vectors.S arm_vectoraddrexcptn.S arm_vectortab.S
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c
CMN_CSRCS += arm_dataabort.c arm_mdelay.c arm_udelay.c arm_exit.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_prefetchabort.c arm_releasepending.c arm_releasestack.c
CMN_CSRCS += arm_reprioritizertr.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_stackframe.c arm_syscall.c arm_unblocktask.c
CMN_CSRCS += arm_undefinedinsn.c arm_usestack.c arm_vfork.c arm_switchcontext.c
CMN_CSRCS += arm_saveusercontext.c arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
CMN_CSRCS += arm_dataabort.c arm_initialstate.c arm_prefetchabort.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c
CMN_CSRCS += arm_undefinedinsn.c arm_tcbinfo.c
ifeq ($(CONFIG_PAGING),y)
CMN_CSRCS += arm_pginitialize.c arm_checkmapping.c arm_allocpage.c arm_va2pte.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
CGU_CSRCS = lpc31_bcrndx.c lpc31_clkdomain.c lpc31_clkexten.c
CGU_CSRCS += lpc31_clkfreq.c lpc31_clkinit.c lpc31_defclk.c
CGU_CSRCS += lpc31_esrndx.c lpc31_fdcndx.c lpc31_fdivinit.c

30
arch/arm/src/lpc43xx/Make.defs
View File

@ -18,17 +18,13 @@
#
############################################################################
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c
CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c
CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c
CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_unblocktask.c arm_udelay.c
CMN_CSRCS += arm_usestack.c arm_vfork.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_initialstate.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_svcall.c arm_trigger_irq.c arm_tcbinfo.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
@ -38,20 +34,6 @@ ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c

30
arch/arm/src/lpc54xx/Make.defs
View File

@ -18,17 +18,13 @@
#
############################################################################
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c
CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c
CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c
CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_unblocktask.c arm_udelay.c
CMN_CSRCS += arm_usestack.c arm_vfork.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_initialstate.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_svcall.c arm_trigger_irq.c arm_tcbinfo.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
@ -38,20 +34,6 @@ ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c

30
arch/arm/src/max326xx/Make.defs
View File

@ -20,35 +20,21 @@
# Common ARMv7-M Source Files
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c arm_vectors.c
CMN_CSRCS += arm_createstack.c arm_doirq.c arm_exit.c arm_hardfault.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_mdelay.c arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c
CMN_CSRCS += arm_modifyreg32.c arm_releasepending.c arm_releasestack.c
CMN_CSRCS += arm_reprioritizertr.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_stackframe.c arm_svcall.c arm_trigger_irq.c arm_unblocktask.c
CMN_CSRCS += arm_udelay.c arm_usestack.c arm_vfork.c arm_switchcontext.c
CMN_CSRCS += arm_saveusercontext.c arm_fullcontextrestore.c
CMN_CSRCS += arm_puts.c arm_tcbinfo.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_initialstate.c arm_memfault.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_tcbinfo.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)

18
arch/arm/src/moxart/Make.defs
View File

@ -18,18 +18,14 @@
#
############################################################################
HEAD_ASRC = moxart_head.S
CMN_ASRCS = arm_vectors.S arm_nommuhead.S vfork.S
include arm/Make.defs
CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_dataabort.c arm_mdelay.c arm_udelay.c
CMN_CSRCS += arm_exit.c arm_initialstate.c arm_initialize.c
CMN_CSRCS += arm_interruptcontext.c arm_prefetchabort.c arm_releasepending.c
CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_stackframe.c arm_syscall.c arm_unblocktask.c
CMN_CSRCS += arm_undefinedinsn.c arm_usestack.c arm_vfork.c arm_etherstub.c
CMN_CSRCS += arm_switchcontext.c arm_saveusercontext.c arm_fullcontextrestore.c
CMN_CSRCS += arm_puts.c arm_tcbinfo.c
HEAD_ASRC = moxart_head.S
CMN_ASRCS += arm_vectors.S arm_nommuhead.S
CMN_CSRCS += arm_dataabort.c arm_initialstate.c arm_prefetchabort.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c
CMN_CSRCS += arm_undefinedinsn.c arm_tcbinfo.c
CHIP_ASRCS = moxart_lowputc.S

32
arch/arm/src/nrf52/Make.defs
View File

@ -18,24 +18,20 @@
#
############################################################################
CMN_ASRCS = arm_testset.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_vectors.c
CMN_CSRCS += arm_createstack.c arm_doirq.c arm_exit.c arm_hardfault.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c
CMN_CSRCS += arm_modifyreg32.c arm_releasepending.c arm_releasestack.c
CMN_CSRCS += arm_reprioritizertr.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_stackframe.c arm_svcall.c arm_trigger_irq.c arm_udelay.c
CMN_CSRCS += arm_unblocktask.c arm_usestack.c arm_vfork.c arm_systemreset.c
CMN_CSRCS += arm_switchcontext.c arm_saveusercontext.c arm_fullcontextrestore.c
CMN_CSRCS += arm_puts.c arm_tcbinfo.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_systemreset.c
CMN_CSRCS += arm_tcbinfo.c
ifeq ($(CONFIG_NRF52_SYSTIMER_SYSTICK),y)
CMN_CSRCS += arm_systick.c nrf52_systick.c
else
ifeq ($(CONFIG_NRF52_SYSTIMER_RTC),y)
CMN_CSRCS += nrf52_tickless_rtc.c arm_mdelay.c
CMN_CSRCS += nrf52_tickless_rtc.c
endif
endif
@ -44,17 +40,7 @@ CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)

29
arch/arm/src/nuc1xx/Make.defs
View File

@ -18,32 +18,13 @@
#
############################################################################
CMN_ASRCS = arm_exception.S vfork.S
include armv6-m/Make.defs
CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_mdelay.c arm_udelay.c arm_exit.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_systemreset.c arm_unblocktask.c arm_usestack.c arm_doirq.c
CMN_CSRCS += arm_hardfault.c arm_svcall.c arm_vectors.c arm_vfork.c
CMN_CSRCS += arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c
CMN_ASRCS += arm_exception.S
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
CMN_CSRCS += arm_initialstate.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_systemreset.c arm_doirq.c arm_hardfault.c arm_svcall.c
CMN_CSRCS += arm_vectors.c arm_tcbinfo.c
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += arm_dumpnvic.c

26
arch/arm/src/phy62xx/Make.defs
View File

@ -18,32 +18,16 @@
#
############################################################################
CMN_ASRCS = phy62xx_exception.S phy62xx_start.S vfork.S
include armv6-m/Make.defs
CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_mdelay.c arm_udelay.c arm_exit.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_puts.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_systemreset.c arm_unblocktask.c arm_usestack.c arm_doirq.c
CMN_CSRCS += phy62xx_hardfault.c arm_svcall.c arm_vectors.c arm_vfork.c
CMN_CSRCS += arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_tcbinfo.c
CMN_ASRCS += phy62xx_exception.S phy62xx_start.S
ifeq ($(CONFIG_ARCH_HAVE_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
CMN_CSRCS += arm_initialstate.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_systemreset.c arm_doirq.c phy62xx_hardfault.c
CMN_CSRCS += arm_svcall.c arm_vectors.c arm_tcbinfo.c
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_pthread_exit.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
ifeq ($(CONFIG_DEBUG_FEATURES),y)

31
arch/arm/src/rp2040/Make.defs
View File

@ -18,37 +18,18 @@
#
############################################################################
CMN_ASRCS = arm_exception.S vfork.S
include armv6-m/Make.defs
CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_mdelay.c arm_udelay.c arm_exit.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_systemreset.c arm_unblocktask.c arm_usestack.c arm_doirq.c
CMN_CSRCS += arm_hardfault.c arm_svcall.c arm_vectors.c arm_vfork.c
CMN_CSRCS += arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_initialstate.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_systemreset.c arm_doirq.c arm_hardfault.c arm_svcall.c
CMN_CSRCS += arm_vectors.c arm_tcbinfo.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += arm_dumpnvic.c
endif

26
arch/arm/src/rtl8720c/Make.defs
View File

@ -18,34 +18,18 @@
#
############################################################################
# arch/arm/src/common
#
CMN_CSRCS += arm_checkstack.c arm_createstack.c arm_exit.c arm_hostfs.c
CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_modifyreg8.c
CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_pthread_start.c
CMN_CSRCS += arm_puts.c arm_releasestack.c arm_semi_syslog.c
CMN_CSRCS += arm_stackframe.c arm_task_start.c arm_usestack.c arm_vfork.c
include armv8-m/Make.defs
# arch/arm/src/armv8-m
#
CMN_ASRCS += arm_exception.S arm_fetchadd.S arm_setjmp.S
CMN_ASRCS += arm_testset.S vfork.S
CMN_ASRCS += arm_exception.S arm_setjmp.S
CMN_UASRCS += arm_signal_handler.S
CMN_CSRCS += arm_assert.c arm_blocktask.c arm_cache.c
CMN_CSRCS += arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_cache.c arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_itm_syslog.c arm_memfault.c arm_mpu.c arm_ramvec_attach.c
CMN_CSRCS += arm_ramvec_initialize.c arm_releasepending.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_signal_dispatch.c
CMN_CSRCS += arm_stackcheck.c arm_svcall.c arm_systick.c arm_unblocktask.c
CMN_CSRCS += arm_switchcontext.c arm_saveusercontext.c arm_fullcontextrestore.c
CMN_CSRCS += arm_ramvec_initialize.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_stackcheck.c arm_svcall.c arm_systick.c
CMN_CSRCS += arm_tcbinfo.c
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
# arch/arm/src/rtl8720c
#
CHIP_CSRCS += ameba_nvic.c ameba_heap.c ameba_idle.c ameba_uart.c ameba_start.c

16
arch/arm/src/s32k1xx/Make.defs
View File

@ -20,24 +20,8 @@
# Common ARM source files
CMN_CSRCS = arm_allocateheap.c arm_exit.c arm_initialize.c arm_interruptcontext.c
CMN_CSRCS += arm_lowputs.c arm_mdelay.c arm_modifyreg8.c arm_modifyreg16.c
CMN_CSRCS += arm_modifyreg32.c arm_puts.c arm_releasestack.c arm_stackframe.c
CMN_CSRCS += arm_task_start.c arm_udelay.c arm_usestack.c arm_vfork.c
CMN_CSRCS += arm_tcbinfo.c
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_pthread_start.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c

16
arch/arm/src/s32k1xx/s32k11x/Make.defs
View File

@ -20,19 +20,13 @@
# Source files specific to the Cortex-M0+
CMN_ASRCS += arm_exception.S vfork.S
include armv6-m/Make.defs
CMN_CSRCS += arm_assert.c arm_blocktask.c arm_createstack.c
CMN_CSRCS += arm_initialstate.c arm_releasepending.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_systemreset.c
CMN_CSRCS += arm_unblocktask.c arm_doirq.c arm_hardfault.c arm_svcall.c
CMN_CSRCS += arm_vectors.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c
CMN_ASRCS += arm_exception.S
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
CMN_CSRCS += arm_initialstate.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_systemreset.c arm_doirq.c
CMN_CSRCS += arm_hardfault.c arm_svcall.c arm_vectors.c
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += arm_dumpnvic.c

16
arch/arm/src/s32k1xx/s32k14x/Make.defs
View File

@ -20,22 +20,20 @@
# Source files specific to the Cortex-M4F
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS += arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c
CMN_CSRCS += arm_doirq.c arm_hardfault.c arm_initialstate.c arm_memfault.c
CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_svcall.c arm_trigger_irq.c arm_unblocktask.c
CMN_CSRCS += arm_systemreset.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_initialstate.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_svcall.c arm_trigger_irq.c arm_systemreset.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
CMN_CSRCS += arm_mpu.c
endif
# Source file specific to the S32k11x family

34
arch/arm/src/sam34/Make.defs
View File

@ -22,23 +22,13 @@
# Common ARM and Cortex-M3 files
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c
CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c
CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c
CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_unblocktask.c arm_udelay.c
CMN_CSRCS += arm_usestack.c arm_vfork.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c
CMN_ASRCS += arm_exception.S
ifneq ($(CONFIG_SMP),y)
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
endif
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_tcbinfo.c
# Configuration-dependent common files
@ -50,25 +40,11 @@ ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# Required SAM3/4 files
CHIP_CSRCS = sam_allocateheap.c sam_irq.c sam_lowputc.c sam_serial.c

31
arch/arm/src/sama5/Make.defs
View File

@ -18,6 +18,8 @@
#
############################################################################
include armv7-a/Make.defs
# The vector table is the "head" object, i.e., the one that must forced into
# the link in order to draw in all of the other components
@ -34,15 +36,14 @@ endif
# debug.
ifeq ($(CONFIG_PAGING),y)
CMN_ASRCS = arm_pghead.S
CMN_ASRCS += arm_pghead.S
else
CMN_ASRCS = arm_head.S
CMN_ASRCS += arm_head.S
endif
# Common assembly language files
CMN_ASRCS += arm_vectors.S arm_fpuconfig.S arm_vectoraddrexcptn.S
CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
CMN_ASRCS += cp15_clean_dcache_all.S cp15_flush_dcache_all.S cp15_cache_size.S
@ -51,22 +52,12 @@ CMN_ASRCS += cp15_clean_dcache_all.S cp15_flush_dcache_all.S cp15_cache_size.S
# Common C source files
CMN_CSRCS = arm_initialize.c arm_interruptcontext.c arm_exit.c arm_createstack.c
CMN_CSRCS += arm_releasestack.c arm_usestack.c arm_vfork.c arm_puts.c arm_mdelay.c
CMN_CSRCS += arm_stackframe.c arm_udelay.c arm_modifyreg8.c arm_modifyreg16.c
CMN_CSRCS += arm_modifyreg32.c arm_assert.c arm_blocktask.c arm_dataabort.c
CMN_CSRCS += arm_doirq.c arm_initialstate.c arm_mmu.c arm_prefetchabort.c
CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c arm_cache.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c
CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c arm_tcbinfo.c
CMN_CSRCS += arm_switchcontext.c arm_saveusercontext.c arm_fullcontextrestore.c
CMN_CSRCS += arm_dataabort.c arm_doirq.c arm_initialstate.c arm_mmu.c
CMN_CSRCS += arm_prefetchabort.c arm_cache.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_syscall.c arm_undefinedinsn.c arm_tcbinfo.c
# Configuration dependent C files
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
ifeq ($(CONFIG_ARMV7A_L2CC_PL310),y)
CMN_CSRCS += arm_l2cc_pl310.c
endif
@ -76,10 +67,6 @@ CMN_CSRCS += arm_allocpage.c arm_checkmapping.c arm_pginitialize.c
CMN_CSRCS += arm_va2pte.c
endif
ifeq ($(CONFIG_BUILD_KERNEL),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c arm_signal_dispatch.c
endif
ifeq ($(CONFIG_ARCH_ADDRENV),y)
CMN_CSRCS += arm_addrenv.c arm_addrenv_utils.c arm_pgalloc.c
ifeq ($(CONFIG_ARCH_STACK_DYNAMIC),y)
@ -104,10 +91,6 @@ ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# SAMA5-specific C source files
CHIP_CSRCS = sam_allocateheap.c sam_boot.c sam_clockconfig.c sam_irq.c

29
arch/arm/src/samd2l2/Make.defs
View File

@ -18,32 +18,13 @@
#
############################################################################
CMN_ASRCS = arm_exception.S vfork.S
include armv6-m/Make.defs
CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_mdelay.c arm_udelay.c arm_exit.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_systemreset.c arm_unblocktask.c arm_usestack.c arm_doirq.c
CMN_CSRCS += arm_hardfault.c arm_svcall.c arm_vectors.c arm_vfork.c
CMN_CSRCS += arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c
CMN_ASRCS += arm_exception.S
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
CMN_CSRCS += arm_initialstate.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_systemreset.c arm_doirq.c arm_hardfault.c arm_svcall.c
CMN_CSRCS += arm_vectors.c arm_tcbinfo.c
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += arm_dumpnvic.c

28
arch/arm/src/samd5e5/Make.defs
View File

@ -22,17 +22,13 @@
# Common ARM and Cortex-M4 files
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c arm_vectors.c
CMN_CSRCS += arm_createstack.c arm_exit.c arm_initialize.c arm_initialstate.c
CMN_CSRCS += arm_interruptcontext.c arm_mdelay.c arm_memfault.c arm_modifyreg8.c
CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasepending.c
CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_stackframe.c arm_svcall.c arm_trigger_irq.c
CMN_CSRCS += arm_unblocktask.c arm_udelay.c arm_usestack.c arm_doirq.c
CMN_CSRCS += arm_hardfault.c arm_vfork.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_tcbinfo.c arm_puts.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_initialstate.c arm_memfault.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_svcall.c
CMN_CSRCS += arm_trigger_irq.c arm_doirq.c arm_hardfault.c arm_tcbinfo.c
# Configuration-dependent common files
@ -41,9 +37,7 @@ CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
@ -51,14 +45,6 @@ CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# Required SAMD5x/E5x files
CHIP_CSRCS = sam_clockconfig.c sam_gclk.c sam_irq.c sam_lowputc.c

34
arch/arm/src/samv7/Make.defs
View File

@ -23,28 +23,17 @@
# Common ARM and Cortex-M7 files
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c
CMN_CSRCS += arm_exit.c arm_hardfault.c arm_initialize.c arm_initialstate.c
CMN_CSRCS += arm_interruptcontext.c arm_mdelay.c arm_udelay.c arm_systemreset.c
CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_unblocktask.c arm_usestack.c
CMN_CSRCS += arm_doirq.c arm_vfork.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c arm_cache.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_systemreset.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_svcall.c arm_trigger_irq.c
CMN_CSRCS += arm_doirq.c arm_tcbinfo.c arm_cache.c
# Configuration-dependent common files
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
@ -60,15 +49,6 @@ endif
ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# Required SAMV7 files

35
arch/arm/src/stm32/Make.defs
View File

@ -18,26 +18,19 @@
#
############################################################################
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c
CMN_CSRCS += arm_exit.c arm_hardfault.c arm_initialize.c arm_initialstate.c
CMN_CSRCS += arm_interruptcontext.c arm_memfault.c arm_modifyreg8.c arm_mdelay.c
CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasepending.c
CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_stackframe.c arm_svcall.c arm_systemreset.c
CMN_CSRCS += arm_trigger_irq.c arm_unblocktask.c arm_udelay.c arm_usestack.c
CMN_CSRCS += arm_doirq.c arm_vfork.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c arm_perf.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c
CMN_CSRCS += arm_doirq.c arm_tcbinfo.c arm_perf.c
ifeq ($(CONFIG_STM32_TICKLESS_SYSTICK),y)
CMN_CSRCS += arm_systick.c
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
@ -50,16 +43,6 @@ ifneq ($(filter y,$(CONFIG_ARM_MPU) $(CONFIG_ARM_MPU_EARLY_RESET)),)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
@ -69,10 +52,6 @@ ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
CMN_CSRCS += arm_itm_syslog.c
endif
ifeq ($(CONFIG_SCHED_THREAD_LOCAL),y)
CMN_CSRCS += arm_tls.c
endif
CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c
CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c
CHIP_CSRCS += stm32_irq.c stm32_lowputc.c

29
arch/arm/src/stm32f0l0g0/Make.defs
View File

@ -18,32 +18,13 @@
#
############################################################################
CMN_ASRCS = arm_exception.S vfork.S
include armv6-m/Make.defs
CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_mdelay.c arm_udelay.c arm_exit.c
CMN_CSRCS += arm_initialize.c arm_initialstate.c arm_interruptcontext.c
CMN_CSRCS += arm_puts.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_systemreset.c arm_unblocktask.c arm_usestack.c arm_doirq.c
CMN_CSRCS += arm_hardfault.c arm_svcall.c arm_vectors.c arm_vfork.c
CMN_CSRCS += arm_switchcontext.c arm_saveusercontext.c arm_fullcontextrestore.c
CMN_CSRCS += arm_tcbinfo.c
CMN_ASRCS += arm_exception.S
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
CMN_CSRCS += arm_initialstate.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_systemreset.c arm_doirq.c arm_hardfault.c arm_svcall.c
CMN_CSRCS += arm_vectors.c arm_tcbinfo.c
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += arm_dumpnvic.c

34
arch/arm/src/stm32f7/Make.defs
View File

@ -23,27 +23,15 @@
# Common ARM and Cortex-M7 files
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c
CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c arm_puts.c
CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c
CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c arm_unblocktask.c
CMN_CSRCS += arm_udelay.c arm_usestack.c arm_vfork.c arm_switchcontext.c
CMN_CSRCS += arm_saveusercontext.c arm_fullcontextrestore.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c
CMN_CSRCS += arm_tcbinfo.c arm_cache.c
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
@ -67,16 +55,6 @@ ifneq ($(filter y,$(CONFIG_ARM_MPU) $(CONFIG_ARM_MPU_EARLY_RESET)),)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# Required STM32F7 files
CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c

37
arch/arm/src/stm32h7/Make.defs
View File

@ -23,28 +23,19 @@
# Common ARM and Cortex-M7 files
CMN_ASRCS = arm_testset.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c
CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c
CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c arm_memfault.c
CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c arm_svcall.c
CMN_CSRCS += arm_systemreset.c arm_trigger_irq.c arm_udelay.c arm_unblocktask.c
CMN_CSRCS += arm_usestack.c arm_vfork.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c arm_cache.c arm_perf.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c
CMN_CSRCS += arm_tcbinfo.c arm_cache.c arm_perf.c
ifeq ($(CONFIG_ARMV7M_SYSTICK),y)
CMN_CSRCS += arm_systick.c
endif
# Configuration-dependent common files
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
@ -54,10 +45,6 @@ CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
@ -70,16 +57,6 @@ ifneq ($(filter y,$(CONFIG_ARM_MPU) $(CONFIG_ARM_MPU_EARLY_RESET)),)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# Required STM32H7 files
CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c stm32_irq.c

32
arch/arm/src/stm32l4/Make.defs
View File

@ -23,25 +23,15 @@
# Common ARM and Cortex-M4 files (copied from stm32/Make.defs)
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c
CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c
CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c arm_memfault.c
CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c arm_udelay.c
CMN_CSRCS += arm_unblocktask.c arm_usestack.c arm_vfork.c arm_switchcontext.c
CMN_CSRCS += arm_saveusercontext.c arm_fullcontextrestore.c arm_puts.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c
CMN_CSRCS += arm_tcbinfo.c arm_vectors.c
# Configuration-dependent common files
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
@ -59,16 +49,6 @@ ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# Required STM32L4 files
CHIP_CSRCS = stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c

28
arch/arm/src/stm32l5/Make.defs
View File

@ -25,24 +25,16 @@ HEAD_ASRC =
# Common ARM and Cortex-M4 files (copied from stm32/Make.defs)
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv8-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c
CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c
CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c arm_memfault.c
CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c arm_udelay.c
CMN_CSRCS += arm_unblocktask.c arm_usestack.c arm_vfork.c arm_switchcontext.c
CMN_CSRCS += arm_saveusercontext.c arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c arm_tcbinfo.c
# Configuration-dependent common files
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_ARMV8M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
@ -57,13 +49,7 @@ CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
CMN_CSRCS += arm_mpu.c
endif
# Required STM32L5 files

30
arch/arm/src/stm32u5/Make.defs
View File

@ -25,24 +25,18 @@ HEAD_ASRC =
# Common ARM and Cortex-M4 files (copied from stm32/Make.defs)
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv8-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c
CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c
CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c arm_memfault.c
CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c arm_puts.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_svcall.c arm_switchcontext.c arm_systemreset.c arm_tcbinfo.c
CMN_CSRCS += arm_trigger_irq.c arm_udelay.c arm_unblocktask.c arm_usestack.c
CMN_CSRCS += arm_vfork.c arm_saveusercontext.c arm_fullcontextrestore.c
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_initialstate.c arm_memfault.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_tcbinfo.c
CMN_CSRCS += arm_trigger_irq.c
# Configuration-dependent common files
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_ARMV8M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
@ -57,14 +51,8 @@ CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_mpu.c
CMN_CSRCS += arm_pthread_exit.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# Required STM32U5 files

24
arch/arm/src/str71x/Make.defs
View File

@ -18,27 +18,15 @@
#
##############################################################################
include arm/Make.defs
HEAD_ASRC = str71x_head.S
CMN_ASRCS = arm_vectors.S vfork.S
CMN_ASRCS += arm_vectors.S
CMN_CSRCS = arm_allocateheap.c arm_assert.c arm_blocktask.c
CMN_CSRCS += arm_createstack.c arm_dataabort.c arm_mdelay.c arm_udelay.c
CMN_CSRCS += arm_exit.c arm_initialize.c arm_initialstate.c
CMN_CSRCS += arm_interruptcontext.c arm_prefetchabort.c arm_releasepending.c
CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_stackframe.c
CMN_CSRCS += arm_syscall.c arm_unblocktask.c arm_undefinedinsn.c arm_usestack.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_lowputs.c arm_vfork.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
CMN_CSRCS += arm_dataabort.c arm_initialstate.c arm_prefetchabort.c
CMN_CSRCS += arm_syscall.c arm_undefinedinsn.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_tcbinfo.c
CHIP_CSRCS = str71x_prccu.c str71x_lowputc.c str71x_decodeirq.c str71x_irq.c
CHIP_CSRCS += str71x_serial.c

34
arch/arm/src/tiva/Make.defs
View File

@ -18,21 +18,13 @@
#
############################################################################
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c
CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c
CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c
CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_unblocktask.c arm_udelay.c
CMN_CSRCS += arm_usestack.c arm_vfork.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c arm_vectors.c
CMN_ASRCS += arm_exception.S
ifeq ($(CONFIG_ARM_SEMIHOSTING_HOSTFS),y)
CMN_CSRCS += arm_hostfs.c
endif
CMN_CSRCS += arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_tcbinfo.c arm_vectors.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += tiva_idle.c
@ -47,26 +39,10 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
else
CMN_CSRCS += arm_allocateheap.c
endif
CHIP_CSRCS = tiva_allocateheap.c tiva_irq.c tiva_lowputc.c tiva_serial.c
CHIP_CSRCS += tiva_ssi.c

36
arch/arm/src/tms570/Make.defs
View File

@ -18,15 +18,17 @@
#
############################################################################
include armv7-r/Make.defs
# The vector table is the "head" object, i.e., the one that must forced into
# the link in order to draw in all of the other components
HEAD_ASRC = arm_vectortab.S
HEAD_ASRC += arm_vectortab.S
# Common assembly language files
CMN_ASRCS += arm_vectortab.S arm_vectors.S arm_head.S
CMN_ASRCS += arm_vectoraddrexcptn.S arm_testset.S arm_fetchadd.S vfork.S
CMN_ASRCS += arm_vectoraddrexcptn.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S
CMN_ASRCS += cp15_clean_dcache_all.S cp15_flush_dcache_all.S
@ -40,28 +42,14 @@ endif
# Common C source files
CMN_CSRCS = arm_allocateheap.c arm_initialize.c arm_interruptcontext.c
CMN_CSRCS += arm_exit.c arm_createstack.c arm_releasestack.c arm_usestack.c
CMN_CSRCS += arm_vfork.c arm_puts.c arm_mdelay.c arm_stackframe.c arm_udelay.c
CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_assert.c arm_blocktask.c arm_dataabort.c
CMN_CSRCS += arm_doirq.c arm_initialstate.c arm_prefetchabort.c
CMN_CSRCS += arm_releasepending.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_syscall.c
CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c arm_switchcontext.c
CMN_CSRCS += arm_saveusercontext.c arm_fullcontextrestore.c arm_cache.c
CMN_CSRCS += arm_dataabort.c arm_doirq.c arm_initialstate.c
CMN_CSRCS += arm_prefetchabort.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_syscall.c arm_undefinedinsn.c arm_cache.c
# Configuration dependent C files
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARMV7R_L2CC_PL310),y)
@ -72,14 +60,6 @@ ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# SAMA5-specific C source files
CHIP_CSRCS = tms570_boot.c tms570_clockconfig.c tms570_esm.c tms570_gio.c

38
arch/arm/src/xmc4/Make.defs
View File

@ -18,21 +18,13 @@
#
############################################################################
CMN_ASRCS = arm_testset.S arm_fetchadd.S vfork.S arm_exception.S
include armv7-m/Make.defs
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_createstack.c arm_vectors.c
CMN_CSRCS += arm_doirq.c arm_exit.c arm_initialize.c arm_initialstate.c
CMN_CSRCS += arm_hardfault.c arm_interruptcontext.c arm_memfault.c arm_mdelay.c
CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_schedulesigaction.c
CMN_CSRCS += arm_releasepending.c arm_sigdeliver.c arm_stackframe.c arm_svcall.c
CMN_CSRCS += arm_systemreset.c arm_udelay.c arm_unblocktask.c arm_usestack.c
CMN_CSRCS += arm_vfork.c arm_switchcontext.c arm_saveusercontext.c
CMN_CSRCS += arm_fullcontextrestore.c arm_puts.c arm_tcbinfo.c
CMN_ASRCS += arm_exception.S
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += arm_backtrace_thumb.c
endif
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_initialstate.c
CMN_CSRCS += arm_hardfault.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_svcall.c arm_systemreset.c arm_tcbinfo.c
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
@ -46,26 +38,6 @@ ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# Use of common/arm_etherstub.c is deprecated. The preferred mechanism is to
# use CONFIG_NETDEV_LATEINIT=y to suppress the call to arm_netinitialize() in
# up_initialize(). Then this stub would not be needed.
ifeq ($(CONFIG_NET),y)
ifneq ($(CONFIG_XMC4_ENET),y)
CMN_CSRCS += arm_etherstub.c
endif
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c