STM32XX: Fix Pending Register definition
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@ -188,9 +188,9 @@
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/* Pending register */
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#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Selected trigger request occurred */
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#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
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#define EXTI_IMR_MASK STM32_EXTI_MASK
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#define EXTI_PR_BIT(n) STM32_EXTI_BIT(n) /* 1=Selected trigger request occurred */
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#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
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#define EXTI_PR_MASK STM32_EXTI_MASK
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/* Compatibility Definitions ********************************************************/
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@ -125,9 +125,9 @@
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/* Pending register */
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#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Selected trigger request occurred */
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#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
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#define EXTI_IMR_MASK STM32_EXTI_MASK
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#define EXTI_PR_BIT(n) STM32_EXTI_BIT(n) /* 1=Selected trigger request occurred */
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#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
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#define EXTI_PR_MASK STM32_EXTI_MASK
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#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
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#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_EXTI_H */
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@ -167,13 +167,13 @@
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/* Pending register */
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#define EXTI_IMR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Selected trigger request occurred */
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#define EXTI_IMR1_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
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#define EXTI_IMR1_MASK STM32L4_EXTI1_MASK
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#define EXTI_PR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Selected trigger request occurred */
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#define EXTI_PR1_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
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#define EXTI_PR1_MASK STM32L4_EXTI1_MASK
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#define EXTI_IMR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Selected trigger request occurred */
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#define EXTI_IMR2_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
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#define EXTI_IMR2_MASK STM32L4_EXTI2_MASK
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#define EXTI_PR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Selected trigger request occurred */
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#define EXTI_PR2_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
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#define EXTI_PR2_MASK STM32L4_EXTI2_MASK
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#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_EXTI_H */
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