stm32_dac: add support for HRTIM triggering
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raiden00pl
parent
a5f3a5848d
commit
a5997cb186
@ -142,13 +142,23 @@
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# endif
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#endif
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#if defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG1) || defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG2)
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# define DAC1CH1_HRTIM
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#endif
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#if defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG1) || defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG2)
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# define DAC1CH2_HRTIM
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#endif
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#if defined(CONFIG_STM32_DAC2CH1_HRTIM_TRG3)
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# define DAC2CH1_HRTIM
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#endif
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/* If DMA is selected, then a timer and output frequency must also be
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* provided to support the DMA transfer. The DMA transfer could be
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* supported by and EXTI trigger, but this feature is not currently
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* supported by the driver.
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*/
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#ifdef CONFIG_STM32_DAC1CH1_DMA
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#if defined(CONFIG_STM32_DAC1CH1_DMA) && !defined(DAC1CH1_HRTIM)
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# if !defined(CONFIG_STM32_DAC1CH1_TIMER)
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# warning "A timer number must be specificed in CONFIG_STM32_DAC1CH1_TIMER"
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# undef CONFIG_STM32_DAC1CH1_DMA
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@ -160,7 +170,7 @@
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# endif
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#endif
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#ifdef CONFIG_STM32_DAC1CH2_DMA
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#if defined(CONFIG_STM32_DAC1CH2_DMA) && !defined(DAC1CH2_HRTIM)
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# if !defined(CONFIG_STM32_DAC1CH2_TIMER)
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# warning "A timer number must be specificed in CONFIG_STM32_DAC1CH2_TIMER"
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# undef CONFIG_STM32_DAC1CH2_DMA
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@ -172,7 +182,7 @@
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# endif
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#endif
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#ifdef CONFIG_STM32_DAC2CH1_DMA
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#if defined(CONFIG_STM32_DAC2CH1_DMA) && !defined(DAC2CH1_HRTIM)
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# if !defined(CONFIG_STM32_DAC2CH1_TIMER)
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# warning "A timer number must be specificed in CONFIG_STM32_DAC2CH1_TIMER"
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# undef CONFIG_STM32_DAC2CH1_DMA
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@ -201,7 +211,7 @@
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# define DAC1CH2_DMA_CHAN DMACHAN_DAC1_CH2
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# endif
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# ifdef CONFIG_STM32_DAC2CH1
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# define DAC2CH1_DMA_CHAN DMACHAN_DAC2_CH2
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# define DAC2CH1_DMA_CHAN DMACHAN_DAC2_CH1
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# endif
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# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
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# define HAVE_DMA 1
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@ -224,12 +234,16 @@
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* TSEL SOURCE DEVICES
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* ---- ----------------------- -------------------------------------
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* 000 Timer 6 TRGO event ALL
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* 001 Timer 3 TRGO event STM32 F1 Connectivity Line
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* 001 Timer 3 TRGO event STM32 F1 Connectivity Line and STM32 F3
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* Timer 8 TRGO event Other STM32 F1 and all STM32 F4
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* 010 Timer 7 TRGO event ALL
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* 011 Timer 5 TRGO event ALL
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* Timer 15 TRGO event STM32 F3
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* HRTIM1_DACTRG1 event STM32F33XX (DAC1 only)
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* 100 Timer 2 TRGO event ALL
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* 101 Timer 4 TRGO event ALL
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* HRTIM1_DACTRG2 event STM32F33XX (DAC1 only)
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* HRTIM1_DACTRG3 event STM32F33XX (DAC2 only)
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* 110 EXTI line9 ALL
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* 111 SWTRIG Software control ALL
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*
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@ -245,7 +259,17 @@
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#undef NEED_TIM4
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#ifdef CONFIG_STM32_DAC1CH1_DMA
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# if CONFIG_STM32_DAC1CH1_TIMER == 6
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# if defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG1)
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# ifndef CONFIG_STM32_HRTIM_DAC
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# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH1"
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# endif
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# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_HRT1TRG1
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# elif defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG2)
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# ifndef CONFIG_STM32_HRTIM_DAC
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# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH2"
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# endif
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# define DAC1CH1_TSEL_VALUE DAC_CR_TSEL_HRT1TRG2
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# elif CONFIG_STM32_DAC1CH1_TIMER == 6
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# ifndef CONFIG_STM32_TIM6_DAC
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# error "CONFIG_STM32_TIM6_DAC required for DAC1CH1"
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# endif
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@ -308,7 +332,17 @@
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#endif
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#ifdef CONFIG_STM32_DAC1CH2_DMA
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# if CONFIG_STM32_DAC1CH2_TIMER == 6
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# if defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG1)
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# ifndef CONFIG_STM32_HRTIM_DAC
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# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH2"
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# endif
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# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_HRT1TRG1
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# elif defined(CONFIG_STM32_DAC1CH2_HRTIM_TRG2)
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# ifndef CONFIG_STM32_HRTIM_DAC
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# error "CONFIG_STM32_HRTIM_DAC required for DAC1CH2"
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# endif
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# define DAC1CH2_TSEL_VALUE DAC_CR_TSEL_HRT1TRG2
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# elif CONFIG_STM32_DAC1CH2_TIMER == 6
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# ifndef CONFIG_STM32_TIM6_DAC
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# error "CONFIG_STM32_TIM6_DAC required for DAC1CH2"
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# endif
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@ -365,7 +399,12 @@
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#endif
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#ifdef CONFIG_STM32_DAC2CH1_DMA
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# if CONFIG_STM32_DAC2CH1_TIMER == 6
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# if defined(CONFIG_STM32_DAC2CH1_HRTIM_TRG3)
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# ifndef CONFIG_STM32_HRTIM_DAC
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# error "CONFIG_STM32_HRTIM_DAC required for DAC2CH1"
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# endif
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# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_HRT1TRG3
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# elif CONFIG_STM32_DAC2CH1_TIMER == 6
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# ifndef CONFIG_STM32_TIM6_DAC
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# error "CONFIG_STM32_TIM6_DAC required for DAC2CH1"
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# endif
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@ -421,6 +460,17 @@
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# define DAC2CH1_TSEL_VALUE DAC_CR_TSEL_SW
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#endif
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/*
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* We need index which describes when HRTIM is selected as trigger.
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* It will be used to skip timer configuration where needed.
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*/
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#define TIM_INDEX_HRTIM 255
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#if defined(DAC1_HRTIM) || defined(DAC2_HRTIM) || defined(DAC3_HRTIM)
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# define HAVE_HRTIM
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#endif
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#ifndef CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE
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# define CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE 256
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#endif
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@ -563,10 +613,17 @@ static struct stm32_chan_s g_dac1ch1priv =
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.dmachan = DAC1CH1_DMA_CHAN,
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.buffer_len = CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE,
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.dmabuffer = dac1ch1_buffer,
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# ifdef DAC1CH1_HRTIM
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.timer = TIM_INDEX_HRTIM,
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.tsel = 0,
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.tbase = 0,
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.tfrequency = 0,
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# else
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.timer = CONFIG_STM32_DAC1CH1_TIMER,
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.tsel = DAC1CH1_TSEL_VALUE,
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.tbase = DAC1CH1_TIMER_BASE,
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.tfrequency = CONFIG_STM32_DAC1CH1_TIMER_FREQUENCY,
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# endif
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#endif
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};
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@ -596,10 +653,17 @@ static struct stm32_chan_s g_dac1ch2priv =
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.dmachan = DAC1CH2_DMA_CHAN,
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.buffer_len = CONFIG_STM32_DAC1CH2_DMA_BUFFER_SIZE,
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.dmabuffer = dac1ch2_buffer,
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# ifdef DAC1CH2_HRTIM
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.timer = TIM_INDEX_HRTIM,
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.tsel = 0,
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.tbase = 0,
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.tfrequency = 0,
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# else
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.timer = CONFIG_STM32_DAC1CH2_TIMER,
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.tsel = DAC1CH2_TSEL_VALUE,
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.tbase = DAC1CH2_TIMER_BASE,
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.tfrequency = CONFIG_STM32_DAC1CH2_TIMER_FREQUENCY,
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# endif
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#endif
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};
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@ -632,10 +696,17 @@ static struct stm32_chan_s g_dac2ch1priv =
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.dmachan = DAC2CH1_DMA_CHAN,
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.buffer_len = CONFIG_STM32_DAC2CH1_DMA_BUFFER_SIZE,
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.dmabuffer = dac2ch1_buffer,
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# ifdef DAC2CH1_HRTIM
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.timer = TIM_INDEX_HRTIM,
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.tsel = 0,
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.tbase = 0,
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.tfrequency = 0,
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# else
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.timer = CONFIG_STM32_DAC2CH1_TIMER,
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.tsel = DAC2CH1_TSEL_VALUE,
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.tbase = DAC2CH1_TIMER_BASE,
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.tfrequency = CONFIG_STM32_DAC2CH1_TIMER_FREQUENCY,
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# endif
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#endif
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};
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@ -946,10 +1017,13 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
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dac_txdone(dev);
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}
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/* Reset counters (generate an update) */
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/* Reset counters (generate an update). Only when timer is not HRTIM */
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#ifdef HAVE_DMA
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tim_modifyreg(chan, STM32_BTIM_EGR_OFFSET, 0, ATIM_EGR_UG);
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if (chan->timer != TIM_INDEX_HRTIM)
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{
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tim_modifyreg(chan, STM32_BTIM_EGR_OFFSET, 0, ATIM_EGR_UG);
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}
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#endif
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return OK;
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}
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@ -997,6 +1071,17 @@ static int dac_timinit(FAR struct stm32_chan_s *chan)
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uint32_t regaddr;
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uint32_t setbits;
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/* Do nothing if HRTIM is selected as trigger.
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* All necessary configuration is done in the HRTIM driver.
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*/
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#ifdef HAVE_HRTIM
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if (chan->timer == TIM_INDEX_HRTIM)
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{
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return OK;
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}
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#endif
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/* Configure the time base: Timer period, prescaler, clock division,
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* counter mode (up).
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*/
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