sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

STM32L4: add GPIO_PORTI definition

Browse Source 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
This commit is contained in:
Juha Niskanen 2017-05-02 12:27:43 +03:00 committed by Gregory Nutt
parent 0eb14e9baa
commit a59b7bc932
5 changed files with 25 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/include/stm32l4/chip.h
View File

@ -108,8 +108,12 @@
# define STM32L4_NSAI 2 /* SAI1-2 */
# define STM32L4_NSDMMC 1 /* SDMMC interface */
# define STM32L4_NDMA 2 /* DMA1-2 */
#if defined(CONFIG_STM32L4_STM32L496XX)
# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */
#else
# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
# define STM32L4_NADC 3 /* 12-bit ADC1-3, 24 channels (except V series) */
#endif
# define STM32L4_NADC 3 /* 12-bit ADC1-3, upto 24 channels */
# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
# define STM32L4_NCRC 1 /* CRC */
# define STM32L4_NCOMP 2 /* Comparators */

13
arch/arm/src/stm32l4/chip/stm32l4x6xx_gpio.h
View File

@ -166,6 +166,19 @@
# define STM32L4_GPIOH_AFRH (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRH_OFFSET)
#endif
#if STM32L4_NPORTS > 8
# define STM32L4_GPIOI_MODER (STM32L4_GPIOI_BASE+STM32L4_GPIO_MODER_OFFSET)
# define STM32L4_GPIOI_OTYPER (STM32L4_GPIOI_BASE+STM32L4_GPIO_OTYPER_OFFSET)
# define STM32L4_GPIOI_OSPEED (STM32L4_GPIOI_BASE+STM32L4_GPIO_OSPEED_OFFSET)
# define STM32L4_GPIOI_PUPDR (STM32L4_GPIOI_BASE+STM32L4_GPIO_PUPDR_OFFSET)
# define STM32L4_GPIOI_IDR (STM32L4_GPIOI_BASE+STM32L4_GPIO_IDR_OFFSET)
# define STM32L4_GPIOI_ODR (STM32L4_GPIOI_BASE+STM32L4_GPIO_ODR_OFFSET)
# define STM32L4_GPIOI_BSRR (STM32L4_GPIOI_BASE+STM32L4_GPIO_BSRR_OFFSET)
# define STM32L4_GPIOI_LCKR (STM32L4_GPIOI_BASE+STM32L4_GPIO_LCKR_OFFSET)
# define STM32L4_GPIOI_AFRL (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRL_OFFSET)
# define STM32L4_GPIOI_AFRH (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRH_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
/* GPIO port mode register */

3
arch/arm/src/stm32l4/stm32l4_gpio.c
View File

@ -88,6 +88,9 @@ const uint32_t g_gpiobase[STM32L4_NPORTS] =
#if STM32L4_NPORTS > 7
STM32L4_GPIOH_BASE,
#endif
#if STM32L4_NPORTS > 8
STM32L4_GPIOI_BASE,
#endif
};
/****************************************************************************

1
arch/arm/src/stm32l4/stm32l4_gpio.h
View File

@ -212,6 +212,7 @@
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
# define GPIO_PORTI (8 << GPIO_PORT_SHIFT) /* GPIOI */
/* This identifies the bit in the port:
*

3
arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
View File

@ -210,6 +210,9 @@ static inline void rcc_enableahb2(void)
#endif
#if STM32L4_NPORTS > 7
| RCC_AHB2ENR_GPIOHEN
#endif
#if STM32L4_NPORTS > 8
| RCC_AHB2ENR_GPIOIEN
#endif
);
#endif