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PIC32 debug fixes

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4095 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2011-11-17 12:36:40 +00:00
parent 93d0aa3a6e
commit a5b16d9f0d
4 changed files with 28 additions and 23 deletions
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38
arch/mips/src/mips32/up_initialstate.c
View File

@ -54,20 +54,6 @@
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_SUPPRESS_INTERRUPTS
/* Enable only software interrupts */
# define INITIAL_STATUS (CP0_STATUS_IE | CP0_STATUS_EXL | CP0_STATUS_IM_SWINTS)
#else
/* Enable all interrupts */
# define INITIAL_STATUS (CP0_STATUS_IE | CP0_STATUS_EXL | CP0_STATUS_IM_ALL)
#endif
/****************************************************************************
* Private Data
****************************************************************************/
@ -97,6 +83,7 @@
void up_initial_state(_TCB *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
uint32_t regval;
/* Initialize the initial exception register context structure */
@ -133,8 +120,27 @@ void up_initial_state(_TCB *tcb)
# warning "Missing logic"
#endif
/* Enable or disable interrupts, based on user configuration */
/* Set the initial value of the status register. It will be the same
* as the current status register with some changes:
*
* 1. Make sure the IE is set (it should be)
* 2. Clear the BEV bit (it should be)
* 3. Set the interrupt mask bits (depending on configuration)
* 4. Set the EXL bit
*
* The EXL bit is set because this new STATUS register will be
* instantiated in kernel mode inside of an interrupt handler. EXL
* will be automatically cleared by the eret instruction.
*/
xcp->regs[REG_STATUS] = INITIAL_STATUS;
regval = cp0_getstatus();
#ifdef CONFIG_SUPPRESS_INTERRUPTS
regval &= ~(CP0_STATUS_IM_ALL | CP0_STATUS_BEV);
regval |= (CP0_STATUS_IE | CP0_STATUS_EXL | CP0_STATUS_IM_SWINTS);
#else
regval &= ~(CP0_STATUS_BEV);
regval |= (CP0_STATUS_IE | CP0_STATUS_EXL | CP0_STATUS_IM_ALL);
#endif
xcp->regs[REG_STATUS] = regval;
}

10
arch/mips/src/mips32/up_swint0.c
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@ -103,21 +103,21 @@ static void up_registerdump(uint32_t *regs)
{
swidbg("MFLO:%08x MFHI:%08x EPC:%08x STATUS:%08x\n",
regs[REG_MFLO], regs[REG_MFHI], regs[REG_EPC], regs[REG_STATUS]);
swidbg("AT:%08x V0:$08x V1:%08x A0:%08x A1:%08x A2:%08x A3:%08x\n",
swidbg("AT:%08x V0:%08x V1:%08x A0:%08x A1:%08x A2:%08x A3:%08x\n",
regs[REG_AT], regs[REG_V0], regs[REG_V1], regs[REG_A0],
regs[REG_A1], regs[REG_A2], regs[REG_A3]);
swidbg("T0:%08x T1:$08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x T7:%08x\n",
swidbg("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x T7:%08x\n",
regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3],
regs[REG_T4], regs[REG_T5], regs[REG_T6], regs[REG_T7]);
swidbg("S0:%08x S1:$08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n",
swidbg("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n",
regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3],
regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]);
#ifdef MIPS32_SAVE_GP
swidbg("T8:%08x T9:$08x GP:%08x SP:%08x FP:%08x RA:%08x\n",
swidbg("T8:%08x T9:%08x GP:%08x SP:%08x FP:%08x RA:%08x\n",
regs[REG_T8], regs[REG_T9], regs[REG_GP], regs[REG_SP],
regs[REG_FP], regs[REG_RA]);
#else
swidbg("T8:%08x T9:$08x SP:%08x FP:%08x RA:%08x\n",
swidbg("T8:%08x T9:%08x SP:%08x FP:%08x RA:%08x\n",
regs[REG_T8], regs[REG_T9], regs[REG_SP], regs[REG_FP],
regs[REG_RA]);
#endif

2
arch/mips/src/pic32mx/excptmacros.h
View File

@ -142,7 +142,7 @@
* Bit 4: Operating mode == USER
*/
ins k1, \tmp, CP0_STATUS_IPL_SHIFT, 6
ins k1, k0, CP0_STATUS_IPL_SHIFT, 6
ins k1, zero, 1, 4
/* And Enable interrupts */

1
arch/mips/src/pic32mx/pic32mx-irq.c
View File

@ -131,7 +131,6 @@ void up_irqinitialize(void)
/* Clear the EXL bit in the STATUS register */
regval = cp0_getstatus();
//regval &= ~CP0_STATUS_BEV;
regval &= ~CP0_STATUS_EXL;
cp0_putstatus(regval);