Add injected channel support.
This commit is contained in:
Daniel P. Carvalho
Alan Carvalho de Assis
parent
5adcdcdc15
commit
a5d340a5df
@ -3603,26 +3603,26 @@ config STM32L4_TIM1_ADC
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channel it is assigned to.
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choice
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prompt "Select TIM1 ADC channel"
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prompt "Select ADC to trigger"
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default STM32L4_TIM1_ADC1
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depends on STM32L4_TIM1_ADC
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config STM32L4_TIM1_ADC1
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bool "TIM1 ADC channel 1"
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bool "TIM1 trigger ADC1"
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depends on STM32L4_ADC1
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select STM32L4_HAVE_ADC1_TIMER
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---help---
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Reserve TIM1 to trigger ADC1
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config STM32L4_TIM1_ADC2
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bool "TIM1 ADC channel 2"
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bool "TIM1 trigger ADC2"
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depends on STM32L4_ADC2
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select STM32L4_HAVE_ADC2_TIMER
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---help---
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Reserve TIM1 to trigger ADC2
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config STM32L4_TIM1_ADC3
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bool "TIM1 ADC channel 3"
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bool "TIM1 trigger ADC3"
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depends on STM32L4_ADC3
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select STM32L4_HAVE_ADC3_TIMER
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---help---
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@ -3630,6 +3630,14 @@ config STM32L4_TIM1_ADC3
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endchoice
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config STM32L4_TIM1_ADC_CHAN
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int "TIM1 channel"
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default 1
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range 1 4
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depends on STM32L4_TIM1_ADC
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---help---
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Values 1:CC1 2:CC2 3:CC3 4:CC4
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config STM32L4_TIM2_ADC
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bool "TIM2 ADC"
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default n
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@ -3645,26 +3653,26 @@ config STM32L4_TIM2_ADC
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channel it is assigned to.
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choice
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prompt "Select TIM2 ADC channel"
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prompt "Select ADC to trigger"
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default STM32L4_TIM2_ADC1
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depends on STM32L4_TIM2_ADC
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config STM32L4_TIM2_ADC1
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bool "TIM2 ADC channel 1"
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bool "TIM2 trigger ADC1"
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depends on STM32L4_ADC1
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select STM32L4_HAVE_ADC1_TIMER
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---help---
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Reserve TIM2 to trigger ADC1
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config STM32L4_TIM2_ADC2
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bool "TIM2 ADC channel 2"
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bool "TIM2 trigger ADC2"
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depends on STM32L4_ADC2
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select STM32L4_HAVE_ADC2_TIMER
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---help---
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Reserve TIM2 to trigger ADC2
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config STM32L4_TIM2_ADC3
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bool "TIM2 ADC channel 3"
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bool "TIM2 trigger ADC3"
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depends on STM32L4_ADC3
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select STM32L4_HAVE_ADC3_TIMER
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---help---
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@ -3672,6 +3680,14 @@ config STM32L4_TIM2_ADC3
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endchoice
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config STM32L4_TIM2_ADC_CHAN
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int "TIM2 channel"
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default 1
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range 1 4
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depends on STM32L4_TIM2_ADC
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---help---
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Values 1:CC1 2:CC2 3:CC3 4:CC4
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config STM32L4_TIM3_ADC
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bool "TIM3 ADC"
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default n
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@ -3687,26 +3703,26 @@ config STM32L4_TIM3_ADC
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channel it is assigned to.
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choice
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prompt "Select TIM3 ADC channel"
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prompt "Select ADC to trigger"
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default STM32L4_TIM3_ADC1
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depends on STM32L4_TIM3_ADC
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config STM32L4_TIM3_ADC1
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bool "TIM3 ADC channel 1"
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bool "TIM3 trigger ADC1"
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depends on STM32L4_ADC1
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select STM32L4_HAVE_ADC1_TIMER
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---help---
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Reserve TIM3 to trigger ADC1
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config STM32L4_TIM3_ADC2
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bool "TIM3 ADC channel 2"
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bool "TIM3 trigger ADC2"
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depends on STM32L4_ADC2
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select STM32L4_HAVE_ADC2_TIMER
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---help---
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Reserve TIM3 to trigger ADC2
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config STM32L4_TIM3_ADC3
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bool "TIM3 ADC channel 3"
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bool "TIM3 trigger ADC3"
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depends on STM32L4_ADC3
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select STM32L4_HAVE_ADC3_TIMER
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---help---
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@ -3714,6 +3730,14 @@ config STM32L4_TIM3_ADC3
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endchoice
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config STM32L4_TIM3_ADC_CHAN
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int "TIM3 channel"
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default 1
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range 1 4
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depends on STM32L4_TIM3_ADC
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---help---
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Values 1:CC2 2:CC2 3:CC3 4:CC4
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config STM32L4_TIM4_ADC
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bool "TIM4 ADC"
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default n
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@ -3729,26 +3753,26 @@ config STM32L4_TIM4_ADC
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channel it is assigned to.
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choice
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prompt "Select TIM4 ADC channel"
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prompt "Select ADC to trigger"
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default STM32L4_TIM4_ADC1
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depends on STM32L4_TIM4_ADC
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config STM32L4_TIM4_ADC1
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bool "TIM4 ADC channel 1"
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bool "TIM4 trigger ADC1"
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depends on STM32L4_ADC1
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select STM32L4_HAVE_ADC1_TIMER
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---help---
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Reserve TIM4 to trigger ADC1
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config STM32L4_TIM4_ADC2
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bool "TIM4 ADC channel 2"
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bool "TIM4 trigger ADC2"
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depends on STM32L4_ADC2
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select STM32L4_HAVE_ADC2_TIMER
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---help---
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Reserve TIM4 to trigger ADC2
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config STM32L4_TIM4_ADC3
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bool "TIM4 ADC channel 3"
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bool "TIM4 trigger ADC3"
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depends on STM32L4_ADC3
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select STM32L4_HAVE_ADC3_TIMER
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---help---
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@ -3756,6 +3780,14 @@ config STM32L4_TIM4_ADC3
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endchoice
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config STM32L4_TIM4_ADC_CHAN
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int "TIM4 channel"
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default 1
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range 1 4
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depends on STM32L4_TIM4_ADC
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---help---
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Values 1:CC2 2:CC2 3:CC3 4:CC4
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config STM32L4_TIM6_ADC
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bool "TIM6 ADC"
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default n
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@ -3771,26 +3803,26 @@ config STM32L4_TIM6_ADC
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channel it is assigned to.
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choice
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prompt "Select TIM6 ADC channel"
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prompt "Select ADC to trigger"
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default STM32L4_TIM6_ADC1
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depends on STM32L4_TIM6_ADC
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config STM32L4_TIM6_ADC1
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bool "TIM6 ADC channel 1"
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bool "TIM6 trigger ADC1"
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depends on STM32L4_ADC1
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select STM32L4_HAVE_ADC1_TIMER
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---help---
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Reserve TIM6 to trigger ADC1
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config STM32L4_TIM6_ADC2
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bool "TIM6 ADC channel 2"
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bool "TIM6 trigger ADC2"
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depends on STM32L4_ADC2
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select STM32L4_HAVE_ADC2_TIMER
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---help---
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Reserve TIM6 to trigger ADC2
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config STM32L4_TIM6_ADC3
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bool "TIM6 ADC channel 3"
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bool "TIM6 trigger ADC3"
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depends on STM32L4_ADC3
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select STM32L4_HAVE_ADC3_TIMER
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---help---
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@ -3798,6 +3830,14 @@ config STM32L4_TIM6_ADC3
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endchoice
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config STM32L4_TIM6_ADC_CHAN
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int "TIM6 channel"
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default 1
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range 1 4
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depends on STM32L4_TIM6_ADC
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---help---
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Values 1:CC2 2:CC2 3:CC3 4:CC4
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config STM32L4_TIM8_ADC
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bool "TIM8 ADC"
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default n
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@ -3813,26 +3853,26 @@ config STM32L4_TIM8_ADC
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channel it is assigned to.
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choice
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prompt "Select TIM8 ADC channel"
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prompt "Select ADC to trigger"
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default STM32L4_TIM8_ADC1
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depends on STM32L4_TIM8_ADC
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config STM32L4_TIM8_ADC1
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bool "TIM8 ADC channel 1"
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bool "TIM8 trigger ADC1"
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depends on STM32L4_ADC1
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select STM32L4_HAVE_ADC1_TIMER
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---help---
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Reserve TIM8 to trigger ADC1
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config STM32L4_TIM8_ADC2
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bool "TIM8 ADC channel 2"
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bool "TIM8 trigger ADC2"
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depends on STM32L4_ADC2
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select STM32L4_HAVE_ADC2_TIMER
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---help---
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Reserve TIM8 to trigger ADC2
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config STM32L4_TIM8_ADC3
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bool "TIM8 ADC channel 3"
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bool "TIM8 trigger ADC3"
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depends on STM32L4_ADC3
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select STM32L4_HAVE_ADC3_TIMER
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---help---
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@ -3840,6 +3880,14 @@ config STM32L4_TIM8_ADC3
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endchoice
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config STM32L4_TIM8_ADC_CHAN
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int "TIM8 channel"
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default 1
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range 1 4
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depends on STM32L4_TIM8_ADC
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---help---
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Values 1:CC2 2:CC2 3:CC3 4:CC4
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config STM32L4_TIM15_ADC
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bool "TIM15 ADC"
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default n
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@ -3855,26 +3903,26 @@ config STM32L4_TIM15_ADC
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channel it is assigned to.
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choice
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prompt "Select TIM15 ADC channel"
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prompt "Select ADC to trigger"
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default STM32L4_TIM15_ADC1
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depends on STM32L4_TIM15_ADC
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config STM32L4_TIM15_ADC1
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bool "TIM15 ADC channel 1"
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bool "TIM15 trigger ADC1"
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depends on STM32L4_ADC1
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select STM32L4_HAVE_ADC1_TIMER
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---help---
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Reserve TIM15 to trigger ADC1
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config STM32L4_TIM15_ADC2
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bool "TIM15 ADC channel 2"
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bool "TIM15 trigger ADC2"
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depends on STM32L4_ADC2
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select STM32L4_HAVE_ADC2_TIMER
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---help---
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Reserve TIM15 to trigger ADC2
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config STM32L4_TIM15_ADC3
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bool "TIM15 ADC channel 3"
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bool "TIM15 trigger ADC3"
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depends on STM32L4_ADC3
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select STM32L4_HAVE_ADC3_TIMER
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---help---
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@ -3882,6 +3930,14 @@ config STM32L4_TIM15_ADC3
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endchoice
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config STM32L4_TIM15_ADC_CHAN
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int "TIM15 channel"
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default 1
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range 1 4
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depends on STM32L4_TIM15_ADC
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---help---
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Values 1:CC2 2:CC2 3:CC3 4:CC4
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config STM32L4_HAVE_ADC1_TIMER
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bool
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@ -3898,14 +3954,6 @@ config STM32L4_ADC1_SAMPLE_FREQUENCY
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---help---
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ADC1 sampling frequency. Default: 100Hz
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config STM32L4_ADC1_TIMTRIG
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int "ADC1 Timer Trigger"
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default 0
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range 0 4
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depends on STM32L4_HAVE_ADC1_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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config STM32L4_ADC2_SAMPLE_FREQUENCY
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int "ADC2 Sampling Frequency"
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default 100
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@ -3913,14 +3961,6 @@ config STM32L4_ADC2_SAMPLE_FREQUENCY
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---help---
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ADC2 sampling frequency. Default: 100Hz
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config STM32L4_ADC2_TIMTRIG
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int "ADC2 Timer Trigger"
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default 0
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range 0 4
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depends on STM32L4_HAVE_ADC2_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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config STM32L4_ADC3_SAMPLE_FREQUENCY
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int "ADC3 Sampling Frequency"
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default 100
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@ -3928,14 +3968,6 @@ config STM32L4_ADC3_SAMPLE_FREQUENCY
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---help---
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ADC3 sampling frequency. Default: 100Hz
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config STM32L4_ADC3_TIMTRIG
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int "ADC3 Timer Trigger"
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default 0
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range 0 4
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depends on STM32L4_HAVE_ADC3_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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config STM32L4_TIM1_DAC
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bool "TIM1 DAC"
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default n
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@ -5150,6 +5182,94 @@ config STM32L4_ADC3_OUTPUT_DFSDM
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---help---
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Route ADC3 output directly to DFSDM parallel inputs.
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menu "STM32L4 ADCx triggering Configuration"
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config STM32L4_ADC1_TIMTRIG
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int "ADC1 regular channel trigger"
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default 0
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range 0 4
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depends on STM32L4_HAVE_ADC1_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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config STM32L4_ADC2_TIMTRIG
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int "ADC2 Timer Trigger"
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default 0
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range 0 4
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depends on STM32L4_HAVE_ADC2_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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config STM32L4_ADC3_TIMTRIG
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int "ADC3 Timer Trigger"
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default 0
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range 0 4
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depends on STM32L4_HAVE_ADC3_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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config STM32L4_ADC1_INJ_CHAN
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int "ADC1 configured injected channels"
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depends on STM32L4_ADC1
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range 0 4
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default 0
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---help---
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Number of configured ADC1 injected channels.
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config STM32L4_ADC2_INJ_CHAN
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int "ADC2 configured injected channels"
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depends on STM32L4_ADC2
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range 0 4
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default 0
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---help---
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Number of configured ADC2 injected channels.
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config STM32L4_ADC3_INJ_CHAN
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int "ADC3 configured injected channels"
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depends on STM32L4_ADC3
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range 0 4
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default 0
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---help---
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Number of configured ADC3 injected channels.
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if STM32L4_ADC1_INJ_CHAN > 0
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config STM32L4_ADC1_JTIMTRIG
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int "ADC1 external trigger for injected channels"
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default 0
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range 0 5
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depends on STM32L4_HAVE_ADC1_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2
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endif
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if STM32L4_ADC2_INJ_CHAN > 0
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config STM32L4_ADC2_JTIMTRIG
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int "ADC2 external trigger for injected channels"
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default 0
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range 0 5
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depends on STM32L4_HAVE_ADC2_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2
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endif
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if STM32L4_ADC3_INJ_CHAN > 0
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config STM32L4_ADC3_JTIMTRIG
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int "ADC3 external trigger for injected channels"
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default 0
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range 0 5
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depends on STM32L4_HAVE_ADC3_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2
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endif
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endmenu #STM32L4 ADCx triggering Configuration
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endmenu
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menu "DAC Configuration"
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@ -50,8 +50,9 @@
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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/* Register Offsets for each ADC (ADC1-3). At offset 0x0000 for master and offset 0x0100
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* for slave.
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/* Register Offsets for each ADC (ADC1-3). At offset 0x0000 for master and offset
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* 0x0100 for slave.
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*/
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#define STM32L4_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */
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@ -187,6 +188,7 @@
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#endif
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/* Register Bitfield Definitions ****************************************************/
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/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */
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#define ADC_INT_ADRDY (1 << 0) /* Bit 0: ADC ready */
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@ -223,51 +225,53 @@
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#define ADC_CFGR_DFSDMCFG (1 << 2) /* Bit 2: DFSDM mode configuration */
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#define ADC_CFGR_RES_SHIFT (3) /* Bits 3-4: Data resolution */
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#define ADC_CFGR_RES_MASK (3 << ADC_CFGR_RES_SHIFT)
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# define ADC_CFGR_RES_12BIT (0 << ADC_CFGR_RES_SHIFT) /* 12-bit resolution */
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# define ADC_CFGR_RES_10BIT (1 << ADC_CFGR_RES_SHIFT) /* 10-bit resolution */
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# define ADC_CFGR_RES_8BIT (2 << ADC_CFGR_RES_SHIFT) /* 8-bit resolution */
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# define ADC_CFGR_RES_6BIT (3 << ADC_CFGR_RES_SHIFT) /* 6-bit resolution */
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#define ADC_CFGR_ALIGN (1 << 5) /* Bit 5: Data Alignment */
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#define ADC_CFGR_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */
|
||||
# define ADC_CFGR_RES_12BIT (0 << ADC_CFGR_RES_SHIFT) /* 12-bit resolution */
|
||||
# define ADC_CFGR_RES_10BIT (1 << ADC_CFGR_RES_SHIFT) /* 10-bit resolution */
|
||||
# define ADC_CFGR_RES_8BIT (2 << ADC_CFGR_RES_SHIFT) /* 8-bit resolution */
|
||||
# define ADC_CFGR_RES_6BIT (3 << ADC_CFGR_RES_SHIFT) /* 6-bit resolution */
|
||||
#define ADC_CFGR_ALIGN (1 << 5) /* Bit 5: Data Alignment */
|
||||
#define ADC_CFGR_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */
|
||||
#define ADC_CFGR_EXTSEL_MASK (15 << ADC_CFGR_EXTSEL_SHIFT)
|
||||
# define ADC_CFGR_EXTSEL(event) ((event) << ADC_CFGR_EXTSEL_SHIFT) /* Event = 0..15 */
|
||||
# define ADC_CFGR_EXTSEL_T1CC1 (0x0 << ADC_CFGR_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */
|
||||
# define ADC_CFGR_EXTSEL_T1CC2 (0x01 << ADC_CFGR_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */
|
||||
# define ADC_CFGR_EXTSEL_T1CC3 (0x02 << ADC_CFGR_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */
|
||||
# define ADC_CFGR_EXTSEL_T2CC2 (0x03 << ADC_CFGR_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
|
||||
# define ADC_CFGR_EXTSEL_T3TRGO (0x04 << ADC_CFGR_EXTSEL_SHIFT) /* 0100: Timer 3 TRGO event */
|
||||
# define ADC_CFGR_EXTSEL(event) ((event) << ADC_CFGR_EXTSEL_SHIFT)/* Event = 0..15 */
|
||||
# define ADC_CFGR_EXTSEL_T1CC1 (0x0 << ADC_CFGR_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */
|
||||
# define ADC_CFGR_EXTSEL_T1CC2 (0x01 << ADC_CFGR_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */
|
||||
# define ADC_CFGR_EXTSEL_T1CC3 (0x02 << ADC_CFGR_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */
|
||||
# define ADC_CFGR_EXTSEL_T2CC2 (0x03 << ADC_CFGR_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
|
||||
# define ADC_CFGR_EXTSEL_T3TRGO (0x04 << ADC_CFGR_EXTSEL_SHIFT) /* 0100: Timer 3 TRGO event */
|
||||
# if !defined(CONFIG_STM32L4_STM32L4X3)
|
||||
# define ADC_CFGR_EXTSEL_T4CC4 (0x05 << ADC_CFGR_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */
|
||||
# define ADC_CFGR_EXTSEL_T4CC4 (0x05 << ADC_CFGR_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */
|
||||
# endif
|
||||
# define ADC_CFGR_EXTSEL_EXTI11 (0x06 << ADC_CFGR_EXTSEL_SHIFT) /* 0110: EXTI line 11 */
|
||||
# define ADC_CFGR_EXTSEL_EXTI11 (0x06 << ADC_CFGR_EXTSEL_SHIFT) /* 0110: EXTI line 11 */
|
||||
# if !defined(CONFIG_STM32L4_STM32L4X3)
|
||||
# define ADC_CFGR_EXTSEL_T8TRGO (0x07 << ADC_CFGR_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */
|
||||
# define ADC_CFGR_EXTSEL_T8TRGO2 (0x08 << ADC_CFGR_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */
|
||||
# define ADC_CFGR_EXTSEL_T8TRGO (0x07 << ADC_CFGR_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */
|
||||
# define ADC_CFGR_EXTSEL_T8TRGO2 (0x08 << ADC_CFGR_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */
|
||||
# endif
|
||||
# define ADC_CFGR_EXTSEL_T1TRGO (0x09 << ADC_CFGR_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */
|
||||
# define ADC_CFGR_EXTSEL_T1TRGO2 (0x0a << ADC_CFGR_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */
|
||||
# define ADC_CFGR_EXTSEL_T2TRGO (0x0b << ADC_CFGR_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */
|
||||
# define ADC_CFGR_EXTSEL_T1TRGO (0x09 << ADC_CFGR_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */
|
||||
# define ADC_CFGR_EXTSEL_T1TRGO2 (0x0a << ADC_CFGR_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */
|
||||
# define ADC_CFGR_EXTSEL_T2TRGO (0x0b << ADC_CFGR_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */
|
||||
# if !defined(CONFIG_STM32L4_STM32L4X3)
|
||||
# define ADC_CFGR_EXTSEL_T4TRGO (0x0c << ADC_CFGR_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */
|
||||
# define ADC_CFGR_EXTSEL_T4TRGO (0x0c << ADC_CFGR_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */
|
||||
# endif
|
||||
# define ADC_CFGR_EXTSEL_T6TRGO (0x0d << ADC_CFGR_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */
|
||||
# define ADC_CFGR_EXTSEL_T15TRGO (0x0e << ADC_CFGR_EXTSEL_SHIFT) /* 1110: Timer 15 TRGO event */
|
||||
# define ADC_CFGR_EXTSEL_T6TRGO (0x0d << ADC_CFGR_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */
|
||||
# define ADC_CFGR_EXTSEL_T15TRGO (0x0e << ADC_CFGR_EXTSEL_SHIFT) /* 1110: Timer 15 TRGO event */
|
||||
# if !defined(CONFIG_STM32L4_STM32L4X3)
|
||||
# define ADC_CFGR_EXTSEL_T3CC4 (0x0f << ADC_CFGR_EXTSEL_SHIFT) /* 1111: Timer 3 CC4 event */
|
||||
# define ADC_CFGR_EXTSEL_T3CC4 (0x0f << ADC_CFGR_EXTSEL_SHIFT) /* 1111: Timer 3 CC4 event */
|
||||
# endif
|
||||
#define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */
|
||||
#define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */
|
||||
#define ADC_CFGR_EXTEN_MASK (3 << ADC_CFGR_EXTEN_SHIFT)
|
||||
# define ADC_CFGR_EXTEN_NONE (0 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */
|
||||
# define ADC_CFGR_EXTEN_RISING (1 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the rising edge */
|
||||
# define ADC_CFGR_EXTEN_FALLING (2 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the falling edge */
|
||||
# define ADC_CFGR_EXTEN_BOTH (3 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on both edges */
|
||||
#define ADC_CFGR_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */
|
||||
#define ADC_CFGR_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */
|
||||
#define ADC_CFGR_AUTDLY (1 << 14) /* Bit 14: Delayed conversion mode */
|
||||
#define ADC_CFGR_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */
|
||||
#define ADC_CFGR_DISCNUM_SHIFT (17) /* Bits 17-19: Discontinuous mode channel count */
|
||||
# define ADC_CFGR_EXTEN_NONE (0 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */
|
||||
# define ADC_CFGR_EXTEN_RISING (1 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the rising edge */
|
||||
# define ADC_CFGR_EXTEN_FALLING (2 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the falling edge */
|
||||
# define ADC_CFGR_EXTEN_BOTH (3 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on both edges */
|
||||
#define ADC_CFGR_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */
|
||||
#define ADC_CFGR_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */
|
||||
#define ADC_CFGR_AUTDLY (1 << 14) /* Bit 14: Delayed conversion mode */
|
||||
#define ADC_CFGR_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */
|
||||
#define ADC_CFGR_DISCNUM_SHIFT (17) /* Bits 17-19: Discontinuous mode channel count */
|
||||
#define ADC_CFGR_DISCNUM_MASK (7 << ADC_CFGR_DISCNUM_SHIFT)
|
||||
# define ADC_CFGR_DISCNUM(n) (((n) - 1) << ADC_CFGR_DISCNUM_SHIFT) /* n = 1..8 channels */
|
||||
# define ADC_CFGR_DISCNUM(n) (((n) - 1) << ADC_CFGR_DISCNUM_SHIFT)
|
||||
/* n = 1..8 channels */
|
||||
|
||||
#define ADC_CFGR_JDISCEN (1 << 20) /* Bit 20: Discontinuous mode on injected channels */
|
||||
#define ADC_CFGR_JQM (1 << 21) /* Bit 21: JSQR queue mode */
|
||||
#define ADC_CFGR_AWD1SGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */
|
||||
@ -293,11 +297,12 @@
|
||||
# define ADC_CFGR2_OVSR_64X (5 << ADC_CFGR2_OVSR_SHIFT) /* 64X oversampling */
|
||||
# define ADC_CFGR2_OVSR_128X (6 << ADC_CFGR2_OVSR_SHIFT) /* 128X oversampling */
|
||||
# define ADC_CFGR2_OVSR_256X (7 << ADC_CFGR2_OVSR_SHIFT) /* 256X oversampling */
|
||||
#define ADC_CFGR2_OVSS_SHIFT (5) /* Bits 5-8: Oversampling shift */
|
||||
#define ADC_CFGR2_OVSS_SHIFT (5) /* Bits 5-8: Oversampling shift */
|
||||
#define ADC_CFGR2_OVSS_MASK (0xf << ADC_CFGR2_OVSS_SHIFT)
|
||||
# define ADC_CFGR2_OVSS(value) ((value) << ADC_CFGR2_OVSS_SHIFT) /* Value = 0..8 */
|
||||
#define ADC_CFGR2_TROVS (1 << 9) /* Bit 9: Triggered Regular Oversampling */
|
||||
#define ADC_CFGR2_ROVSM (1 << 10) /* Bit 10: Regular Oversampling mode */
|
||||
# define ADC_CFGR2_OVSS(value) ((value) << ADC_CFGR2_OVSS_SHIFT)
|
||||
/* Value = 0..8 */
|
||||
#define ADC_CFGR2_TROVS (1 << 9) /* Bit 9: Triggered Regular Oversampling */
|
||||
#define ADC_CFGR2_ROVSM (1 << 10) /* Bit 10: Regular Oversampling mode */
|
||||
|
||||
/* ADC sample time register 1 */
|
||||
|
||||
@ -446,30 +451,49 @@
|
||||
|
||||
/* ADC injected sequence register */
|
||||
|
||||
#define ADC_JSQR_JL_SHIFT (0) /* Bits 0-1: Injected Sequence length */
|
||||
#define ADC_JSQR_JL_SHIFT (0) /* Bits 0-1: Injected Sequence length */
|
||||
#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT)
|
||||
# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */
|
||||
#define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */
|
||||
# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT)
|
||||
/* n=1..4 */
|
||||
#define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */
|
||||
#define ADC_JSQR_JEXTSEL_MASK (15 << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
# define ADC_JSQR_JEXTSEL(event) ((event) << ADC_JSQR_JEXTSEL_SHIFT) /* Event = 0..15 */
|
||||
#define ADC_JSQR_JEXTEN_SHIFT (6) /* Bits 6-7: External trigger selection for injected greoup */
|
||||
# define ADC_JSQR_JEXTSEL(event) ((event) << ADC_JSQR_JEXTSEL_SHIFT)
|
||||
/* Event = 0..15 */
|
||||
# define ADC_JEXTSEL_T1TRGO ADC_JSQR_JEXTSEL(0) /* 0000 TIM1_TRGO */
|
||||
# define ADC_JEXTSEL_T1CC4 ADC_JSQR_JEXTSEL(1) /* 0001 TIM1_CH4 */
|
||||
# define ADC_JEXTSEL_T2TRGO ADC_JSQR_JEXTSEL(2) /* 0010 TIM2_TRGO */
|
||||
# define ADC_JEXTSEL_T2CC1 ADC_JSQR_JEXTSEL(3) /* 0011 TIM2_CH1 */
|
||||
# define ADC_JEXTSEL_T3CC4 ADC_JSQR_JEXTSEL(4) /* 0100 TIM3_CH4 */
|
||||
# define ADC_JEXTSEL_T4TRGO ADC_JSQR_JEXTSEL(5) /* 0101 TIM4_TRGO */
|
||||
# define ADC_JEXTSEL_EXTI15 ADC_JSQR_JEXTSEL(6) /* 0110 EXTI line 15 */
|
||||
# define ADC_JEXTSEL_T8CC4 ADC_JSQR_JEXTSEL(7) /* 0111 TIM8_CH4 */
|
||||
# define ADC_JEXTSEL_T1TRGO2 ADC_JSQR_JEXTSEL(8) /* 1000 TIM1_TRGO2 */
|
||||
# define ADC_JEXTSEL_T8TRGO ADC_JSQR_JEXTSEL(9) /* 1001 TIM8_TRGO */
|
||||
# define ADC_JEXTSEL_T8TRGO2 ADC_JSQR_JEXTSEL(10) /* 1010 TIM8_TRG02 */
|
||||
# define ADC_JEXTSEL_T3CC3 ADC_JSQR_JEXTSEL(11) /* 1011 TIM3_CH3 */
|
||||
# define ADC_JEXTSEL_T3TRGO ADC_JSQR_JEXTSEL(12) /* 1011 TIM3_TRGO */
|
||||
# define ADC_JEXTSEL_T3CC1 ADC_JSQR_JEXTSEL(13) /* 1101 TIM3_CH1 */
|
||||
# define ADC_JEXTSEL_T6TRGO ADC_JSQR_JEXTSEL(14) /* 1110 TIM6_TRGO */
|
||||
# define ADC_JEXTSEL_T15TRGO ADC_JSQR_JEXTSEL(15) /* 1111 TIM15_TRGO */
|
||||
#define ADC_JSQR_JEXTEN_SHIFT (6) /* Bits 6-7: External trigger selection for injected greoup */
|
||||
#define ADC_JSQR_JEXTEN_MASK (3 << ADC_JSQR_JEXTEN_SHIFT)
|
||||
# define ADC_JSQR_JEXTEN_NONE (0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
|
||||
# define ADC_JSQR_JEXTEN_RISING (1 << ADC_JSQR_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
|
||||
# define ADC_JSQR_JEXTEN_FALLING (2 << ADC_JSQR_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
|
||||
# define ADC_JSQR_JEXTEN_BOTH (3 << ADC_JSQR_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
|
||||
#define ADC_JSQR_JSQ1_SHIFT (8) /* Bits 8-12: 1st conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ_SHIFT (6)
|
||||
#define ADC_JSQR_JSQ1_SHIFT (8) /* Bits 8-12: 1st conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
|
||||
# define ADC_JSQR_JSQ1(ch) ((ch) << ADC_JSQR_JSQ1_SHIFT) /* Channel number 1..18 */
|
||||
#define ADC_JSQR_JSQ2_SHIFT (14) /* Bits 14-18: 2nd conversion in injected sequence */
|
||||
# define ADC_JSQR_JSQ1(ch) ((ch) << ADC_JSQR_JSQ1_SHIFT)/* Channel number 1..18 */
|
||||
#define ADC_JSQR_JSQ2_SHIFT (14) /* Bits 14-18: 2nd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_MASK)
|
||||
# define ADC_JSQR_JSQ2(ch) ((ch) << ADC_JSQR_JSQ2_MASK) /* Channel number 1..18 */
|
||||
#define ADC_JSQR_JSQ3_SHIFT (20) /* Bits 20-24: 3rd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ3_SHIFT (20) /* Bits 20-24: 3rd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
|
||||
# define ADC_JSQR_JSQ3(ch) ((ch) << ADC_JSQR_JSQ3_SHIFT) /* Channel number 1..18 */
|
||||
#define ADC_JSQR_JSQ4_SHIFT (26) /* Bits 26-30: 4th conversion in injected sequence */
|
||||
# define ADC_JSQR_JSQ3(ch) ((ch) << ADC_JSQR_JSQ3_SHIFT)/* Channel number 1..18 */
|
||||
#define ADC_JSQR_JSQ4_SHIFT (26) /* Bits 26-30: 4th conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT)
|
||||
# define ADC_JSQR_JSQ4(ch) ((ch) << ADC_JSQR_JSQ4_SHIFT) /* Channel number 1..18 */
|
||||
# define ADC_JSQR_JSQ4(ch) ((ch) << ADC_JSQR_JSQ4_SHIFT)/* Channel number 1..18 */
|
||||
|
||||
/* ADC offset register 1, 2, 3, and 4 */
|
||||
|
||||
@ -541,33 +565,34 @@
|
||||
/* Common control register */
|
||||
|
||||
#ifndef CONFIG_STM32L4_STM32L4X3
|
||||
# define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */
|
||||
# define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */
|
||||
# define ADC_CCR_DUAL_MASK (31 << ADC_CCR_DUAL_SHIFT)
|
||||
# define ADC_CCR_DUAL_IND (0 << ADC_CCR_DUAL_SHIFT) /* Independent mode */
|
||||
# define ADC_CCR_DUAL_DUAL (1 << ADC_CCR_DUAL_SHIFT) /* Dual mode, master/slave ADCs together */
|
||||
# define ADC_CCR_DUAL_SIMINJ (1 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + injected sim. */
|
||||
# define ADC_CCR_DUAL_SIMALT (2 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + alternate trigger */
|
||||
# define ADC_CCR_DUAL_INJECTED (5 << ADC_CCR_DUAL_SHIFT) /* Injected simultaneous mode only */
|
||||
# define ADC_CCR_DUAL_SIM (6 << ADC_CCR_DUAL_SHIFT) /* Regular simultaneous mode only */
|
||||
# define ADC_CCR_DUAL_INTERLEAVE (7 << ADC_CCR_DUAL_SHIFT) /* Interleaved mode only */
|
||||
# define ADC_CCR_DUAL_ALT (9 << ADC_CCR_DUAL_SHIFT) /* Alternate trigger mode only */
|
||||
# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */
|
||||
# define ADC_CCR_DUAL_IND (0 << ADC_CCR_DUAL_SHIFT) /* Independent mode */
|
||||
# define ADC_CCR_DUAL_DUAL (1 << ADC_CCR_DUAL_SHIFT) /* Dual mode, master/slave ADCs together */
|
||||
# define ADC_CCR_DUAL_SIMINJ (1 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + injected sim. */
|
||||
# define ADC_CCR_DUAL_SIMALT (2 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + alternate trigger */
|
||||
# define ADC_CCR_DUAL_INJECTED (5 << ADC_CCR_DUAL_SHIFT) /* Injected simultaneous mode only */
|
||||
# define ADC_CCR_DUAL_SIM (6 << ADC_CCR_DUAL_SHIFT) /* Regular simultaneous mode only */
|
||||
# define ADC_CCR_DUAL_INTERLEAVE (7 << ADC_CCR_DUAL_SHIFT) /* Interleaved mode only */
|
||||
# define ADC_CCR_DUAL_ALT (9 << ADC_CCR_DUAL_SHIFT) /* Alternate trigger mode only */
|
||||
# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */
|
||||
# define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT)
|
||||
# define ADC_CCR_DELAY(n) (((n)-1) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, 1-13 */
|
||||
# define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */
|
||||
# define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */
|
||||
# define ADC_CCR_DELAY(n) (((n)-1) << ADC_CCR_DELAY_SHIFT)
|
||||
/* n * TADCCLK, 1-13 */
|
||||
# define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */
|
||||
# define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */
|
||||
# define ADC_CCR_MDMA_MASK (3 << ADC_CCR_MDMA_SHIFT)
|
||||
# define ADC_CCR_MDMA_DISABLE (0 << ADC_CCR_MDMA_SHIFT) /* MDMA mode disabled */
|
||||
# define ADC_CCR_MDMA_10_12 (2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */
|
||||
# define ADC_CCR_MDMA_6_8 (3 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (8 / 6-bit) */
|
||||
# define ADC_CCR_MDMA_DISABLE (0 << ADC_CCR_MDMA_SHIFT) /* MDMA mode disabled */
|
||||
# define ADC_CCR_MDMA_10_12 (2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */
|
||||
# define ADC_CCR_MDMA_6_8 (3 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (8 / 6-bit) */
|
||||
#endif
|
||||
#define ADC_CCR_CKMODE_SHIFT (16) /* Bits 16-17: ADC clock mode */
|
||||
#define ADC_CCR_CKMODE_SHIFT (16) /* Bits 16-17: ADC clock mode */
|
||||
#define ADC_CCR_CKMODE_MASK (3 << ADC_CCR_CKMODE_SHIFT)
|
||||
# define ADC_CCR_CKMODE_ASYCH (0 << ADC_CCR_CKMODE_SHIFT) /* Asynchronous clock mode */
|
||||
# define ADC_CCR_CKMODE_SYNCH_DIV1 (1 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 1 */
|
||||
# define ADC_CCR_CKMODE_SYNCH_DIV2 (2 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 2 */
|
||||
# define ADC_CCR_CKMODE_SYNCH_DIV4 (3 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 4 */
|
||||
#define ADC_CCR_PRESC_SHIFT (18) /* Bits 18-21: ADC prescaler */
|
||||
#define ADC_CCR_PRESC_SHIFT (18) /* Bits 18-21: ADC prescaler */
|
||||
#define ADC_CCR_PRESC_MASK (3 << ADC_CCR_PRESC_SHIFT)
|
||||
# define ADC_CCR_PRESC_NOT_DIV (0 << ADC_CCR_PRESC_SHIFT) /* Input ADC clock not divided */
|
||||
# define ADC_CCR_PRESC_DIV2 (1 << ADC_CCR_PRESC_SHIFT) /* Input ADC clock divided by 2 */
|
||||
@ -581,9 +606,9 @@
|
||||
# define ADC_CCR_PRESC_DIV64 (9 << ADC_CCR_PRESC_SHIFT) /* Input ADC clock divided by 64 */
|
||||
# define ADC_CCR_PRESC_DIV128 (10 << ADC_CCR_PRESC_SHIFT) /* Input ADC clock divided by 128 */
|
||||
# define ADC_CCR_PRESC_DIV256 (11 << ADC_CCR_PRESC_SHIFT) /* Input ADC clock divided by 256 */
|
||||
#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */
|
||||
#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */
|
||||
#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */
|
||||
#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */
|
||||
#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */
|
||||
#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */
|
||||
|
||||
/* Common regular data register for dual mode */
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -161,6 +161,14 @@
|
||||
# undef ADC3_HAVE_DMA
|
||||
#endif
|
||||
|
||||
/* Injected channels support */
|
||||
|
||||
#if (defined(CONFIG_STM32L4_ADC1) && (CONFIG_STM32L4_ADC1_INJ_CHAN > 0)) || \
|
||||
(defined(CONFIG_STM32L4_ADC2) && (CONFIG_STM32L4_ADC2_INJ_CHAN > 0)) || \
|
||||
(defined(CONFIG_STM32L4_ADC3) && (CONFIG_STM32L4_ADC3_INJ_CHAN > 0))
|
||||
# define ADC_HAVE_INJECTED
|
||||
#endif
|
||||
|
||||
/* Timer configuration: If a timer trigger is specified, then get
|
||||
* information about the timer.
|
||||
*/
|
||||
@ -169,30 +177,37 @@
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32L4_TIM1_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN
|
||||
# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM2_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32L4_TIM2_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN
|
||||
# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM3_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32L4_TIM3_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN
|
||||
# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM4_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32L4_TIM4_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN
|
||||
# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM6_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32L4_TIM6_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN
|
||||
# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM8_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32L4_TIM8_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN
|
||||
# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM15_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32L4_TIM15_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN
|
||||
# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN
|
||||
#else
|
||||
# undef ADC1_HAVE_TIMER
|
||||
#endif
|
||||
@ -211,30 +226,37 @@
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32L4_TIM1_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN
|
||||
# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM2_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32L4_TIM2_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN
|
||||
# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM3_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32L4_TIM3_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN
|
||||
# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM4_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32L4_TIM4_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN
|
||||
# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM6_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32L4_TIM6_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN
|
||||
# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM8_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32L4_TIM8_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN
|
||||
# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM15_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32L4_TIM15_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN
|
||||
# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN
|
||||
#else
|
||||
# undef ADC2_HAVE_TIMER
|
||||
#endif
|
||||
@ -253,30 +275,37 @@
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32L4_TIM1_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN
|
||||
# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM2_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32L4_TIM2_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN
|
||||
# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM3_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32L4_TIM3_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN
|
||||
# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM4_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32L4_TIM4_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN
|
||||
# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM6_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32L4_TIM6_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN
|
||||
# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM8_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32L4_TIM8_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN
|
||||
# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN
|
||||
#elif defined(CONFIG_STM32L4_TIM15_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32L4_TIM15_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN
|
||||
# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN
|
||||
#else
|
||||
# undef ADC3_HAVE_TIMER
|
||||
#endif
|
||||
@ -426,7 +455,13 @@
|
||||
|
||||
/* EXTSEL configuration ******************************************************/
|
||||
|
||||
/* Configure external event for regular group */
|
||||
/* ADCx_EXTSEL_VALUE can be set by this driver or by board specific logic in
|
||||
* board.h file.
|
||||
*/
|
||||
|
||||
#ifndef ADC_EXTREG_EXTEN_DEFAULT
|
||||
# define ADC_EXTREG_EXTEN_DEFAULT ADC_CFGR_EXTEN_RISING
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32L4_TIM1_ADC1)
|
||||
# if CONFIG_STM32L4_ADC1_TIMTRIG == 0
|
||||
@ -740,10 +775,306 @@
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef ADC1_EXTSEL_VALUE
|
||||
# define ADC1_HAVE_EXTCFG 1
|
||||
# define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
|
||||
#else
|
||||
# undef ADC1_HAVE_EXTCFG
|
||||
#endif
|
||||
#ifdef ADC2_EXTSEL_VALUE
|
||||
# define ADC2_HAVE_EXTCFG 1
|
||||
# define ADC2_EXTCFG_VALUE (ADC2_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
|
||||
#else
|
||||
# undef ADC2_HAVE_EXTCFG
|
||||
#endif
|
||||
#ifdef ADC3_EXTSEL_VALUE
|
||||
# define ADC3_HAVE_EXTCFG 1
|
||||
# define ADC3_EXTCFG_VALUE (ADC3_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
|
||||
#else
|
||||
# undef ADC3_HAVE_EXTCFG
|
||||
#endif
|
||||
|
||||
#if defined(ADC1_HAVE_EXTCFG) || defined(ADC2_HAVE_EXTCFG) || \
|
||||
defined(ADC3_HAVE_EXTCFG) || defined(ADC3_HAVE_EXTCFG)
|
||||
# define ADC_HAVE_EXTCFG
|
||||
#endif
|
||||
|
||||
/* JEXTSEL configuration *****************************************************/
|
||||
|
||||
#ifndef ADC_JEXTREG_JEXTEN_DEFAULT
|
||||
# define ADC_JEXTREG_JEXTEN_DEFAULT ADC_JSQR_JEXTEN_RISING
|
||||
#endif
|
||||
|
||||
#if (CONFIG_STM32L4_ADC1_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM1)
|
||||
# if CONFIG_STM32L4_ADC1_JTIMTRIG == 3
|
||||
# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T1CC4
|
||||
# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 4
|
||||
# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T1TRGO
|
||||
# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 5
|
||||
# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T1TRGO2
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if (CONFIG_STM32L4_ADC1_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM2)
|
||||
# if CONFIG_STM32L4_ADC1_JTIMTRIG == 0
|
||||
# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T2CC1
|
||||
# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 4
|
||||
# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T2TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if (CONFIG_STM32L4_ADC1_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM3)
|
||||
# if CONFIG_STM32L4_ADC1_JTIMTRIG == 0
|
||||
# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T3CC1
|
||||
# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 2
|
||||
# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T3CC3
|
||||
# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 3
|
||||
# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T3CC4
|
||||
# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 4
|
||||
# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T3TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if (CONFIG_STM32L4_ADC1_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM4)
|
||||
# if CONFIG_STM32L4_ADC1_JTIMTRIG == 4
|
||||
# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T4TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if (CONFIG_STM32L4_ADC1_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM6)
|
||||
# if CONFIG_STM32L4_ADC1_JTIMTRIG == 4
|
||||
# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T6TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if (CONFIG_STM32L4_ADC1_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM8)
|
||||
# if CONFIG_STM32L4_ADC1_JTIMTRIG == 3
|
||||
# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T8CC4
|
||||
# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 4
|
||||
# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T8TRGO
|
||||
# elif CONFIG_STM32L4_ADC1_JTIMTRIG == 5
|
||||
# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T8TRGO2
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if (CONFIG_STM32L4_ADC1_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM15)
|
||||
# if CONFIG_STM32L4_ADC1_JTIMTRIG == 4
|
||||
# define ADC1_JEXTSEL_VALUE ADC_JEXTSEL_T15TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC1_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef ADC1_JEXTSEL_VALUE
|
||||
# define ADC1_HAVE_JEXTCFG 1
|
||||
# define ADC1_JEXTCFG_VALUE (ADC1_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC2
|
||||
#if (CONFIG_STM32L4_ADC2_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM1)
|
||||
# if CONFIG_STM32L4_ADC2_JTIMTRIG == 3
|
||||
# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T1CC4
|
||||
# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 4
|
||||
# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T1TRGO
|
||||
# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 5
|
||||
# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T1TRGO2
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC2
|
||||
#if (CONFIG_STM32L4_ADC2_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM2)
|
||||
# if CONFIG_STM32L4_ADC2_JTIMTRIG == 0
|
||||
# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T2CC1
|
||||
# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 4
|
||||
# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T2TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC2
|
||||
#if (CONFIG_STM32L4_ADC2_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM3)
|
||||
# if CONFIG_STM32L4_ADC2_JTIMTRIG == 0
|
||||
# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T3CC1
|
||||
# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 2
|
||||
# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T3CC3
|
||||
# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 3
|
||||
# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T3CC4
|
||||
# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 4
|
||||
# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T3TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC2
|
||||
#if (CONFIG_STM32L4_ADC2_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM4)
|
||||
# if CONFIG_STM32L4_ADC2_JTIMTRIG == 4
|
||||
# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T4TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC2
|
||||
#if (CONFIG_STM32L4_ADC2_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM6)
|
||||
# if CONFIG_STM32L4_ADC2_JTIMTRIG == 4
|
||||
# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T6TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC2
|
||||
#if (CONFIG_STM32L4_ADC2_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM8)
|
||||
# if CONFIG_STM32L4_ADC2_JTIMTRIG == 3
|
||||
# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T8CC4
|
||||
# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 4
|
||||
# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T8TRGO
|
||||
# elif CONFIG_STM32L4_ADC2_JTIMTRIG == 5
|
||||
# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T8TRGO2
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC2
|
||||
#if (CONFIG_STM32L4_ADC2_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM15)
|
||||
# if CONFIG_STM32L4_ADC2_JTIMTRIG == 4
|
||||
# define ADC2_JEXTSEL_VALUE ADC_JEXTSEL_T15TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC2_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef ADC2_JEXTSEL_VALUE
|
||||
# define ADC2_HAVE_JEXTCFG 1
|
||||
# define ADC2_JEXTCFG_VALUE (ADC2_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC3
|
||||
#if (CONFIG_STM32L4_ADC3_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM1)
|
||||
# if CONFIG_STM32L4_ADC3_JTIMTRIG == 3
|
||||
# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T1CC4
|
||||
# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 4
|
||||
# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T1TRGO
|
||||
# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 5
|
||||
# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T1TRGO2
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC3
|
||||
#if (CONFIG_STM32L4_ADC3_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM2)
|
||||
# if CONFIG_STM32L4_ADC3_JTIMTRIG == 0
|
||||
# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T2CC1
|
||||
# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 4
|
||||
# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T2TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC3
|
||||
#if (CONFIG_STM32L4_ADC3_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM3)
|
||||
# if CONFIG_STM32L4_ADC3_JTIMTRIG == 0
|
||||
# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T3CC1
|
||||
# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 2
|
||||
# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T3CC3
|
||||
# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 3
|
||||
# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T3CC4
|
||||
# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 4
|
||||
# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T3TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC3
|
||||
#if (CONFIG_STM32L4_ADC3_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM4)
|
||||
# if CONFIG_STM32L4_ADC3_JTIMTRIG == 4
|
||||
# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T4TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC3
|
||||
#if (CONFIG_STM32L4_ADC3_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM6)
|
||||
# if CONFIG_STM32L4_ADC3_JTIMTRIG == 4
|
||||
# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T6TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC3
|
||||
#if (CONFIG_STM32L4_ADC3_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM8)
|
||||
# if CONFIG_STM32L4_ADC3_JTIMTRIG == 3
|
||||
# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T8CC4
|
||||
# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 4
|
||||
# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T8TRGO
|
||||
# elif CONFIG_STM32L4_ADC3_JTIMTRIG == 5
|
||||
# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T8TRGO2
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32L4_ADC3
|
||||
#if (CONFIG_STM32L4_ADC3_INJ_CHAN > 0) && defined(CONFIG_STM32L4_TIM15)
|
||||
# if CONFIG_STM32L4_ADC3_JTIMTRIG == 4
|
||||
# define ADC3_JEXTSEL_VALUE ADC_JEXTSEL_T15TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32L4_ADC3_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef ADC3_JEXTSEL_VALUE
|
||||
# define ADC3_HAVE_JEXTCFG 1
|
||||
# define ADC3_JEXTCFG_VALUE (ADC3_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT)
|
||||
#endif
|
||||
|
||||
#if defined(ADC1_HAVE_JEXTCFG) || defined(ADC2_HAVE_JEXTCFG) || \
|
||||
defined(ADC3_HAVE_JEXTCFG)
|
||||
# define ADC_HAVE_JEXTCFG
|
||||
#endif
|
||||
|
||||
/* ADC interrupts ************************************************************/
|
||||
|
||||
#define ADC_ISR_EOC ADC_INT_EOC
|
||||
#define ADC_IER_EOC ADC_INT_EOC
|
||||
#define ADC_ISR_EOS ADC_INT_EOS
|
||||
#define ADC_IER_EOS ADC_INT_EOS
|
||||
#define ADC_ISR_AWD ADC_INT_AWD1
|
||||
#define ADC_IER_AWD ADC_INT_AWD1
|
||||
#define ADC_ISR_JEOC ADC_INT_JEOC
|
||||
@ -753,10 +1084,10 @@
|
||||
#define ADC_ISR_JEOS ADC_INT_JEOS
|
||||
#define ADC_IER_JEOS ADC_INT_JEOS
|
||||
|
||||
#define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_AWD | ADC_ISR_JEOC | \
|
||||
ADC_ISR_JEOS | ADC_ISR_OVR)
|
||||
#define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_AWD | ADC_IER_JEOC | \
|
||||
ADC_IER_JEOS | ADC_IER_OVR)
|
||||
#define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_EOS | ADC_ISR_AWD | \
|
||||
ADC_ISR_JEOC | ADC_ISR_JEOS | ADC_ISR_OVR)
|
||||
#define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_EOS | ADC_IER_AWD | \
|
||||
ADC_IER_JEOC | ADC_IER_JEOS | ADC_IER_OVR)
|
||||
|
||||
/* Low-level ops helpers *****************************************************/
|
||||
|
||||
@ -770,10 +1101,14 @@
|
||||
(adc)->llops->int_dis(adc, source)
|
||||
#define ADC_REGDATA_GET(adc) \
|
||||
(adc)->llops->val_get(adc)
|
||||
#define ADC_INJDATA_GET(adc, chan) \
|
||||
(adc)->llops->inj_get(adc, chan)
|
||||
#define ADC_REGBUF_REGISTER(adc, buffer, len) \
|
||||
(adc)->llops->regbuf_reg(adc, buffer, len)
|
||||
#define ADC_REG_STARTCONV(adc, state) \
|
||||
(adc)->llops->reg_startconv(adc, state)
|
||||
#define ADC_INJ_STARTCONV(adc, state) \
|
||||
(adc)->llops->inj_startconv(adc, state)
|
||||
#define ADC_OFFSET_SET(adc, ch, i, o) \
|
||||
(adc)->llops->offset_set(adc, ch, i, o)
|
||||
#define ADC_EXTSEL_SET(adc, extcfg) \
|
||||
@ -781,6 +1116,16 @@
|
||||
#define ADC_DUMP_REGS(adc) \
|
||||
(adc)->llops->dump_regs(adc)
|
||||
|
||||
/* IOCTL Commands ************************************************************
|
||||
*
|
||||
* Cmd: ANIOC_STM32L4_TRIGGER_REG Arg:
|
||||
* Cmd: ANIOC_STM32L4_TRIGGER_INJ Arg:
|
||||
*
|
||||
*/
|
||||
|
||||
#define ANIOC_STM32L4_TRIGGER_REG _ANIOC(AN_STM32L4_FIRST + 0)
|
||||
#define ANIOC_STM32L4_TRIGGER_INJ _ANIOC(AN_STM32L4_FIRST + 1)
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Types
|
||||
*****************************************************************************/
|
||||
@ -842,6 +1187,22 @@ struct stm32_adc_ops_s
|
||||
|
||||
int (*extsel_set)(FAR struct stm32_adc_dev_s *dev, uint32_t extcfg);
|
||||
|
||||
#ifdef ADC_HAVE_JEXTCFG
|
||||
/* Configure the ADC external trigger for injected conversion */
|
||||
|
||||
void (*jextsel_set)(FAR struct stm32_adc_dev_s *dev, uint32_t jextcfg);
|
||||
#endif
|
||||
|
||||
#ifdef ADC_HAVE_INJECTED
|
||||
/* Get current ADC injected data register */
|
||||
|
||||
uint32_t (*inj_get)(FAR struct stm32_adc_dev_s *dev, uint8_t chan);
|
||||
|
||||
/* Start/stop injected conversion */
|
||||
|
||||
void (*inj_startconv)(FAR struct stm32_adc_dev_s *dev, bool state);
|
||||
#endif
|
||||
|
||||
/* Dump ADC regs */
|
||||
|
||||
void (*dump_regs)(FAR struct stm32_adc_dev_s *dev);
|
||||
|
||||
@ -91,6 +91,11 @@
|
||||
AN_LMP92001_NCMDS)
|
||||
#define AN_ADS7828_NCMDS 6
|
||||
|
||||
/* See arch/arm/src/stm32l4/stm32l4_adc.h */
|
||||
|
||||
#define AN_STM32L4_FIRST (AN_ADS7828_FIRST + AN_ADS7828_NCMDS)
|
||||
#define AN_STM32L4_NCMDS 2
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user