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Add beginning of an Kinetics Ethernet driver

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3886 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2011-08-16 23:04:11 +00:00
parent 7c0bd1ad17
commit a60daf4fe7
12 changed files with 1721 additions and 235 deletions
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4
arch/arm/src/kinetis/Make.defs
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@ -49,7 +49,7 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
up_doirq.c up_hardfault.c up_svcall.c up_checkstack.c
ifeq ($(CONFIG_NET),y)
ifneq ($(CONFIG_KINETIS_ETHERNET),y)
ifneq ($(CONFIG_KINETIS_ENET),y)
CMN_CSRCS += up_etherstub.c
endif
endif
@ -88,7 +88,7 @@ CHIP_CSRCS += kinetis_dma.c
endif
ifeq ($(CONFIG_NET),y)
ifeq ($(CONFIG_KINETIS_ETHERNET),y)
ifeq ($(CONFIG_KINETIS_ENET),y)
CHIP_CSRCS += kinetis_enet.c
endif
endif

1
arch/arm/src/kinetis/chip.h
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@ -836,6 +836,7 @@
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Steps between supported priority values */
/************************************************************************************
* Public Types

23
arch/arm/src/kinetis/kinetis_config.h
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@ -163,7 +163,7 @@
#undef CONFIG_KINETIS_UARTFIFOS
/* Default Priorities */
/* UART Default Interrupt Priorities */
#ifndef CONFIG_KINETIS_UART0PRIO
# define CONFIG_KINETIS_UART0PRIO NVIC_SYSH_PRIORITY_DEFAULT
@ -184,6 +184,27 @@
# define CONFIG_KINETIS_UART5PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
/* Ethernet controller configuration */
#ifndef CONFIG_ENET_NBUFFERS
# define CONFIG_ENET_NBUFFERS 8
#endif
/* EMAC Default Interrupt Priorities */
#ifndef CONFIG_KINETIS_EMACTMR_PRIO
# define CONFIG_KINETIS_EMACTMR_PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
#ifndef CONFIG_KINETIS_EMACTX_PRIO
# define CONFIG_KINETIS_EMACTX_PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
#ifndef CONFIG_KINETIS_EMACRX_PRIO
# define CONFIG_KINETIS_EMACRX_PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
#ifndef CONFIG_KINETIS_EMACMISC_PRIO
# define CONFIG_KINETIS_EMACMISC_PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
/************************************************************************************
* Public Types
************************************************************************************/

1302
arch/arm/src/kinetis/kinetis_enet.c Normal file
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File diff suppressed because it is too large Load Diff

162
arch/arm/src/kinetis/kinetis_enet.h
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@ -433,9 +433,171 @@
/* Bits 8-31: Reserved */
/* Timer Compare Capture Register (32-bit compare value) */
/* Buffer Descriptors ***********************************************************************/
/* Endian-independent descriptor offsets */
#define DESC_STATUS1_OFFSET (0)
#define DESC_LENGTH_OFFSET (2)
#define DESC_DATAPTR_OFFSET (4)
#define DESC_LEGACY_LEN (8)
#define DESC_STATUS2_OFFSET (8)
#define DESC_LENPROTO_OFFSET (12)
#define DESC_CHECKSUM_OFFSET (14)
#define DESC_BDU_OFFSET (16)
#define DESC_TIMESTAMP_OFFSET (20)
#define DESC_ENHANCED_LEN (32)
/* Legacy/Common TX Buffer Descriptor Bit Definitions.
*
* The descriptors are represented by structures Unfortunately, when the
* structures are overlayed on the data, the bytes are reversed because
* the underlying hardware writes the data in big-endian byte order.
*/
#ifdef CONFIG_ENDIAN_BIG
# define TXDESC_ABC (1 << 9) /* Legacy */
# define TXDESC_TC (1 << 10) /* Common */
# define TXDESC_L (1 << 11) /* Common */
# define TXDESC_TO2 (1 << 12) /* Common */
# define TXDESC_W (1 << 13) /* Common */
# define TXDESC_TO1 (1 << 14) /* Common */
# define TXDESC_R (1 << 15) /* Common */
#endif
# define TXDESC_ABC (1 << 1) /* Legacy */
# define TXDESC_TC (1 << 2) /* Common */
# define TXDESC_L (1 << 3) /* Common */
# define TXDESC_TO2 (1 << 4) /* Common */
# define TXDESC_W (1 << 5) /* Common */
# define TXDESC_TO1 (1 << 6) /* Common */
# define TXDESC_R (1 << 7) /* Common */
#endif
/* Enhanced (only) TX Buffer Descriptor Bit Definitions */
#ifdef CONFIG_ENDIAN_BIG
# define TXDESC_TSE (1 << 8)
# define TXDESC_OE (1 << 9)
# define TXDESC_LCE (1 << 10)
# define TXDESC_FE (1 << 11)
# define TXDESC_EE (1 << 12)
# define TXDESC_UE (1 << 13)
# define TXDESC_TXE (1 << 15)
# define TXDESC_IINS (1 << 27)
# define TXDESC_PINS (1 << 28)
# define TXDESC_TS (1 << 29)
# define TXDESC_INT (1 << 30)
# define TXDESC_BDU (1 << 31)
#else
# define TXDESC_IINS (1 << 3)
# define TXDESC_PINS (1 << 4)
# define TXDESC_TS (1 << 5)
# define TXDESC_INT (1 << 6)
# define TXDESC_TSE (1 << 16)
# define TXDESC_OE (1 << 17)
# define TXDESC_LCE (1 << 18)
# define TXDESC_FE (1 << 19)
# define TXDESC_EE (1 << 20)
# define TXDESC_UE (1 << 21)
# define TXDESC_TXE (1 << 23)
# define TXDESC_BDU (1 << 7)
#endif
/* Legacy (and Common) RX Buffer Descriptor Bit Definitions */
#ifdef CONFIG_ENDIAN_BIG
# define RXDESC_TR (1 << 0)
# define RXDESC_OV (1 << 1)
# define RXDESC_CR (1 << 2)
# define RXDESC_NO (1 << 4)
# define RXDESC_LG (1 << 5)
# define RXDESC_MC (1 << 6)
# define RXDESC_BC (1 << 7)
# define RXDESC_M (1 << 8)
# define RXDESC_L (1 << 11)
# define RXDESC_R02 (1 << 12)
# define RXDESC_W (1 << 13)
# define RXDESC_R01 (1 << 14)
# define RXDESC_E (1 << 15)
#else
# define RXDESC_M (1 << 0)
# define RXDESC_L (1 << 3)
# define RXDESC_R02 (1 << 4)
# define RXDESC_W (1 << 5)
# define RXDESC_R01 (1 << 6)
# define RXDESC_E (1 << 7)
# define RXDESC_TR (1 << 8)
# define RXDESC_OV (1 << 9)
# define RXDESC_CR (1 << 10)
# define RXDESC_NO (1 << 12)
# define RXDESC_LG (1 << 13)
# define RXDESC_MC (1 << 14)
# define RXDESC_BC (1 << 15)
#endif
/* Enhanced (only) TX Buffer Descriptor Bit Definitions */
#ifdef CONFIG_ENDIAN_BIG
# define RXDESC_FRAG (1 << 0)
# define RXDESC_IPV6 (1 << 1)
# define RXDESC_VLAN (1 << 2)
# define RXDESC_PCR (1 << 4)
# define RXDESC_ICE (1 << 5)
# define RXDESC_INT (1 << 23)
# define RXDESC_UC (1 << 24)
# define RXDESC_CE (1 << 25)
# define RXDESC_PE (1 << 26)
# define RXDESC_ME (1 << 31)
# define RXDESC_BDU (1 << 31)
#else
# define RXDESC_UC (1 << 0)
# define RXDESC_CE (1 << 1)
# define RXDESC_PE (1 << 2)
# define RXDESC_ME (1 << 7)
# define RXDESC_INT (1 << 15)
# define RXDESC_FRAG (1 << 24)
# define RXDESC_IPV6 (1 << 25)
# define RXDESC_VLAN (1 << 26)
# define RXDESC_PCR (1 << 28)
# define RXDESC_ICE (1 << 29)
# define RXDESC_BDU (1 << 7)
#endif
/********************************************************************************************
* Public Types
********************************************************************************************/
/* Buffer Descriptors ***********************************************************************/
/* Legacy Buffer Descriptor */
#ifdef CONFIG_ENET_ENHANCEDBD
struct enet_desc_s
{
uint16_t status1; /* Control and status */
uint16_t length; /* Data length */
uint8_t *data; /* Buffer address */
uint32_t status2; /* Extended status */
uint16_t lenproto; /* Header length + Protocol type */
uint16_t checksum; /* Payload checksum */
uint32_t bdu; /* BDU */
uint32_t timestamp; /* Time stamp */
uint32_t reserved1; /* unused */
uint32_t reserved2; /* unused */
}
#else
struct enet_desc_s
{
uint16_t status1; /* Control and status */
uint16_t length; /* Data length */
uint8_t *data; /* Buffer address */
};
#endif
/********************************************************************************************
* Public Data

5
arch/arm/src/kinetis/kinetis_k60pinmux.h
View File

@ -82,8 +82,13 @@
#define PIN_FTM0_CH1_1 (PIN_ALT3 | PIN_PORTA | PIN4)
#define PIN_NMI (PIN_ALT7 | PIN_PORTA | PIN4)
#define PIN_FTM0_CH2_1 (PIN_ALT3 | PIN_PORTA | PIN5)
#if 0
# define PIN_RMII0_RXER (PIN_ALT4 | PIN_PORTA | PIN5)
# define PIN_MII0_RXER (PIN_ALT4 | PIN_PORTA | PIN5)
#else
# define PIN_RMII0_RXER (GPIO_PULLDOWN | PIN_PORTA | PIN5)
# define PIN_MII0_RXER (GPIO_PULLDOWN | PIN_PORTA | PIN5)
#endif
#define PIN_CMP2_OUT_1 (PIN_ALT5 | PIN_PORTA | PIN5)
#define PIN_I2S0_RX_BCLK_1 (PIN_ALT6 | PIN_PORTA | PIN5)
#define PIN_JTAG_TRST (PIN_ALT7 | PIN_PORTA | PIN5)

3
arch/arm/src/kinetis/kinetis_sim.h
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@ -292,7 +292,7 @@
/* Bits 12-31: Reserved */
/* System Clock Gating Control Register 2 */
#ifdef KINETIS_K60
#if defined(KINETIS_NENET) && KINETIS_NENET > 0
# define SIM_SCGC2_ENET (1 << 0) /* Bit 0: ENET Clock Gate Control (K60) */
#endif
/* Bits 1-11: Reserved */
@ -301,6 +301,7 @@
/* Bits 14-31: Reserved */
/* System Clock Gating Control Register 3 */
#if defined(KINETIS_NRNG) && KINETIS_NRNG > 0
#ifdef KINETIS_K60
# define SIM_SCGC3_RNGB (1 << 0) /* Bit 0: RNGB Clock Gate Control (K60) */
#endif

2
configs/kwikstik-k40/README.txt
View File

@ -349,7 +349,7 @@ KwikStik-K40-specific Configuration Options
CONFIG_KINETIS_UART3 -- Support UART3
CONFIG_KINETIS_UART4 -- Support UART4
CONFIG_KINETIS_UART5 -- Support UART5
CONFIG_KINETIS_ETHERNET -- Support Ethernet (K60 only)
CONFIG_KINETIS_ENET -- Support Ethernet (K60 only)
CONFIG_KINETIS_RNGB -- Support the random number generator(K60 only)
CONFIG_KINETIS_FLEXCAN0 -- Support FlexCAN0
CONFIG_KINETIS_FLEXCAN1 -- Support FlexCAN1

4
configs/kwikstik-k40/ostest/defconfig
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@ -118,7 +118,7 @@ CONFIG_KINETIS_DFU=y
# CONFIG_KINETIS_UART3 - Support UART3
# CONFIG_KINETIS_UART4 - Support UART4
# CONFIG_KINETIS_UART5 - Support UART5
# CONFIG_KINETIS_ETHERNET - Support Ethernet (K60 only)
# CONFIG_KINETIS_ENET - Support Ethernet (K60 only)
# CONFIG_KINETIS_RNGB - Support the random number generator(K60 only)
# CONFIG_KINETIS_FLEXCAN0 - Support FlexCAN0
# CONFIG_KINETIS_FLEXCAN1 - Support FlexCAN1
@ -162,7 +162,7 @@ CONFIG_KINETIS_UART2=n
CONFIG_KINETIS_UART3=n
CONFIG_KINETIS_UART4=n
CONFIG_KINETIS_UART5=y
CONFIG_KINETIS_ETHERNET=n
CONFIG_KINETIS_ENET=n
CONFIG_KINETIS_RNGB=n
CONFIG_KINETIS_FLEXCAN0=n
CONFIG_KINETIS_FLEXCAN1=n

26
configs/twr-k60n512/README.txt
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@ -483,7 +483,7 @@ TWR-K60N512-specific Configuration Options
CONFIG_KINETIS_UART3 -- Support UART3
CONFIG_KINETIS_UART4 -- Support UART4
CONFIG_KINETIS_UART5 -- Support UART5
CONFIG_KINETIS_ETHERNET -- Support Ethernet (K60 only)
CONFIG_KINETIS_ENET -- Support Ethernet (K60 only)
CONFIG_KINETIS_RNGB -- Support the random number generator(K60 only)
CONFIG_KINETIS_FLEXCAN0 -- Support FlexCAN0
CONFIG_KINETIS_FLEXCAN1 -- Support FlexCAN1
@ -528,6 +528,11 @@ TWR-K60N512-specific Configuration Options
CONFIG_KINETIS_UART4PRIO
CONFIG_KINETIS_UART5PRIO
CONFIG_KINETIS_EMACTMR_PRIO
CONFIG_KINETIS_EMACTX_PRIO
CONFIG_KINETIS_EMACRX_PRIO
CONFIG_KINETIS_EMACMISC_PRIO
PIN Interrupt Support
CONFIG_GPIO_IRQ -- Enable pin interrtup support. Also needs
@ -550,22 +555,11 @@ TWR-K60N512-specific Configuration Options
CONFIG_UARTn_BITS - The number of bits. Must be either 8 or 8.
CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
TWR-K60N512 LCD Hardware Configuration
Kenetis ethernet controller settings
CONFIG_LCD_LANDSCAPE - Define for 320x240 display "landscape"
support. Default is this 320x240 "landscape" orientation
(this setting is informative only... not used).
CONFIG_LCD_PORTRAIT - Define for 240x320 display "portrait"
orientation support. In this orientation, the TWR-K60N512's
LCD ribbon cable is at the bottom of the display. Default is
320x240 "landscape" orientation.
CONFIG_LCD_RPORTRAIT - Define for 240x320 display "reverse
portrait" orientation support. In this orientation, the
TWR-K60N512's LCD ribbon cable is at the top of the display.
Default is 320x240 "landscape" orientation.
CONFIG_LCD_BACKLIGHT - Define to support an adjustable backlight
using timer 1. The granularity of the settings is determined
by CONFIG_LCD_MAXPOWER. Requires CONFIG_KINETIS_TIM1.
CONFIG_ENET_NBUFFERS - Number of TX/RX buffers. The size of one
buffer is determined by CONFIG_NET_BUFSIZE. Default: 8
CONFIG_ENET_USEMII - Usee MII mode. Default: RMII mode.
Configurations
==============

4
configs/twr-k60n512/ostest/defconfig
View File

@ -111,7 +111,7 @@ CONFIG_KINETIS_DFU=y
# CONFIG_KINETIS_UART3 - Support UART3
# CONFIG_KINETIS_UART4 - Support UART4
# CONFIG_KINETIS_UART5 - Support UART5
# CONFIG_KINETIS_ETHERNET - Support Ethernet (K60 only)
# CONFIG_KINETIS_ENET - Support Ethernet (K60 only)
# CONFIG_KINETIS_RNGB - Support the random number generator(K60 only)
# CONFIG_KINETIS_FLEXCAN0 - Support FlexCAN0
# CONFIG_KINETIS_FLEXCAN1 - Support FlexCAN1
@ -155,7 +155,7 @@ CONFIG_KINETIS_UART2=n
CONFIG_KINETIS_UART3=n
CONFIG_KINETIS_UART4=n
CONFIG_KINETIS_UART5=y
CONFIG_KINETIS_ETHERNET=n
CONFIG_KINETIS_ENET=n
CONFIG_KINETIS_RNGB=n
CONFIG_KINETIS_FLEXCAN0=n
CONFIG_KINETIS_FLEXCAN1=n

8
drivers/net/skeleton.c
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@ -67,7 +67,7 @@
# define CONFIG_skeleton_NINTERFACES 1
#endif
/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
#define skeleton_WDDELAY (1*CLK_TCK)
#define skeleton_POLLHSEC (1*2)
@ -355,7 +355,7 @@ static int skel_interrupt(int irq, FAR void *context)
skel_receive(skel);
/* Check is a packet transmission just completed. If so, call skel_txdone.
/* Check if a packet transmission just completed. If so, call skel_txdone.
* This may disable further Tx interrupts if there are no pending
* tansmissions.
*/
@ -504,7 +504,7 @@ static int skel_ifdown(struct uip_driver_s *dev)
wd_cancel(skel->sk_txpoll);
wd_cancel(skel->sk_txtimeout);
/* Put the the EMAC is its reset, non-operational state. This should be
/* Put the EMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the skel_ifup() always
* successfully brings the interface back up.
*/
@ -655,7 +655,7 @@ int skel_initialize(int intf)
if (irq_attach(CONFIG_skeleton_IRQ, skel_interrupt))
{
/* We could not attach the ISR to the the interrupt */
/* We could not attach the ISR to the interrupt */
return -EAGAIN;
}