samv7: adds support for QSPI driver in SPI Mode
This commit adds new files that support functionality of QSPI driver in SPI Master Mode. This functionality is included in new files sam_qspi_spi.x to avoid too much mess in the source code. QSPI in SPI mode can be turn on by config option SAMV7_QSPI_SPI_MODE. Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit is contained in:
Michal Lenc
Xiang Xiao
parent
b5b00c6ba3
commit
a64903acc7
@ -182,7 +182,8 @@
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# define SAMV7_NUSART 0 /* No USARTs */
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# define SAMV7_NUART 5 /* 5 UARTs */
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# define SAMV7_NQSPI 0 /* No Quad SPI */
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# define SAMV7_NSPI 1 /* No SPI, QSPI functions in SPI mode only */
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# define SAMV7_NQSPI_SPI 1 /* QSPI functions in SPI mode only */
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# define SAMV7_NSPI 0 /* No SPI */
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# define SAMV7_NTWIHS 2 /* 2 TWIHS */
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# define SAMV7_NHSMCI4 0 /* No 4-bit HSMCI port */
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# define SAMV7_NCAN 1 /* 1 CAN port */
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@ -394,6 +394,17 @@ config SAMV7_QSPI
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select ARCH_USE_MPU
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select ARM_MPU
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if SAMV7_QSPI
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config SAMV7_QSPI_SPI_MODE
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bool "SPI Mode"
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default n
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depends on SAMV7_QSPI_IS_SPI
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---help---
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Use Quad SPI in SPI mode
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endif
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config SAMV7_RTC
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bool "Real Time Clock (RTC)"
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default n
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@ -123,7 +123,9 @@ ifeq ($(CONFIG_SAMV7_SPI_SLAVE),y)
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CHIP_CSRCS += sam_spi_slave.c
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endif
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ifeq ($(CONFIG_SAMV7_QSPI),y)
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ifeq ($(CONFIG_SAMV7_QSPI_SPI_MODE),y)
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CHIP_CSRCS += sam_qspi_spi.c
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else ifeq ($(CONFIG_SAMV7_QSPI),y)
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CHIP_CSRCS += sam_qspi.c
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endif
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@ -30,7 +30,7 @@
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#include "hardware/sam_memorymap.h"
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#if SAMV7_NQSPI > 0
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#if SAMV7_NQSPI > 0 || SAMV7_NQSPI_SPI > 0
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/****************************************************************************
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* Pre-processor Definitions
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@ -112,6 +112,7 @@
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/* QSPI Mode Register */
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#define QSPI_MR_SPI (0 << 0) /* Bit 0: SPI Master Mode */
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#define QSPI_MR_SMM (1 << 0) /* Bit 0: Serial Memory Mode */
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#define QSPI_MR_LLB (1 << 1) /* Bit 1: Local Loopback Enable */
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#define QSPI_MR_WDRBT (1 << 2) /* Bit 2: Wait Data Read Before Transfer */
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@ -55,7 +55,7 @@
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#include "hardware/sam_qspi.h"
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#include "hardware/sam_pinmap.h"
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#ifdef CONFIG_SAMV7_QSPI
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#if defined(CONFIG_SAMV7_QSPI) && !defined(CONFIG_SAMV7_QSPI_SPI_MODE)
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/****************************************************************************
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* Pre-processor Definitions
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864
arch/arm/src/samv7/sam_qspi_spi.c
Normal file
864
arch/arm/src/samv7/sam_qspi_spi.c
Normal file
@ -0,0 +1,864 @@
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/****************************************************************************
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* arch/arm/src/samv7/sam_qspi_spi.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <inttypes.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include <string.h>
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#include <errno.h>
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#include <assert.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/wdog.h>
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#include <nuttx/clock.h>
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#include <nuttx/semaphore.h>
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#include <nuttx/spi/spi.h>
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#include "arm_internal.h"
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#include "arm_arch.h"
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#include "sam_gpio.h"
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#include "sam_xdmac.h"
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#include "sam_periphclks.h"
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#include "sam_qspi_spi.h"
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#include "hardware/sam_pmc.h"
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#include "hardware/sam_xdmac.h"
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#include "hardware/sam_qspi.h"
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#include "hardware/sam_pinmap.h"
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#ifdef CONFIG_SAMV7_QSPI_SPI_MODE
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The SPI Baud rate clock is generated by dividing the peripheral clock by
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* a value between 1 and 255
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*/
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#define SAM_QSPI_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */
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struct sam_spics_s
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{
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struct spi_dev_s spidev; /* Externally visible part of the SPI interface */
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uint32_t frequency; /* Requested clock frequency */
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uint32_t actual; /* Actual clock frequency */
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uint8_t mode; /* Mode 0,1,2,3 */
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uint8_t nbits; /* Width of word in bits (8 to 16) */
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};
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/* Type of board-specific SPI status function */
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typedef void (*select_t)(uint32_t devid, bool selected);
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/* The overall state of one SPI controller */
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struct sam_spidev_s
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{
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uint32_t base; /* SPI controller register base address */
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sem_t spisem; /* Assures mutually exclusive access to SPI */
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select_t select; /* SPI select call-out */
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bool initialized; /* TRUE: Controller has been initialized */
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bool escape_lastxfer; /* Don't set LASTXFER-Bit in the next transfer */
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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static inline uint32_t qspi_getreg(struct sam_spidev_s *spi,
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unsigned int offset);
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static inline void qspi_putreg(struct sam_spidev_s *spi, uint32_t value,
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unsigned int offset);
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static inline void qspi_flush(struct sam_spidev_s *spi);
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/* SPI master methods */
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static int qspi_spi_lock(struct spi_dev_s *dev, bool lock);
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static void qspi_spi_select(struct spi_dev_s *dev, uint32_t devid,
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bool selected);
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static uint32_t qspi_spi_setfrequency(struct spi_dev_s *dev,
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uint32_t frequency);
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static void qspi_spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode);
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static void qspi_spi_setbits(struct spi_dev_s *dev, int nbits);
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static uint32_t qspi_spi_send(struct spi_dev_s *dev, uint32_t wd);
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static void qspi_spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
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void *rxbuffer, size_t nwords);
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#ifndef CONFIG_SPI_EXCHANGE
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static void qspi_spi_sndblock(struct spi_dev_s *dev, const void *buffer,
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size_t nwords);
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static void qspi_spi_recvblock(struct spi_dev_s *dev, void *buffer,
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size_t nwords);
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* QSPI_SPI driver operations */
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static const struct spi_ops_s g_spiops =
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{
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.lock = qspi_spi_lock,
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.select = qspi_spi_select,
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.setfrequency = qspi_spi_setfrequency,
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.setmode = qspi_spi_setmode,
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.setbits = qspi_spi_setbits,
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.status = sam_qspi_status,
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#ifdef CONFIG_SPI_CMDDATA
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.cmddata = sam_qspi_cmddata,
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#endif
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.send = qspi_spi_send,
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#ifdef CONFIG_SPI_EXCHANGE
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.exchange = qspi_spi_exchange,
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#else
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.sndblock = qspi_spi_sndblock,
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.recvblock = qspi_spi_recvblock,
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#endif
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.registercallback = 0, /* Not implemented */
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};
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/* This is the overall state of the SPI0 controller */
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static struct sam_spidev_s g_spidev =
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{
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.base = SAM_QSPI_BASE,
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.select = sam_qspi_select,
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};
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: qspi_spi_getreg
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*
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* Description:
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* Read a QSPI register
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*
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****************************************************************************/
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static inline uint32_t qspi_getreg(struct sam_spidev_s *spi,
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unsigned int offset)
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{
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uint32_t address = spi->base + offset;
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uint32_t value = getreg32(address);
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return value;
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}
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/****************************************************************************
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* Name: qspi_putreg
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*
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* Description:
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* Write a value to a QSPI register
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*
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****************************************************************************/
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static inline void qspi_putreg(struct sam_spidev_s *spi, uint32_t value,
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unsigned int offset)
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{
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uint32_t address = spi->base + offset;
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putreg32(value, address);
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}
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/****************************************************************************
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* Name: qspi_flush
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*
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* Description:
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* Make sure that there are now dangling SPI transfer in progress
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*
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* Input Parameters:
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* spi - SPI controller state
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void qspi_flush(struct sam_spidev_s *spi)
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{
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/* Make sure the no TX activity is in progress... waiting if necessary */
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while ((qspi_getreg(spi, SAM_QSPI_SR_OFFSET) & QSPI_INT_TXEMPTY) == 0);
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/* Then make sure that there is no pending RX data .. reading as
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* discarding as necessary.
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*/
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while ((qspi_getreg(spi, SAM_QSPI_SR_OFFSET) & QSPI_INT_RDRF) != 0)
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{
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qspi_getreg(spi, SAM_QSPI_RDR_OFFSET);
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}
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}
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/****************************************************************************
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* Name: qspi_spi_lock
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*
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* Description:
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* On SPI buses where there are multiple devices, it will be necessary to
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* lock SPI to have exclusive access to the buses for a sequence of
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* transfers. The bus should be locked before the chip is selected. After
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* locking the SPI bus, the caller should then also call the setfrequency,
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* setbits, and setmode methods to make sure that the SPI is properly
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* configured for the device. If the SPI bus is being shared, then it
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* may have been left in an incompatible state.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* lock - true: Lock spi bus, false: unlock SPI bus
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static int qspi_spi_lock(struct spi_dev_s *dev, bool lock)
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{
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struct sam_spidev_s *spi = &g_spidev;
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int ret;
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spiinfo("lock=%d\n", lock);
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if (lock)
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{
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ret = nxsem_wait_uninterruptible(&spi->spisem);
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}
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else
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{
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ret = nxsem_post(&spi->spisem);
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}
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return ret;
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}
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/****************************************************************************
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* Name: qspi_spi_select
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*
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* Description:
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* This function does not actually set the chip select line. Rather, it
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* simply maps the device ID into a chip select number and retains that
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* chip select number for later use.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* frequency - The SPI frequency requested
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*
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* Returned Value:
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* Returns the actual frequency selected
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*
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****************************************************************************/
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static void qspi_spi_select(struct spi_dev_s *dev, uint32_t devid,
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bool selected)
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{
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struct sam_spidev_s *spi = &g_spidev;
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/* QSPI has just one CS so there is no need to perform any operation */
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spi->select(devid, selected);
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}
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/****************************************************************************
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* Name: qspi_spi_setfrequency
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*
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* Description:
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* Set the QSPI frequency.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* frequency - The QSPI frequency requested
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*
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* Returned Value:
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* Returns the actual frequency selected
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*
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****************************************************************************/
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static uint32_t qspi_spi_setfrequency(struct spi_dev_s *dev,
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uint32_t frequency)
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{
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struct sam_spics_s *spics = (struct sam_spics_s *)dev;
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struct sam_spidev_s *spi = &g_spidev;
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uint32_t actual;
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uint32_t scbr;
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uint32_t dlybct;
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uint32_t regval;
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spiinfo("frequency=%ld\n", frequency);
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/* Check if the requested frequency is the same as the frequency
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* selection
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*/
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if (spics->frequency == frequency)
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{
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/* We are already at this frequency. Return the actual. */
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return spics->actual;
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}
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/* Configure QSPI to a frequency as close as possible to the requested
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* frequency.
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*
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* QSCK frequency = QSPI_CLK / SCBR, or SCBR = QSPI_CLK / frequency
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*
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* Where SCBR can have the range 1 to 256 and the SCR register field holds
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* SCBR - 1. NOTE that a "ceiling" type of calculation is performed.
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* 'frequency' is treated as a not-to-exceed value.
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*/
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scbr = (frequency + SAM_QSPI_CLOCK - 1) / frequency;
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/* Make sure that the divider is within range */
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if (scbr < 1)
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{
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scbr = 1;
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}
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else if (scbr > 256)
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{
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scbr = 256;
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}
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/* Save the new SCBR value (minus one) */
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regval = qspi_getreg(spi, SAM_QSPI_SCR_OFFSET);
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regval &= ~(QSPI_SCR_SCBR_MASK | QSPI_SCR_DLYBS_MASK);
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regval |= (scbr - 1) << QSPI_SCR_SCBR_SHIFT;
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qspi_putreg(spi, regval, SAM_QSPI_SCR_OFFSET);
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/* DLYBCT: Delay Between Consecutive Transfers. This field defines the
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* delay between two consecutive transfers with the same peripheral without
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* removing the chip select. The delay is always inserted after each
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* transfer and before removing the chip select if needed.
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*
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* Delay Between Consecutive Transfers = (32 x DLYBCT) / SPI_CLK
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*
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* For a 5uS delay:
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*
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* DLYBCT = SPI_CLK * 0.000005 / 32 = SPI_CLK / 200000 / 32
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*/
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dlybct = SAM_QSPI_CLOCK / 200000 / 32;
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regval = qspi_getreg(spi, SAM_QSPI_MR_OFFSET);
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regval &= ~(QSPI_MR_DLYBCT_MASK);
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regval |= dlybct << QSPI_MR_DLYBCT_SHIFT;
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qspi_putreg(spi, regval, SAM_QSPI_MR_OFFSET);
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/* Calculate the new actual frequency */
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actual = SAM_QSPI_CLOCK / scbr;
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spiinfo("SCBR=%ld actual=%ld\n", scbr, actual);
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/* Save the frequency setting */
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spics->frequency = frequency;
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spics->actual = actual;
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spiinfo("Frequency %ld->%ld\n", frequency, actual);
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return actual;
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}
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/****************************************************************************
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* Name: qspi_spi_setmode
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*
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* Description:
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* Set the SPI mode. Optional. See enum spi_mode_e for mode definitions
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*
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* Input Parameters:
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* dev - Device-specific state data
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* mode - The SPI mode requested
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*
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* Returned Value:
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* none
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*
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****************************************************************************/
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static void qspi_spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
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{
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struct sam_spics_s *spics = (struct sam_spics_s *)dev;
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struct sam_spidev_s *spi = &g_spidev;
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uint32_t regval;
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spiinfo("mode=%d\n", mode);
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/* Has the mode changed? */
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||||
if (mode != spics->mode)
|
||||
{
|
||||
/* Yes... Set the mode appropriately:
|
||||
*
|
||||
* MODE
|
||||
* SPI CPOL NCPHA
|
||||
* 0 0 1
|
||||
* 1 0 0
|
||||
* 2 1 1
|
||||
* 3 1 0
|
||||
*/
|
||||
|
||||
regval = qspi_getreg(spi, SAM_QSPI_SCR_OFFSET);
|
||||
regval &= ~(QSPI_SCR_CPOL | QSPI_SCR_CPHA);
|
||||
|
||||
switch (mode)
|
||||
{
|
||||
case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
|
||||
break;
|
||||
|
||||
case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
|
||||
regval |= QSPI_SCR_CPHA;
|
||||
break;
|
||||
|
||||
case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */
|
||||
regval |= QSPI_SCR_CPOL;
|
||||
break;
|
||||
|
||||
case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
|
||||
regval |= (QSPI_SCR_CPOL | QSPI_SCR_CPHA);
|
||||
break;
|
||||
|
||||
default:
|
||||
DEBUGASSERT(FALSE);
|
||||
return;
|
||||
}
|
||||
|
||||
qspi_putreg(spi, regval, SAM_QSPI_SCR_OFFSET);
|
||||
|
||||
/* Save the mode so that subsequent re-configurations will be faster */
|
||||
|
||||
spics->mode = mode;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: qspi_spi_setbits
|
||||
*
|
||||
* Description:
|
||||
* Set the number if bits per word.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* nbits - The number of bits requested
|
||||
*
|
||||
* Returned Value:
|
||||
* none
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void qspi_spi_setbits(struct spi_dev_s *dev, int nbits)
|
||||
{
|
||||
struct sam_spics_s *spics = (struct sam_spics_s *)dev;
|
||||
struct sam_spidev_s *spi = &g_spidev;
|
||||
uint32_t regval;
|
||||
|
||||
spiinfo("nbits=%d\n", nbits);
|
||||
DEBUGASSERT(nbits > 7 && nbits < 17);
|
||||
|
||||
/* Has the number of bits changed? */
|
||||
|
||||
if (nbits != spics->nbits)
|
||||
{
|
||||
/* Yes... Set number of bits appropriately */
|
||||
|
||||
regval = qspi_getreg(spi, SAM_QSPI_MR_OFFSET);
|
||||
regval &= ~QSPI_MR_NBBITS_MASK;
|
||||
regval |= QSPI_MR_NBBITS(nbits);
|
||||
qspi_putreg(spi, regval, SAM_QSPI_MR_OFFSET);
|
||||
|
||||
/* Save the selection so that subsequent re-configurations will be
|
||||
* faster.
|
||||
*/
|
||||
|
||||
spics->nbits = nbits;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: qspi_spi_send
|
||||
*
|
||||
* Description:
|
||||
* Exchange one word on SPI
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* wd - The word to send. the size of the data is determined by the
|
||||
* number of bits selected for the SPI interface.
|
||||
*
|
||||
* Returned Value:
|
||||
* response
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static uint32_t qspi_spi_send(struct spi_dev_s *dev, uint32_t wd)
|
||||
{
|
||||
struct sam_spics_s *spics = (struct sam_spics_s *)dev;
|
||||
if (spics->nbits <= 8)
|
||||
{
|
||||
uint8_t txbyte;
|
||||
uint8_t rxbyte;
|
||||
|
||||
txbyte = (uint8_t)wd;
|
||||
rxbyte = (uint8_t)0;
|
||||
qspi_spi_exchange(dev, &txbyte, &rxbyte, 1);
|
||||
|
||||
spiinfo("Sent %02x received %02x\n", txbyte, rxbyte);
|
||||
return (uint32_t)rxbyte;
|
||||
}
|
||||
else
|
||||
{
|
||||
uint16_t txword;
|
||||
uint16_t rxword;
|
||||
|
||||
txword = (uint16_t)wd;
|
||||
rxword = (uint16_t)0;
|
||||
qspi_spi_exchange(dev, &txword, &rxword, 1);
|
||||
|
||||
spiinfo("Sent %02x received %02x\n", txword, rxword);
|
||||
return (uint32_t)rxword;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: qspi_spi_exchange
|
||||
*
|
||||
* Description:
|
||||
* Exchange a block of data from SPI.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* txbuffer - A pointer to the buffer of data to be sent
|
||||
* rxbuffer - A pointer to the buffer in which to receive data
|
||||
* nwords - the length of data that to be exchanged in units of words.
|
||||
* The wordsize is determined by the number of bits-per-word
|
||||
* selected for the SPI interface. If nbits <= 8, the data is
|
||||
* packed into uint8_t's; if nbits >8, the data is packed into
|
||||
* uint16_t's
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void qspi_spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
|
||||
void *rxbuffer, size_t nwords)
|
||||
{
|
||||
struct sam_spics_s *spics = (struct sam_spics_s *)dev;
|
||||
struct sam_spidev_s *spi = &g_spidev;
|
||||
uint32_t data;
|
||||
uint16_t *rxptr16;
|
||||
uint16_t *txptr16;
|
||||
uint8_t *rxptr8;
|
||||
uint8_t *txptr8;
|
||||
|
||||
spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
|
||||
|
||||
/* Set up working pointers */
|
||||
|
||||
if (spics->nbits > 8)
|
||||
{
|
||||
rxptr16 = (uint16_t *)rxbuffer;
|
||||
txptr16 = (uint16_t *)txbuffer;
|
||||
rxptr8 = NULL;
|
||||
txptr8 = NULL;
|
||||
}
|
||||
else
|
||||
{
|
||||
rxptr16 = NULL;
|
||||
txptr16 = NULL;
|
||||
rxptr8 = (uint8_t *)rxbuffer;
|
||||
txptr8 = (uint8_t *)txbuffer;
|
||||
}
|
||||
|
||||
/* Make sure that any previous transfer is flushed from the hardware */
|
||||
|
||||
qspi_flush(spi);
|
||||
|
||||
/* Loop, sending each word in the user-provided data buffer.
|
||||
*
|
||||
* Note 1: Good SPI performance would require that we implement DMA
|
||||
* transfers!
|
||||
* Note 2: This loop might be made more efficient. Would logic
|
||||
* like the following improve the throughput? Or would it
|
||||
* just add the risk of overruns?
|
||||
*
|
||||
* Get word 1;
|
||||
* Send word 1; Now word 1 is "in flight"
|
||||
* nwords--;
|
||||
* for ( ; nwords > 0; nwords--)
|
||||
* {
|
||||
* Get word N.
|
||||
* Wait for TDRE meaning that word N-1 has moved to the shift
|
||||
* register.
|
||||
* Disable interrupts to keep the following atomic
|
||||
* Send word N. Now both work N-1 and N are "in flight"
|
||||
* Wait for RDRF meaning that word N-1 is available
|
||||
* Read word N-1.
|
||||
* Re-enable interrupts.
|
||||
* Save word N-1.
|
||||
* }
|
||||
* Wait for RDRF meaning that the final word is available
|
||||
* Read the final word.
|
||||
* Save the final word.
|
||||
*/
|
||||
|
||||
for (; nwords > 0; nwords--)
|
||||
{
|
||||
/* Get the data to send (0xff if there is no data source). */
|
||||
|
||||
if (txptr8)
|
||||
{
|
||||
data = (uint32_t)*txptr8++;
|
||||
}
|
||||
else if (txptr16)
|
||||
{
|
||||
data = (uint32_t)*txptr16++;
|
||||
}
|
||||
else
|
||||
{
|
||||
data = 0xffff;
|
||||
}
|
||||
|
||||
/* Wait for any previous data written to the TDR to be transferred
|
||||
* to the serializer.
|
||||
*/
|
||||
|
||||
while ((qspi_getreg(spi, SAM_QSPI_SR_OFFSET) & QSPI_INT_TDRE) == 0);
|
||||
|
||||
/* Write the data to transmitted to the Transmit Data Register (TDR) */
|
||||
|
||||
qspi_putreg(spi, data, SAM_QSPI_TDR_OFFSET);
|
||||
|
||||
/* Wait for the read data to be available in the RDR.
|
||||
* TODO: Data transfer rates would be improved using the RX FIFO
|
||||
* (and also DMA)
|
||||
*/
|
||||
|
||||
while ((qspi_getreg(spi, SAM_QSPI_SR_OFFSET) & QSPI_INT_RDRF) == 0);
|
||||
|
||||
/* Read the received data from the SPI Data Register. */
|
||||
|
||||
data = qspi_getreg(spi, SAM_QSPI_RDR_OFFSET);
|
||||
if (rxptr8)
|
||||
{
|
||||
*rxptr8++ = (uint8_t)data;
|
||||
}
|
||||
else if (rxptr16)
|
||||
{
|
||||
*rxptr16++ = (uint16_t)data;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: qspi_spi_sndblock
|
||||
*
|
||||
* Description:
|
||||
* Send a block of data on SPI
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* buffer - A pointer to the buffer of data to be sent
|
||||
* nwords - the length of data to send from the buffer in number of words.
|
||||
* The wordsize is determined by the number of bits-per-word
|
||||
* selected for the SPI interface. If nbits <= 8, the data is
|
||||
* packed into uint8_t's; if nbits >8, the data is packed into
|
||||
* uint16_t's
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_SPI_EXCHANGE
|
||||
static void qspi_spi_sndblock(struct spi_dev_s *dev, const void *buffer,
|
||||
size_t nwords)
|
||||
{
|
||||
/* spi_exchange can do this. */
|
||||
|
||||
qspi_spi_exchange(dev, buffer, NULL, nwords);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: qspi_spi_recvblock
|
||||
*
|
||||
* Description:
|
||||
* Revice a block of data from SPI
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* buffer - A pointer to the buffer in which to receive data
|
||||
* nwords - the length of data that can be received in the buffer in number
|
||||
* of words. The wordsize is determined by the number of
|
||||
* bits-per-word selected for the SPI interface. If nbits <= 8,
|
||||
* the data is packed into uint8_t's; if nbits >8, the data is
|
||||
* packed into uint16_t's
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void qspi_spi_recvblock(struct spi_dev_s *dev, void *buffer,
|
||||
size_t nwords)
|
||||
{
|
||||
/* spi_exchange can do this. */
|
||||
|
||||
qspi_spi_exchange(dev, NULL, buffer, nwords);
|
||||
}
|
||||
#endif /* CONFIG_SPI_EXCHANGE */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_qspi_spi_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected SPI port in master mode
|
||||
*
|
||||
* Input Parameters:
|
||||
* cs - Chip select number (identifying the "logical" SPI port)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct spi_dev_s *sam_qspi_spi_initialize(int intf)
|
||||
{
|
||||
FAR struct sam_spidev_s *spi;
|
||||
FAR struct sam_spics_s *spics;
|
||||
irqstate_t flags;
|
||||
uint32_t regval;
|
||||
|
||||
/* The supported SAM parts have only a single QSPI port */
|
||||
|
||||
spiinfo("intf: %d\n", intf);
|
||||
DEBUGASSERT(intf >= 0 && intf < SAMV7_NQSPI_SPI);
|
||||
|
||||
/* Allocate a new state structure for this chip select. */
|
||||
|
||||
spics = (struct sam_spics_s *)kmm_zalloc(sizeof(struct sam_spics_s));
|
||||
if (!spics)
|
||||
{
|
||||
spierr("ERROR: Failed to allocate a chip select structure\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Select the SPI operations */
|
||||
|
||||
spics->spidev.ops = &g_spiops;
|
||||
|
||||
/* Get the SPI device structure associated with the chip select */
|
||||
|
||||
spi = &g_spidev;
|
||||
|
||||
/* Has the SPI hardware been initialized? */
|
||||
|
||||
if (!spi->initialized)
|
||||
{
|
||||
flags = enter_critical_section();
|
||||
sam_qspi_enableclk();
|
||||
|
||||
/* Configure multiplexed pins as connected on the board. Chip
|
||||
* select pins must be selected by board-specific logic.
|
||||
*/
|
||||
|
||||
sam_configgpio(GPIO_QSPI_IO0); /* MOSI */
|
||||
sam_configgpio(GPIO_QSPI_IO1); /* MISO */
|
||||
sam_configgpio(GPIO_QSPI_SCK);
|
||||
|
||||
/* Disable write protection */
|
||||
|
||||
qspi_putreg(spi, SAM_QSPI_WPCR_OFFSET, QSPI_WPCR_WPKEY);
|
||||
|
||||
/* Disable QSPI before configuring it */
|
||||
|
||||
qspi_putreg(spi, QSPI_CR_QSPIDIS, SAM_QSPI_CR_OFFSET);
|
||||
|
||||
/* Execute a software reset of the QSPI (twice) */
|
||||
|
||||
qspi_putreg(spi, QSPI_CR_SWRST, SAM_QSPI_CR_OFFSET);
|
||||
qspi_putreg(spi, QSPI_CR_SWRST, SAM_QSPI_CR_OFFSET);
|
||||
leave_critical_section(flags);
|
||||
|
||||
/* Configure the QSPI mode register - select SPI mode */
|
||||
|
||||
qspi_putreg(spi, QSPI_MR_SPI, SAM_QSPI_MR_OFFSET);
|
||||
|
||||
/* And enable the SPI */
|
||||
|
||||
qspi_putreg(spi, QSPI_CR_QSPIEN, SAM_QSPI_CR_OFFSET);
|
||||
up_mdelay(20);
|
||||
|
||||
/* Flush any pending transfers */
|
||||
|
||||
qspi_getreg(spi, SAM_QSPI_SR_OFFSET);
|
||||
qspi_getreg(spi, SAM_QSPI_RDR_OFFSET);
|
||||
|
||||
/* Initialize the SPI semaphore that enforces mutually exclusive
|
||||
* access to the SPI registers.
|
||||
*/
|
||||
|
||||
nxsem_init(&spi->spisem, 0, 1);
|
||||
spi->escape_lastxfer = false;
|
||||
spi->initialized = true;
|
||||
}
|
||||
|
||||
/* Set to mode=0 and nbits=8 and impossible frequency. The SPI will only
|
||||
* be reconfigured if there is a change.
|
||||
*/
|
||||
|
||||
regval = qspi_getreg(spi, SAM_QSPI_SCR_OFFSET);
|
||||
regval &= ~(QSPI_SCR_CPOL | QSPI_SCR_CPHA);
|
||||
qspi_putreg(spi, regval, SAM_QSPI_SCR_OFFSET);
|
||||
spics->mode = 0;
|
||||
|
||||
regval = qspi_getreg(spi, SAM_QSPI_MR_OFFSET);
|
||||
regval |= QSPI_MR_NBBITS_8BIT;
|
||||
qspi_putreg(spi, regval, SAM_QSPI_MR_OFFSET);
|
||||
spics->nbits = 8;
|
||||
|
||||
spics->frequency = 0;
|
||||
|
||||
return &spics->spidev;
|
||||
}
|
||||
#endif /* CONFIG_SAMV7_QSPI_SPI_MODE */
|
||||
165
arch/arm/src/samv7/sam_qspi_spi.h
Normal file
165
arch/arm/src/samv7/sam_qspi_spi.h
Normal file
@ -0,0 +1,165 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/samv7/sam_qspi_spi.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMV7_SAM_QSPI_SPI_H
|
||||
#define __ARCH_ARM_SRC_SAMV7_SAM_QSPI_SPI_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "sam_config.h"
|
||||
|
||||
#ifdef CONFIG_SAMV7_QSPI_SPI_MODE
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_qspi_spi_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected QSPI port in SPI master mode
|
||||
*
|
||||
* Input Parameters:
|
||||
* intf - Interface number(must be zero)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct spi_dev_s;
|
||||
FAR struct spi_dev_s *sam_qspi_spi_initialize(int intf);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_qspi_select
|
||||
*
|
||||
* Description:
|
||||
* PIO chip select pins may be programmed by the board specific logic in
|
||||
* one of two different ways. First, the pins may be programmed as SPI
|
||||
* peripherals. In that case, the pins are completely controlled by the
|
||||
* SPI driver. This method still needs to be provided, but it may be only
|
||||
* a stub.
|
||||
*
|
||||
* An alternative way to program the PIO chip select pins is as a normal
|
||||
* PIO output. In that case, the automatic control of the CS pins is
|
||||
* bypassed and this function must provide control of the chip select.
|
||||
* NOTE: In this case, the PIO output pin does *not* have to be the
|
||||
* same as the NPCS pin normal associated with the chip select number.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - SPI device info
|
||||
* devid - Identifies the (logical) device
|
||||
* selected - TRUE:Select the device, FALSE:De-select the device
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_qspi_select(uint32_t devid, bool selected);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_qspi_status
|
||||
*
|
||||
* Description:
|
||||
* Return status information associated with the SPI device.
|
||||
*
|
||||
* Input Parameters:
|
||||
* devid - Identifies the (logical) device
|
||||
*
|
||||
* Returned Value:
|
||||
* Bit-encoded SPI status (see include/nuttx/spi/spi.h.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint8_t sam_qspi_status(FAR struct spi_dev_s *dev, uint32_t devid);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_qspi_cmddata
|
||||
*
|
||||
* Description:
|
||||
* Some SPI devices require an additional control to determine if the SPI
|
||||
* data being sent is a command or is data. If CONFIG_SPI_CMDDATA then
|
||||
* this function will be called to different be command and data transfers.
|
||||
*
|
||||
* This is often needed, for example, by LCD drivers. Some LCD hardware
|
||||
* may be configured to use 9-bit data transfers with the 9th bit
|
||||
* indicating command or data. That same hardware may be configurable,
|
||||
* instead, to use 8-bit data but to require an additional, board-
|
||||
* specific PIO control to distinguish command and data. This function
|
||||
* would be needed in that latter case.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - SPI device info
|
||||
* devid - Identifies the (logical) device
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SPI_CMDDATA
|
||||
int sam_qspi_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
|
||||
#endif /* CONFIG_SPI_CMDDATA */
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_SAMV7_QSPI_SPI_MODE */
|
||||
#endif /* __ARCH_ARM_SRC_SAMV7_SAM_QSPI_SPI_H */
|
||||
Loading…
Reference in New Issue
Block a user