diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b43121be95..27e6fb13b7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -468,7 +468,6 @@ config ARCH_CHIP_STM32F7
 
 config ARCH_CHIP_STM32H7
 	bool "STMicro STM32 H7"
-	select ARCH_CORTEXM7
 	select ARCH_HAVE_MPU
 	select ARCH_HAVE_I2CRESET
 	select ARCH_HAVE_PROGMEM
@@ -479,11 +478,8 @@ config ARCH_CHIP_STM32H7
 	select ARCH_HAVE_TICKLESS
 	select ARCH_HAVE_TIMEKEEPING
 	---help---
-		STMicro STM32H7 architectures (ARM Cortex-M7).
-
-		BEWARE: This is a work-in-progress and not yet ready for general
-		usage.  See boards/arm/stm32/nucleo-h743zi/README.txt for the
-		current state of the port.
+		STMicro STM32H7 architectures (ARM Cortex-M7 or
+		dual ARM Cortex-M7 Cortex-M4).
 
 config ARCH_CHIP_STM32L4
 	bool "STMicro STM32 L4"
diff --git a/arch/arm/include/stm32h7/irq.h b/arch/arm/include/stm32h7/irq.h
index a6582a4b36..66dd6f1f93 100644
--- a/arch/arm/include/stm32h7/irq.h
+++ b/arch/arm/include/stm32h7/irq.h
@@ -72,7 +72,11 @@
 #elif defined(CONFIG_STM32H7_STM32H7B3XX)
 #  include <arch/stm32h7/stm32h7x3xx_irq.h>
 #elif defined(CONFIG_STM32H7_STM32H7X5XX)
-#  include <arch/stm32h7/stm32h7x5xx_irq.h>
+#  if CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
+#    include <arch/stm32h7/stm32h7x5xx_irq.h>
+#  else
+#    include <arch/stm32h7/stm32h7x5xx_cpu2_irq.h>
+#  endif
 #elif defined(CONFIG_STM32H7_STM32H7X7XX)
 #  include <arch/stm32h7/stm32h7x7xx_irq.h>
 #else
diff --git a/arch/arm/include/stm32h7/stm32h7x5xx_cpu2_irq.h b/arch/arm/include/stm32h7/stm32h7x5xx_cpu2_irq.h
new file mode 100644
index 0000000000..f564a9b891
--- /dev/null
+++ b/arch/arm/include/stm32h7/stm32h7x5xx_cpu2_irq.h
@@ -0,0 +1,210 @@
+/****************************************************************************
+ * arch/arm/include/stm32h7/stm32h7x5xx_cpu2_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through arch/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32H7_STM32H7X5XX_CPU2_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* IRQ numbers.
+ * The IRQ number corresponds vector number and hence map directly to bits
+ * in the NVIC.
+ * This does, however, waste several words of memory in the IRQ to handle
+ * mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15).  These common definitions can be
+ * found in the file nuttx/arch/arm/include/stm32h7/irq.h which includes
+ * this file
+ *
+ * External interrupts (vectors >= 16)
+ */
+
+#define STM32_IRQ_WWDG2        (STM32_IRQ_FIRST + 0)    /*  0: Window Watchdog interrupt */
+#define STM32_IRQ_PVDPVM       (STM32_IRQ_FIRST + 1)    /*  1: PVD through EXTI line detection interrupt */
+#define STM32_IRQ_RTC          (STM32_IRQ_FIRST + 2)    /*  2: RTC tamper, timestamp */
+#define STM32_IRQ_CSSLSE       (STM32_IRQ_FIRST + 2)    /*  2: CSS LSE */
+#define STM32_IRQ_RTCWKUP      (STM32_IRQ_FIRST + 3)    /*  3: RTC Wakeup interrupt through the EXTI line */
+#define STM32_IRQ_FLASH        (STM32_IRQ_FIRST + 4)    /*  4: Flash memory global interrupt */
+#define STM32_IRQ_RCC          (STM32_IRQ_FIRST + 5)    /*  5: RCC global interrupt */
+#define STM32_IRQ_EXTI0        (STM32_IRQ_FIRST + 6)    /*  6: EXTI Line 0 interrupt */
+#define STM32_IRQ_EXTI1        (STM32_IRQ_FIRST + 7)    /*  7: EXTI Line 1 interrupt */
+#define STM32_IRQ_EXTI2        (STM32_IRQ_FIRST + 8)    /*  8: EXTI Line 2 interrupt */
+#define STM32_IRQ_EXTI3        (STM32_IRQ_FIRST + 9)    /*  9: EXTI Line 3 interrupt */
+#define STM32_IRQ_EXTI4        (STM32_IRQ_FIRST + 10)   /* 10: EXTI Line 4 interrupt */
+#define STM32_IRQ_DMA1S0       (STM32_IRQ_FIRST + 11)   /* 11: DMA1 Stream0 global interrupt */
+#define STM32_IRQ_DMA1S1       (STM32_IRQ_FIRST + 12)   /* 12: DMA1 Stream1 global interrupt */
+#define STM32_IRQ_DMA1S2       (STM32_IRQ_FIRST + 13)   /* 13: DMA1 Stream2 global interrupt */
+#define STM32_IRQ_DMA1S3       (STM32_IRQ_FIRST + 14)   /* 14: DMA1 Stream3 global interrupt */
+#define STM32_IRQ_DMA1S4       (STM32_IRQ_FIRST + 15)   /* 15: DMA1 Stream4 global interrupt */
+#define STM32_IRQ_DMA1S5       (STM32_IRQ_FIRST + 16)   /* 16: DMA1 Stream5 global interrupt */
+#define STM32_IRQ_DMA1S6       (STM32_IRQ_FIRST + 17)   /* 17: DMA1 Stream6 global interrupt */
+#define STM32_IRQ_ADC12        (STM32_IRQ_FIRST + 18)   /* 18: ADC1 and ADC2 global interrupt */
+#define STM32_IRQ_FDCAN1_0     (STM32_IRQ_FIRST + 19)   /* 19: FDCAN1 Interrupt 0 */
+#define STM32_IRQ_FDCAN2_0     (STM32_IRQ_FIRST + 20)   /* 20: FDCAN2 Interrupt 0 */
+#define STM32_IRQ_FDCAN1_1     (STM32_IRQ_FIRST + 21)   /* 21: FDCAN1 Interrupt 1 */
+#define STM32_IRQ_FDCAN2_1     (STM32_IRQ_FIRST + 22)   /* 22: FDCAN2 Interrupt 1 */
+#define STM32_IRQ_EXTI95       (STM32_IRQ_FIRST + 23)   /* 23: EXTI Line[9:5] interrupts */
+#define STM32_IRQ_TIM1BRK      (STM32_IRQ_FIRST + 24)   /* 24: TIM1 break interrupt */
+#define STM32_IRQ_TIM1UP       (STM32_IRQ_FIRST + 25)   /* 25: TIM1 update interrupt */
+#define STM32_IRQ_TIM1TRGCOM   (STM32_IRQ_FIRST + 26)   /* 26: TIM1 trigger and commutation interrupts */
+#define STM32_IRQ_TIMCC        (STM32_IRQ_FIRST + 27)   /* 27: TIM1 capture / compare interrupt */
+#define STM32_IRQ_TIM2         (STM32_IRQ_FIRST + 28)   /* 28: TIM2 global interrupt */
+#define STM32_IRQ_TIM3         (STM32_IRQ_FIRST + 29)   /* 29: TIM3 global interrupt */
+#define STM32_IRQ_TIM4         (STM32_IRQ_FIRST + 30)   /* 30: TIM4 global interrupt */
+#define STM32_IRQ_I2C1EV       (STM32_IRQ_FIRST + 31)   /* 31: I2C1 event interrupt */
+#define STM32_IRQ_I2C1ER       (STM32_IRQ_FIRST + 32)   /* 32: I2C1 error interrupt */
+#define STM32_IRQ_I2C2EV       (STM32_IRQ_FIRST + 33)   /* 33: I2C2 event interrupt */
+#define STM32_IRQ_I2C2ER       (STM32_IRQ_FIRST + 34)   /* 34: I2C2 error interrupt */
+#define STM32_IRQ_SPI1         (STM32_IRQ_FIRST + 35)   /* 35: SPI1 global interrupt */
+#define STM32_IRQ_SPI2         (STM32_IRQ_FIRST + 36)   /* 36: SPI2 global interrupt */
+#define STM32_IRQ_USART1       (STM32_IRQ_FIRST + 37)   /* 37: USART1 global interrupt */
+#define STM32_IRQ_USART2       (STM32_IRQ_FIRST + 38)   /* 38: USART2 global interrupt */
+#define STM32_IRQ_USART3       (STM32_IRQ_FIRST + 39)   /* 39: USART3 global interrupt */
+#define STM32_IRQ_EXTI1510     (STM32_IRQ_FIRST + 40)   /* 40: EXTI Line[15:10] interrupts */
+#define STM32_IRQ_RTCALARM     (STM32_IRQ_FIRST + 41)   /* 41: RTC alarms (A and B) through EXTI Line interrupts */
+#define STM32_IRQ_RESERVED42   (STM32_IRQ_FIRST + 42)   /* 42: Reserved */
+#define STM32_IRQ_TIM8BRK      (STM32_IRQ_FIRST + 43)   /* 43: TIM8 break interrupt */
+#define STM32_IRQ_TIM12        (STM32_IRQ_FIRST + 43)   /* 43: TIM12 global interrupt */
+#define STM32_IRQ_TIM8UP       (STM32_IRQ_FIRST + 44)   /* 44: TIM8 update interrupt */
+#define STM32_IRQ_TIM13        (STM32_IRQ_FIRST + 44)   /* 44: TIM13 global interrupt */
+#define STM32_IRQ_TIM8TRGCOM   (STM32_IRQ_FIRST + 45)   /* 45: TIM8 trigger /commutation interrupt */
+#define STM32_IRQ_TIM14        (STM32_IRQ_FIRST + 45)   /* 45: TIM14 global interrupts */
+#define STM32_IRQ_TIM8CC       (STM32_IRQ_FIRST + 46)   /* 46: TIM8 capture / compare interrupts */
+#define STM32_IRQ_DMA1S7       (STM32_IRQ_FIRST + 47)   /* 47: DMA1 Stream7 global interrupt */
+#define STM32_IRQ_FMC          (STM32_IRQ_FIRST + 48)   /* 48: FMC global interrupt */
+#define STM32_IRQ_SDMMC1       (STM32_IRQ_FIRST + 49)   /* 49: SDMMC1 global interrupt */
+#define STM32_IRQ_TIM5         (STM32_IRQ_FIRST + 50)   /* 50: TIM5 global interrupt */
+#define STM32_IRQ_SPI3         (STM32_IRQ_FIRST + 51)   /* 51: SPI3 global interrupt */
+#define STM32_IRQ_UART4        (STM32_IRQ_FIRST + 52)   /* 52: UART4 global interrupt */
+#define STM32_IRQ_UART5        (STM32_IRQ_FIRST + 53)   /* 53: UART5 global interrupt */
+#define STM32_IRQ_TIM6         (STM32_IRQ_FIRST + 54)   /* 54: TIM6 global interrupt */
+#define STM32_IRQ_DAC1         (STM32_IRQ_FIRST + 54)   /* 54: DAC1 underrun error interrupt */
+#define STM32_IRQ_TIM7         (STM32_IRQ_FIRST + 55)   /* 55: TIM7 global interrupt */
+#define STM32_IRQ_DMA2S0       (STM32_IRQ_FIRST + 56)   /* 56: DMA2 Stream0 interrupt */
+#define STM32_IRQ_DMA2S1       (STM32_IRQ_FIRST + 57)   /* 57: DMA2 Stream1 interrupt */
+#define STM32_IRQ_DMA2S2       (STM32_IRQ_FIRST + 58)   /* 58: FMA2 Stream2 interrupt */
+#define STM32_IRQ_DMA2S3       (STM32_IRQ_FIRST + 59)   /* 59: DMA2 Stream3 interrupt */
+#define STM32_IRQ_DMA2S4       (STM32_IRQ_FIRST + 60)   /* 60: DMA2 Stream4 interrupt */
+#define STM32_IRQ_ETH          (STM32_IRQ_FIRST + 61)   /* 61: Ethernet global interrupt */
+#define STM32_IRQ_ETHWKUP      (STM32_IRQ_FIRST + 62)   /* 62: Ethernet wakeup through EXTI line interrupt */
+#define STM32_IRQ_FDCANCAL     (STM32_IRQ_FIRST + 63)   /* 63: CAN2TX interrupts */
+#define STM32_IRQ_RESERVED64   (STM32_IRQ_FIRST + 64)   /* 64: Reserved */
+#define STM32_IRQ_CM4SEND      (STM32_IRQ_FIRST + 65)   /* 64: Cortex-M4 Send event interrupt */
+#define STM32_IRQ_RESERVED66   (STM32_IRQ_FIRST + 66)   /* 66: Reserved */
+#define STM32_IRQ_RESERVED67   (STM32_IRQ_FIRST + 67)   /* 67: Reserved */
+#define STM32_IRQ_DMA2S5       (STM32_IRQ_FIRST + 68)   /* 68: DMA2 Stream5 interrupt */
+#define STM32_IRQ_DMA2S6       (STM32_IRQ_FIRST + 69)   /* 69: DMA2 Stream6 interrupt */
+#define STM32_IRQ_DMA2S7       (STM32_IRQ_FIRST + 70)   /* 70: DMA2 Stream7 interrupt */
+#define STM32_IRQ_USART6       (STM32_IRQ_FIRST + 71)   /* 71: USART6 global interrupt */
+#define STM32_IRQ_I2C3EV       (STM32_IRQ_FIRST + 72)   /* 72: I2C3 event interrupt */
+#define STM32_IRQ_I2C3ER       (STM32_IRQ_FIRST + 73)   /* 73: I2C3 error interrupt*/
+#define STM32_IRQ_OTGHS_EP1OUT (STM32_IRQ_FIRST + 74)   /* 74: OTG_HS out global interrupt */
+#define STM32_IRQ_OTGHS_EP1IN  (STM32_IRQ_FIRST + 75)   /* 75: OTG_HS in global interrupt */
+#define STM32_IRQ_OTGHS_WKUP   (STM32_IRQ_FIRST + 76)   /* 76: OTG_HS wakeup interrupt */
+#define STM32_IRQ_OTGHS        (STM32_IRQ_FIRST + 77)   /* 77: OTG_HS global interrupt */
+#define STM32_IRQ_DCMI         (STM32_IRQ_FIRST + 78)   /* 78: DCMI global interrupt */
+#define STM32_IRQ_CRYP         (STM32_IRQ_FIRST + 79)   /* 79: CRYP global interrupt */
+#define STM32_IRQ_HASH         (STM32_IRQ_FIRST + 80)   /* 80: HASH global interrupt */
+#define STM32_IRQ_RNG          (STM32_IRQ_FIRST + 80)   /* 80: RNG global interrupt */
+#define STM32_IRQ_FPU          (STM32_IRQ_FIRST + 81)   /* 81: CPU FPU */
+#define STM32_IRQ_UART7        (STM32_IRQ_FIRST + 82)   /* 82: UART7 global interrupt */
+#define STM32_IRQ_UART8        (STM32_IRQ_FIRST + 83)   /* 83: UART8 global interrupt */
+#define STM32_IRQ_SPI4         (STM32_IRQ_FIRST + 84)   /* 84: SPI4 global interrupt */
+#define STM32_IRQ_SPI5         (STM32_IRQ_FIRST + 85)   /* 85: SPI5 global interrupt */
+#define STM32_IRQ_SPI6         (STM32_IRQ_FIRST + 86)   /* 86: SPI6  global interrupt */
+#define STM32_IRQ_SAI1         (STM32_IRQ_FIRST + 87)   /* 87: SAI1  global interrupt */
+#define STM32_IRQ_LTDC         (STM32_IRQ_FIRST + 88)   /* 88: LCD-TFT global interrupt */
+#define STM32_IRQ_LTDCER       (STM32_IRQ_FIRST + 89)   /* 89: LCD-TFT error interrupt */
+#define STM32_IRQ_DMA2D        (STM32_IRQ_FIRST + 90)   /* 90: DMA2D global interrupt */
+#define STM32_IRQ_SAI2         (STM32_IRQ_FIRST + 91)   /* 91: SAI2 global interrupt */
+#define STM32_IRQ_QUADSPI      (STM32_IRQ_FIRST + 92)   /* 92: QuadSPI global interrupt */
+#define STM32_IRQ_LPTIM1       (STM32_IRQ_FIRST + 93)   /* 93: LPTIM1 global interrupt */
+#define STM32_IRQ_CEC          (STM32_IRQ_FIRST + 94)   /* 94: HDMI-CEC global interrupt */
+#define STM32_IRQ_I2C4EV       (STM32_IRQ_FIRST + 95)   /* 95: I2C4 event interrupt */
+#define STM32_IRQ_I2C4ER       (STM32_IRQ_FIRST + 96)   /* 96: I2C4 error interrupt */
+#define STM32_IRQ_SPDIF        (STM32_IRQ_FIRST + 97)   /* 97: SPDIFRX global interrupt */
+#define STM32_IRQ_OTGFS_EP1OUT (STM32_IRQ_FIRST + 98)   /* 98: OTG_FS out global interrupt */
+#define STM32_IRQ_OTGFS_EP1IN  (STM32_IRQ_FIRST + 99)   /* 99: OTG_FS in global interrupt */
+#define STM32_IRQ_OTGFS_WKUP   (STM32_IRQ_FIRST + 100)  /* 100: OTG_FS wakeup */
+#define STM32_IRQ_OTGFS        (STM32_IRQ_FIRST + 101)  /* 101: OTG_FS global interrupt */
+#define STM32_IRQ_DMAMUX1OV    (STM32_IRQ_FIRST + 102)  /* 102: DMAMUX1 overrun interrupt */
+#define STM32_IRQ_HRTIM1MST    (STM32_IRQ_FIRST + 103)  /* 103: HRTIM1 master timer interrupt */
+#define STM32_IRQ_HRTIM1TIMA   (STM32_IRQ_FIRST + 104)  /* 104: HRTIM1 timer A interrupt */
+#define STM32_IRQ_HRTIMTIMB    (STM32_IRQ_FIRST + 105)  /* 105: HRTIM1 timer B interrupt */
+#define STM32_IRQ_HRTIM1TIMC   (STM32_IRQ_FIRST + 106)  /* 106: HRTIM1 timer C interrupt */
+#define STM32_IRQ_HRTIM1TIMD   (STM32_IRQ_FIRST + 107)  /* 107: HRTIM1 timer D interrupt */
+#define STM32_IRQ_HRTIMTIME    (STM32_IRQ_FIRST + 108)  /* 108: HRTIM1 timer E interrupt */
+#define STM32_IRQ_HRTIM1FLT    (STM32_IRQ_FIRST + 109)  /* 109: HRTIM1 fault interrupt */
+#define STM32_IRQ_DFSDM1FLT0   (STM32_IRQ_FIRST + 110)  /* 110: DFSDM1 filter 0 interrupt */
+#define STM32_IRQ_DFSDM1FLT1   (STM32_IRQ_FIRST + 111)  /* 111: DFSDM1 filter 1 interrupt */
+#define STM32_IRQ_DFSDM1FLT2   (STM32_IRQ_FIRST + 112)  /* 112: DFSDM1 filter 2 interrupt */
+#define STM32_IRQ_DFSDM1FLT3   (STM32_IRQ_FIRST + 113)  /* 113: DFSDM1 filter 3 interrupt */
+#define STM32_IRQ_SAI3         (STM32_IRQ_FIRST + 114)  /* 114: SAI3 global interrupt */
+#define STM32_IRQ_SWPMI1       (STM32_IRQ_FIRST + 115)  /* 115: SWPMI global interrupt/wakeup */
+#define STM32_IRQ_TIM15        (STM32_IRQ_FIRST + 116)  /* 116: TIM15 global interrupt */
+#define STM32_IRQ_TIM16        (STM32_IRQ_FIRST + 117)  /* 117: TIM16 global interrupt */
+#define STM32_IRQ_TIM17        (STM32_IRQ_FIRST + 118)  /* 118: TIM17 global interrupt */
+#define STM32_IRQ_MDIOSWKUP    (STM32_IRQ_FIRST + 119)  /* 119: MDIOS wakeup */
+#define STM32_IRQ_MDIOS        (STM32_IRQ_FIRST + 120)  /* 120: MDIOS global interrupt */
+#define STM32_IRQ_JPEG         (STM32_IRQ_FIRST + 121)  /* 121: JPEG  global interrupt */
+#define STM32_IRQ_MDMA         (STM32_IRQ_FIRST + 122)  /* 122: MDMA */
+#define STM32_IRQ_JPEG         (STM32_IRQ_FIRST + 123)  /* 123: JPEG */
+#define STM32_IRQ_SDMMC2       (STM32_IRQ_FIRST + 124)  /* 124: SDMMC2 global interrupt */
+#define STM32_IRQ_RESERVED125  (STM32_IRQ_FIRST + 125)  /* 125: Reserved */
+#define STM32_IRQ_HSEM1        (STM32_IRQ_FIRST + 126)  /* 126: HSEM global interrupt 1 */
+#define STM32_IRQ_ADC3         (STM32_IRQ_FIRST + 127)  /* 127: ADC3 global interrupt */
+#define STM32_IRQ_DMAMUX2OVR   (STM32_IRQ_FIRST + 128)  /* 128: DMAMUX2 overrun interrupt */
+#define STM32_IRQ_BDMACH1      (STM32_IRQ_FIRST + 129)  /* 129: BDMA channel 1 interrupt */
+#define STM32_IRQ_BDMACH2      (STM32_IRQ_FIRST + 130)  /* 130: BDMA channel 2 interrupt */
+#define STM32_IRQ_BDMACH3      (STM32_IRQ_FIRST + 131)  /* 131: BDMA channel 3 interrupt */
+#define STM32_IRQ_BDMACH4      (STM32_IRQ_FIRST + 132)  /* 132: BDMA channel 4 interrupt */
+#define STM32_IRQ_BDMACH5      (STM32_IRQ_FIRST + 133)  /* 133: BDMA channel 5 interrupt */
+#define STM32_IRQ_BDMACH6      (STM32_IRQ_FIRST + 134)  /* 134: BDMA channel 6 interrupt */
+#define STM32_IRQ_BDMACH7      (STM32_IRQ_FIRST + 135)  /* 135: BDMA channel 7 interrupt */
+#define STM32_IRQ_BDMACH8      (STM32_IRQ_FIRST + 136)  /* 136: BDMA channel 8 interrupt */
+#define STM32_IRQ_COMP         (STM32_IRQ_FIRST + 137)  /* 137: COMP1 and COMP2 exti_comp1_wkup global interrupt */
+#define STM32_IRQ_LPTIM2       (STM32_IRQ_FIRST + 138)  /* 138: LPTIM2 timer interrupt */
+#define STM32_IRQ_LPTIM3       (STM32_IRQ_FIRST + 139)  /* 139: LPTIM2 timer interrupt */
+#define STM32_IRQ_LPTIM4       (STM32_IRQ_FIRST + 140)  /* 140: LPTIM2 timer interrupt */
+#define STM32_IRQ_LPTIM5       (STM32_IRQ_FIRST + 141)  /* 141: LPTIM2 timer interrupt */
+#define STM32_IRQ_LPUART       (STM32_IRQ_FIRST + 142)  /* 142: LPUART global interrupt */
+#define STM32_IRQ_WWDG1RST     (STM32_IRQ_FIRST + 143)  /* 143: Window Watchdog 1 interrupt */
+#define STM32_IRQ_CRS          (STM32_IRQ_FIRST + 144)  /* 144: Clock Recovery System global interrupt */
+#define STM32_IRQ_ECC          (STM32_IRQ_FIRST + 145)  /* 145: ECC */
+#define STM32_IRQ_SAI4         (STM32_IRQ_FIRST + 146)  /* 146: SAI4  global interrupt */
+#define STM32_IRQ_RESERVED147  (STM32_IRQ_FIRST + 147)  /* 147: Reserved */
+#define STM32_IRQ_HOLDCORE     (STM32_IRQ_FIRST + 148)  /* CPUx hold */
+#define STM32_IRQ_WKUP         (STM32_IRQ_FIRST + 149)  /* 149: WKUP1 to WKUP6 pins */
+
+#define STM32_IRQ_NEXTINTS     150
+#define NR_IRQS                (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
+
+#endif /* __ARCH_ARM_INCLUDE_STM32H7_STM32H7X5XX_CPU2_IRQ_H */
diff --git a/arch/arm/include/stm32h7/stm32h7x5xx_irq.h b/arch/arm/include/stm32h7/stm32h7x5xx_irq.h
index 539a064c5d..238ef7a55f 100644
--- a/arch/arm/include/stm32h7/stm32h7x5xx_irq.h
+++ b/arch/arm/include/stm32h7/stm32h7x5xx_irq.h
@@ -116,7 +116,7 @@
 #define STM32_IRQ_ETH          (STM32_IRQ_FIRST + 61)   /* 61: Ethernet global interrupt */
 #define STM32_IRQ_ETHWKUP      (STM32_IRQ_FIRST + 62)   /* 62: Ethernet wakeup through EXTI line interrupt */
 #define STM32_IRQ_FDCANCAL     (STM32_IRQ_FIRST + 63)   /* 63: CAN2TX interrupts */
-#define STM32_IRQ_RESERVED64   (STM32_IRQ_FIRST + 64)   /* 64: Reserved */
+#define STM32_IRQ_CM7SEND      (STM32_IRQ_FIRST + 64)   /* 64: Cortex-M7 Send event interrupt */
 #define STM32_IRQ_RESERVED65   (STM32_IRQ_FIRST + 65)   /* 65: Reserved */
 #define STM32_IRQ_RESERVED66   (STM32_IRQ_FIRST + 66)   /* 66: Reserved */
 #define STM32_IRQ_RESERVED67   (STM32_IRQ_FIRST + 67)   /* 67: Reserved */
@@ -176,9 +176,9 @@
 #define STM32_IRQ_MDIOS        (STM32_IRQ_FIRST + 120)  /* 120: MDIOS global interrupt */
 #define STM32_IRQ_JPEG         (STM32_IRQ_FIRST + 121)  /* 121: JPEG  global interrupt */
 #define STM32_IRQ_MDMA         (STM32_IRQ_FIRST + 122)  /* 122: MDMA */
-#define STM32_IRQ_RESERVED123  (STM32_IRQ_FIRST + 123)  /* 123: Reserved */
+#define STM32_IRQ_JPEG         (STM32_IRQ_FIRST + 123)  /* 123: JPEG */
 #define STM32_IRQ_SDMMC2       (STM32_IRQ_FIRST + 124)  /* 124: SDMMC2 global interrupt */
-#define STM32_IRQ_HSEM0        (STM32_IRQ_FIRST + 125)  /* 125: HSEM global interrupt 1 */
+#define STM32_IRQ_HSEM0        (STM32_IRQ_FIRST + 125)  /* 125: HSEM global interrupt 0 */
 #define STM32_IRQ_RESERVED126  (STM32_IRQ_FIRST + 126)  /* 126: Reserved */
 #define STM32_IRQ_ADC3         (STM32_IRQ_FIRST + 127)  /* 127: ADC3 global interrupt */
 #define STM32_IRQ_DMAMUX2OVR   (STM32_IRQ_FIRST + 128)  /* 128: DMAMUX2 overrun interrupt */
@@ -196,12 +196,12 @@
 #define STM32_IRQ_LPTIM4       (STM32_IRQ_FIRST + 140)  /* 140: LPTIM2 timer interrupt */
 #define STM32_IRQ_LPTIM5       (STM32_IRQ_FIRST + 141)  /* 141: LPTIM2 timer interrupt */
 #define STM32_IRQ_LPUART       (STM32_IRQ_FIRST + 142)  /* 142: LPUART global interrupt */
-#define STM32_IRQ_WWDG1RST     (STM32_IRQ_FIRST + 143)  /* 143: Window Watchdog interrupt */
+#define STM32_IRQ_WWDG2RST     (STM32_IRQ_FIRST + 143)  /* 143: Window Watchdog 2 interrupt */
 #define STM32_IRQ_CRS          (STM32_IRQ_FIRST + 144)  /* 144: Clock Recovery System global interrupt */
-#define STM32_IRQ_RESERVED145  (STM32_IRQ_FIRST + 145)  /* 145: Reserved */
+#define STM32_IRQ_ECC          (STM32_IRQ_FIRST + 145)  /* 145: ECC */
 #define STM32_IRQ_SAI4         (STM32_IRQ_FIRST + 146)  /* 146: SAI4  global interrupt */
 #define STM32_IRQ_RESERVED147  (STM32_IRQ_FIRST + 147)  /* 147: Reserved */
-#define STM32_IRQ_RESERVED148  (STM32_IRQ_FIRST + 148)  /* 148: Reserved */
+#define STM32_IRQ_HOLDCORE     (STM32_IRQ_FIRST + 148)  /* CPUx hold */
 #define STM32_IRQ_WKUP         (STM32_IRQ_FIRST + 149)  /* 149: WKUP1 to WKUP6 pins */
 
 #define STM32_IRQ_NEXTINTS     150
diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt
index 34ad2414b1..a57984670c 100644
--- a/arch/arm/src/stm32h7/CMakeLists.txt
+++ b/arch/arm/src/stm32h7/CMakeLists.txt
@@ -37,6 +37,10 @@ if(CONFIG_STM32H7_PROGMEM)
   list(APPEND SRCS stm32_flash.c)
 endif()
 
+if(CONFIG_ARCH_STM32H7_DUALCORE)
+  list(APPEND SRCS stm32_dualcore.c)
+endif()
+
 if(CONFIG_STM32H7_HSEM)
   list(APPEND SRCS stm32_hsem.c)
 endif()
diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig
index 9706d8ab4b..1346f9f826 100644
--- a/arch/arm/src/stm32h7/Kconfig
+++ b/arch/arm/src/stm32h7/Kconfig
@@ -148,7 +148,7 @@ config ARCH_CHIP_STM32H745BG
 	select STM32H7_FLASH_CONFIG_G
 	select STM32H7_IO_CONFIG_B
 	---help---
-		STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
+		Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM,
 		LQFP208
 
 config ARCH_CHIP_STM32H745BI
@@ -157,7 +157,7 @@ config ARCH_CHIP_STM32H745BI
 	select STM32H7_FLASH_CONFIG_I
 	select STM32H7_IO_CONFIG_B
 	---help---
-		STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
+		Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM,
 		LQFP208
 
 config ARCH_CHIP_STM32H745IG
@@ -166,7 +166,7 @@ config ARCH_CHIP_STM32H745IG
 	select STM32H7_FLASH_CONFIG_G
 	select STM32H7_IO_CONFIG_I
 	---help---
-		STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
+		Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM,
 		LQFP176 or UFBGA176
 
 config ARCH_CHIP_STM32H745II
@@ -175,7 +175,7 @@ config ARCH_CHIP_STM32H745II
 	select STM32H7_FLASH_CONFIG_I
 	select STM32H7_IO_CONFIG_I
 	---help---
-		STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
+		Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM,
 		LQFP176 or UFBGA176
 
 config ARCH_CHIP_STM32H745XG
@@ -184,7 +184,7 @@ config ARCH_CHIP_STM32H745XG
 	select STM32H7_FLASH_CONFIG_G
 	select STM32H7_IO_CONFIG_X
 	---help---
-		STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
+		Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM,
 		TFBGA240
 
 config ARCH_CHIP_STM32H745XI
@@ -193,7 +193,7 @@ config ARCH_CHIP_STM32H745XI
 	select STM32H7_FLASH_CONFIG_I
 	select STM32H7_IO_CONFIG_X
 	---help---
-		STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
+		Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM,
 		TFBGA240
 
 config ARCH_CHIP_STM32H745ZG
@@ -202,7 +202,7 @@ config ARCH_CHIP_STM32H745ZG
 	select STM32H7_FLASH_CONFIG_G
 	select STM32H7_IO_CONFIG_Z
 	---help---
-		STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM,
+		Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM,
 		LQFP144
 
 config ARCH_CHIP_STM32H745ZI
@@ -211,7 +211,7 @@ config ARCH_CHIP_STM32H745ZI
 	select STM32H7_FLASH_CONFIG_I
 	select STM32H7_IO_CONFIG_Z
 	---help---
-		STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM,
+		Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM,
 		LQFP144
 
 config ARCH_CHIP_STM32H747XI
@@ -339,15 +339,36 @@ config STM32H7_IO_CONFIG_Z
 	bool
 	default n
 
+config ARCH_STM32H7_DUALCORE
+	bool
+	default n
+	select STM32H7_HSEM if !STM32H7_CORTEXM4_DISABLED
+	select STM32H7_HAVE_CM4
+
+choice
+	prompt "STM32 H7 Core selection"
+	default ARCH_CHIP_STM32H7_CORTEXM7
+
+config ARCH_CHIP_STM32H7_CORTEXM7
+	bool "STM32H7 Cortex-M7 core"
+	select ARCH_CORTEXM7
+	select ARMV7M_HAVE_ICACHE
+	select ARMV7M_HAVE_DCACHE
+	select ARMV7M_HAVE_ITCM
+	select ARMV7M_HAVE_DTCM
+
+config ARCH_CHIP_STM32H7_CORTEXM4
+	bool "STM32H7 Cortex-M4 core"
+	depends on ARCH_STM32H7_DUALCORE
+	select ARCH_CORTEXM4
+
+endchoice # STM32 H7 Core selection
+
 config STM32H7_STM32H7X3XX
 	bool
 	default n
 	select ARCH_HAVE_FPU
 	select ARCH_HAVE_DPFPU
-	select ARMV7M_HAVE_ICACHE
-	select ARMV7M_HAVE_DCACHE
-	select ARMV7M_HAVE_ITCM
-	select ARMV7M_HAVE_DTCM
 	select STM32H7_HAVE_LTDC
 	select STM32H7_HAVE_ETHERNET
 	select STM32H7_HAVE_FMC
@@ -362,10 +383,6 @@ config STM32H7_STM32H7B3XX
 	default n
 	select ARCH_HAVE_FPU
 	select ARCH_HAVE_DPFPU
-	select ARMV7M_HAVE_ICACHE
-	select ARMV7M_HAVE_DCACHE
-	select ARMV7M_HAVE_ITCM
-	select ARMV7M_HAVE_DTCM
 	select STM32H7_HAVE_ETHERNET
 	select STM32H7_HAVE_FMC
 	select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V
@@ -377,12 +394,9 @@ config STM32H7_STM32H7B3XX
 config STM32H7_STM32H7X5XX
 	bool
 	default n
+	select ARCH_STM32H7_DUALCORE
 	select ARCH_HAVE_FPU
 	select ARCH_HAVE_DPFPU
-	select ARMV7M_HAVE_ICACHE
-	select ARMV7M_HAVE_DCACHE
-	select ARMV7M_HAVE_ITCM
-	select ARMV7M_HAVE_DTCM
 	select STM32H7_HAVE_LTDC
 	select STM32H7_HAVE_ETHERNET
 	select STM32H7_HAVE_FMC
@@ -391,16 +405,14 @@ config STM32H7_STM32H7X5XX
 	select STM32H7_HAVE_SPI4
 	select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V
 	select STM32H7_HAVE_SPI6
+	select STM32H7_HAVE_SMPS
 
 config STM32H7_STM32H7X7XX
 	bool
 	default n
+	select ARCH_STM32H7_DUALCORE
 	select ARCH_HAVE_FPU
 	select ARCH_HAVE_DPFPU
-	select ARMV7M_HAVE_ICACHE
-	select ARMV7M_HAVE_DCACHE
-	select ARMV7M_HAVE_ITCM
-	select ARMV7M_HAVE_DTCM
 	select STM32H7_HAVE_LTDC
 	select STM32H7_HAVE_ETHERNET
 	select STM32H7_HAVE_FMC
@@ -492,6 +504,39 @@ config STM32H7_AXI_SRAM_CORRUPTION_WAR
 		AXI_TARG7_FN_MOD register. This will reduce the read issuing capability
 		of the SRAM to 1 at AXI interconnect level and avoid data corruption.
 
+if ARCH_STM32H7_DUALCORE
+
+if ARCH_CHIP_STM32H7_CORTEXM7
+
+config STM32H7_CORTEXM4_ENABLED
+	bool "Enable support for M4 core"
+	default y
+
+config STM32H7_CORTEXM7_BOOTM4
+	bool "Boot M4 core"
+	select STM32H7_SYSCFG
+	default y if STM32H7_CORTEXM4_ENABLED
+	default n
+
+endif
+
+config STM32H7_CORTEXM7_FLASH_SIZE
+	int "Flash reserved for M7 core"
+	default 1048576 if STM32_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4
+	default 2097152
+
+config STM32H7_CORTEXM7_SHMEM
+	bool
+	select ARM_MPU if ARCH_CHIP_STM32H7_CORTEXM7
+	default y if STM32H7_CORTEXM4_ENABLED
+	default n
+
+config STM32H7_SHMEM_SRAM3
+	bool "Use SRAM3 as shared memory"
+	depends on STM32H7_CORTEXM7_SHMEM
+	default y
+
+endif
 
 config STM32_HAVE_OTA_PARTITION
 	bool
@@ -538,6 +583,10 @@ menu "STM32H7 Peripheral Selection"
 # These "hidden" settings determine whether a peripheral option is available
 # for the selected MCU
 
+config STM32H7_HAVE_CM4
+	bool
+	default n
+
 config STM32H7_HAVE_LTDC
 	bool
 	default n
diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs
index aeaa171425..e9effafd0f 100644
--- a/arch/arm/src/stm32h7/Make.defs
+++ b/arch/arm/src/stm32h7/Make.defs
@@ -29,6 +29,10 @@ ifeq ($(CONFIG_STM32H7_PROGMEM),y)
 CHIP_CSRCS += stm32_flash.c
 endif
 
+ifeq ($(CONFIG_ARCH_STM32H7_DUALCORE),y)
+CHIP_CSRCS += stm32_dualcore.c
+endif
+
 ifeq ($(CONFIG_STM32H7_HSEM),y)
 CHIP_CSRCS += stm32_hsem.c
 endif
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h
index b1ab7e0d92..b3780a4ef8 100644
--- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h
@@ -60,10 +60,24 @@
 
 #define STM32_DTCRAM_BASE    0x20000000     /* 0x20000000-0x2001ffff: DTCM-RAM on TCM interface */
 #define STM32_AXISRAM_BASE   0x24000000     /* 0x24000000-0x247fffff: System AXI SRAM */
-#define STM32_SRAM1_BASE     0x30000000     /* 0x30000000-0x3001ffff: System SRAM1 */
-#define STM32_SRAM2_BASE     0x30020000     /* 0x30020000-0x3003ffff: System SRAM2 */
-#define STM32_SRAM3_BASE     0x3004c000     /* 0x30040000-0x30047fff: System SRAM3 */
-#define STM32_SRAM123_BASE   0x30000000     /* 0x30000000-0x30047fff: System SRAM123 */
+
+#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
+#  define STM32_SRAM1_BASE   0x30000000     /* 0x30000000-0x3001ffff: System SRAM1 */
+#  define STM32_SRAM2_BASE   0x30020000     /* 0x30020000-0x3003ffff: System SRAM2 */
+#  define STM32_SRAM3_BASE   0x30040000     /* 0x30040000-0x30047fff: System SRAM3 */
+#  define STM32_SRAM123_BASE 0x30000000     /* 0x30000000-0x30047fff: System SRAM123 */
+#else
+
+/* The AHB SRAMs of the D2 domain are also aliased to an address range below
+ * 0x2000 0000 to maintain the Cortex®-M4 Harvard architecture.
+ * For details, see RM0399 section "2.4 Embedded SRAM".
+ */
+
+#  define STM32_SRAM1_BASE   0x10000000     /* 0x10000000-0x1001ffff: System SRAM1 */
+#  define STM32_SRAM2_BASE   0x10020000     /* 0x10020000-0x1003ffff: System SRAM2 */
+#  define STM32_SRAM3_BASE   0x10040000     /* 0x10040000-0x10047fff: System SRAM3 */
+#  define STM32_SRAM123_BASE 0x10000000     /* 0x10000000-0x10047fff: System SRAM123 */
+#endif
 #define STM32_SRAM4_BASE     0x38000000     /* 0x38000000-0x3800ffff: System SRAM4 */
 #define STM32_BBSRAM_BASE    0x38800000     /* 0x38800000-0x38800fff: System Backup SRAM */
 
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
index b7545523b1..1c0de2d453 100644
--- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
@@ -812,6 +812,13 @@
 /* RCC Global Control register */
 
 #define RCC_GCR_WW1RSC                  (1 << 0)  /* Bit 0: WWDG1 reset scope control */
+#ifdef CONFIG_STM32H7_HAVE_CM4
+#  define RCC_GCR_WW2RSC                (1 << 1)  /* Bit 1: WWDG2 reset scope control */
+#endif
+#ifdef CONFIG_STM32H7_HAVE_CM4
+#  define RCC_GCR_BOOT_C1               (1 << 2)  /* Bit 2: Allows CPU1 to boot */
+#  define RCC_GCR_BOOT_C2               (1 << 3)  /* Bit 3: Allows CPU2 to boot */
+#endif
 
 /* TODO: D3 Autonomous mode register */
 
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h
index 7d1b82c7a5..cbfb85034e 100644
--- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h
@@ -54,6 +54,9 @@
 
 #define STM32_SYSCFG_UR_OFFSET(n)     (0x0300 + ((n) << 2))
 #define STM32_SYSCFG_UR0_OFFSET       0x0300 /* User register 0 */
+#ifdef CONFIG_STM32H7_HAVE_CM4
+#  define STM32_SYSCFG_UR1_OFFSET     0x0304 /* User register 2 */
+#endif
 #define STM32_SYSCFG_UR2_OFFSET       0x0308 /* User register 2 */
 #define STM32_SYSCFG_UR3_OFFSET       0x030c /* User register 3 */
 #define STM32_SYSCFG_UR4_OFFSET       0x0310 /* User register 4 */
@@ -86,6 +89,27 @@
 #define STM32_SYSCFG_CCCR             (STM32_SYSCFG_BASE + STM32_SYSCFG_CCCR_OFFSET)
 #define STM32_SYSCFG_PWRCR            (STM32_SYSCFG_BASE + STM32_SYSCFG_PWRCR_OFFSET)
 
+#define STM32_SYSCFG_UR0              (STM32_SYSCFG_BASE + STM32_SYSCFG_UR0_OFFSET)
+#ifdef CONFIG_STM32H7_HAVE_CM4
+#  define STM32_SYSCFG_UR1            (STM32_SYSCFG_BASE + STM32_SYSCFG_UR1_OFFSET)
+#endif
+#define STM32_SYSCFG_UR2              (STM32_SYSCFG_BASE + STM32_SYSCFG_UR2_OFFSET)
+#define STM32_SYSCFG_UR3              (STM32_SYSCFG_BASE + STM32_SYSCFG_UR3_OFFSET)
+#define STM32_SYSCFG_UR4              (STM32_SYSCFG_BASE + STM32_SYSCFG_UR4_OFFSET)
+#define STM32_SYSCFG_UR5              (STM32_SYSCFG_BASE + STM32_SYSCFG_UR5_OFFSET)
+#define STM32_SYSCFG_UR6              (STM32_SYSCFG_BASE + STM32_SYSCFG_UR6_OFFSET)
+#define STM32_SYSCFG_UR7              (STM32_SYSCFG_BASE + STM32_SYSCFG_UR7_OFFSET)
+#define STM32_SYSCFG_UR8              (STM32_SYSCFG_BASE + STM32_SYSCFG_UR8_OFFSET)
+#define STM32_SYSCFG_UR9              (STM32_SYSCFG_BASE + STM32_SYSCFG_UR9_OFFSET)
+#define STM32_SYSCFG_UR10             (STM32_SYSCFG_BASE + STM32_SYSCFG_UR10_OFFSET)
+#define STM32_SYSCFG_UR11             (STM32_SYSCFG_BASE + STM32_SYSCFG_UR11_OFFSET)
+#define STM32_SYSCFG_UR12             (STM32_SYSCFG_BASE + STM32_SYSCFG_UR12_OFFSET)
+#define STM32_SYSCFG_UR13             (STM32_SYSCFG_BASE + STM32_SYSCFG_UR13_OFFSET)
+#define STM32_SYSCFG_UR14             (STM32_SYSCFG_BASE + STM32_SYSCFG_UR14_OFFSET)
+#define STM32_SYSCFG_UR15             (STM32_SYSCFG_BASE + STM32_SYSCFG_UR15_OFFSET)
+#define STM32_SYSCFG_UR16             (STM32_SYSCFG_BASE + STM32_SYSCFG_UR16_OFFSET)
+#define STM32_SYSCFG_UR17             (STM32_SYSCFG_BASE + STM32_SYSCFG_UR17_OFFSET)
+
 /* Register Bitfield Definitions ********************************************/
 
 /* SYSCFG peripheral mode configuration register */
@@ -191,6 +215,14 @@
 /* REVISIT:  Missing bitfield definitions */
 
 #define SYSCFG_UR0_
+
+/* User register 1 */
+
+#ifdef CONFIG_STM32H7_HAVE_CM4
+#  define SYSCFG_UR1_BCM4            (1 << 0)  /* Bit 0: Boot Cortex-M4 */
+#  define SYSCFG_UR1_BCM7            (1 << 16) /* Bit 16: Boot Cortex-M7 */
+#endif
+
 #define SYSCFG_UR2_
 #define SYSCFG_UR3_
 #define SYSCFG_UR4_
diff --git a/arch/arm/src/stm32h7/stm32_allocateheap.c b/arch/arm/src/stm32h7/stm32_allocateheap.c
index ef458e7f1f..30531dc3eb 100644
--- a/arch/arm/src/stm32h7/stm32_allocateheap.c
+++ b/arch/arm/src/stm32h7/stm32_allocateheap.c
@@ -44,13 +44,21 @@
 #include "arm_internal.h"
 #include "hardware/stm32_memorymap.h"
 #include "stm32_mpuinit.h"
-#include "stm32_dtcm.h"
+
+#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
+#  include "stm32_dtcm.h"
+#endif
 #include "stm32_fmc.h"
 
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
 
+#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \
+    !defined(CONFIG_STM32H7_CORTEXM4_ENABLED)
+
+/* Configuration for M7 core and M4 core support disabled */
+
 /* At startup the kernel will invoke arm_addregion() so that platform code
  * may register available memories for use as part of system heap.
  * The global configuration option CONFIG_MM_REGIONS defines the maximal
@@ -100,11 +108,33 @@
 
 /* Set the start and end of the SRAMs */
 
-#define SRAM_START STM32_AXISRAM_BASE
-#define SRAM_END   (SRAM_START + STM32H7_SRAM_SIZE)
+#  define SRAM_START STM32_AXISRAM_BASE
+#  define SRAM_END   (SRAM_START + STM32H7_SRAM_SIZE)
 
-#define SRAM123_START STM32_SRAM123_BASE
-#define SRAM123_END   (SRAM123_START + STM32H7_SRAM123_SIZE)
+#  define SRAM123_START STM32_SRAM123_BASE
+#  define SRAM123_END   (SRAM123_START + STM32H7_SRAM123_SIZE)
+
+#elif defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \
+      defined(CONFIG_STM32H7_CORTEXM4_ENABLED)
+
+/* Configuration for M7 core and M4 core support enabled */
+
+#  define SRAM_START STM32_AXISRAM_BASE
+#  define SRAM_END   (SRAM_START + STM32H7_SRAM_SIZE)
+
+/* Exclude SRAM123 */
+
+#  undef SRAM123_START
+#  undef SRAM123_END
+
+#elif defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM4)
+
+/* Configuration for M4 core support enabled */
+
+#  define SRAM_START STM32_SRAM123_BASE
+#  define SRAM_END   (SRAM_START + STM32H7_SRAM123_SIZE - \
+                      STM32H7_SRAM3_SIZE)
+#endif
 
 #undef HAVE_SRAM4
 #if !defined(CONFIG_STM32H7_SRAM4EXCLUDE)
@@ -130,6 +160,12 @@
 #  undef HAVE_DTCM
 #endif
 
+#if defined(SRAM123_START) || defined(HAVE_SRAM4) ||                    \
+    defined(BOARD_SDRAM1_SIZE) || defined(BOARD_SDRAM2_SIZE) ||           \
+    defined(CONFIG_ARCH_HAVE_HEAP2)
+#  define HAVE_MMREGIONS 1
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -201,6 +237,7 @@ static inline void up_heap_color(void *start, size_t size)
 void up_allocate_heap(void **heap_start, size_t *heap_size)
 {
 #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+
   /* Get the unaligned size and position of the user-space heap.
    * This heap begins after the user-space .bss section at an offset
    * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
@@ -310,7 +347,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size)
  *
  ****************************************************************************/
 
-static void addregion (uintptr_t start, uint32_t size, const char *desc)
+static void addregion(uintptr_t start, uint32_t size, const char *desc)
 {
   /* Display memory ranges to help debugging */
 
@@ -321,7 +358,6 @@ static void addregion (uintptr_t start, uint32_t size, const char *desc)
   /* Allow user-mode access to the SRAM123 heap */
 
   stm32_mpu_uheap(start, size);
-
 #endif
 
   /* Colorize the heap for debug */
@@ -348,11 +384,13 @@ void arm_addregion(void)
 
   unsigned mm_regions = 1;
 
+#ifdef SRAM123_START
   if (mm_regions < CONFIG_MM_REGIONS)
     {
       addregion (SRAM123_START, SRAM123_END - SRAM123_START, "SRAM1,2,3");
       mm_regions++;
     }
+#endif
 
 #ifdef HAVE_SRAM4
   if (mm_regions < CONFIG_MM_REGIONS)
diff --git a/arch/arm/src/stm32h7/stm32_dualcore.c b/arch/arm/src/stm32h7/stm32_dualcore.c
new file mode 100644
index 0000000000..547905af2c
--- /dev/null
+++ b/arch/arm/src/stm32h7/stm32_dualcore.c
@@ -0,0 +1,179 @@
+/****************************************************************************
+ * arch/arm/src/stm32h7/stm32_dualcore.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "hardware/stm32_rcc.h"
+#include "hardware/stm32_hsem.h"
+#include "hardware/stm32_syscfg.h"
+
+#include "arm_internal.h"
+
+#include "stm32_dualcore.h"
+#include "stm32_hsem.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Check CM4 core configuration */
+
+#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4
+#  if defined(CONFIG_ARMV7M_DCACHE) || defined(CONFIG_ARMV7M_DTCM) || \
+      defined(CONFIG_ARMV7M_ICACHE)
+#    error Invalid configuration for CM4 core
+#  endif
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#if (defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) &&  \
+     defined(CONFIG_STM32H7_CORTEXM4_ENABLED)) || \
+    defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM4)
+
+/****************************************************************************
+ * Name: stm32_cm4_boot
+ *
+ * Description:
+ *   Return true if CM4 was started at boot
+ *
+ ****************************************************************************/
+
+static bool stm32_cm4_boot(void)
+{
+  uint32_t regval = 0;
+
+  /* Make sure that SYSCFG is enabled */
+
+  regval = getreg32(STM32_RCC_APB4ENR);
+  regval |= RCC_APB4ENR_SYSCFGEN;
+  putreg32(regval, STM32_RCC_APB4ENR);
+
+  return (bool)(getreg32(STM32_SYSCFG_UR1) & SYSCFG_UR1_BCM4);
+}
+#endif
+
+#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4
+/****************************************************************************
+ * Name: stm32_cpu2sem_wait
+ ****************************************************************************/
+
+static void stm32_cpu2sem_wait(void)
+{
+  /* CM4 started at boot - wait for CM7 initialization done */
+
+  putreg32(RCC_AHB4ENR_HSEMEN, STM32_RCC_AHB4ENR);
+
+  /* Wait for CPU1 */
+
+  stm32_hsem_busywait_lock(CPU2_HOLD_HSEM);
+}
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \
+    defined(CONFIG_STM32H7_CORTEXM4_ENABLED)
+
+/****************************************************************************
+ * Name: stm32_cpu2sem_take
+ ****************************************************************************/
+
+static void stm32_cpu2sem_take(void)
+{
+  /* Take semaphore */
+
+  while (stm32_hsem_take(CPU2_HOLD_HSEM) == 0);
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \
+    defined(CONFIG_STM32H7_CORTEXM4_ENABLED)
+
+/****************************************************************************
+ * Name: stm32h7_start_cm4
+ *
+ * Description:
+ *   Start CM4 core
+ *
+ ****************************************************************************/
+
+void stm32h7_start_cm4(void)
+{
+  uint32_t regval = 0;
+
+  /* Get BCM4 bit */
+
+  regval = getreg32(STM32_RCC_APB4ENR);
+  regval |= RCC_APB4ENR_SYSCFGEN;
+  putreg32(regval, STM32_RCC_APB4ENR);
+
+  regval = getreg32(STM32_SYSCFG_UR1);
+
+  if (stm32_cm4_boot() == true)
+    {
+      /* CM4 started at boot - signal that CM7 initialization done */
+
+      stm32_cpu2sem_take();
+    }
+#ifdef CONFIG_STM32H7_CORTEXM7_BOOTM4
+  else
+    {
+      /* CM4 not started at boot - force CM4 boot */
+
+      getreg32(STM32_RCC_GCR);
+      regval |= RCC_GCR_BOOT_C1;
+      putreg32(regval, STM32_RCC_GCR);
+    }
+#endif
+}
+#endif
+
+#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4
+/****************************************************************************
+ * Name: stm32h7_waitfor_cm7
+ *
+ * Description:
+ *   Wait for CM7 core initialization
+ *
+ ****************************************************************************/
+
+void stm32h7_waitfor_cm7(void)
+{
+  if (stm32_cm4_boot() == true)
+    {
+      /* Wait for CM7 initialization done if we started at boot */
+
+      stm32_cpu2sem_wait();
+    }
+  else
+    {
+      /* CM4 boot forced by CM7 - initialization done */
+    }
+}
+#endif
diff --git a/arch/arm/src/stm32h7/stm32_dualcore.h b/arch/arm/src/stm32h7/stm32_dualcore.h
new file mode 100644
index 0000000000..3e78764669
--- /dev/null
+++ b/arch/arm/src/stm32h7/stm32_dualcore.h
@@ -0,0 +1,83 @@
+/****************************************************************************
+ * arch/arm/src/stm32h7/stm32_dualcore.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H7_STM32_DUALCORE_H
+#define __ARCH_ARM_SRC_STM32H7_STM32_DUALCORE_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Hardware semaphore used for cores synchronisation */
+
+#define CPU2_HOLD_HSEM (0)
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \
+    defined(CONFIG_STM32H7_CORTEXM4_ENABLED)
+
+/****************************************************************************
+ * Name: stm32h7_start_cm4
+ *
+ * Description:
+ *   Start CM4 core
+ *
+ ****************************************************************************/
+
+void stm32h7_start_cm4(void);
+#endif
+
+#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4
+/****************************************************************************
+ * Name: stm32h7_waitfor_cm7
+ *
+ * Description:
+ *   Wait for CM7 core initialization
+ *
+ ****************************************************************************/
+
+void stm32h7_waitfor_cm7(void);
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM_SRC_STM32H7_STM32_DUALCORE_H */
diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c
index f8f37257eb..00db1b23df 100644
--- a/arch/arm/src/stm32h7/stm32_start.c
+++ b/arch/arm/src/stm32h7/stm32_start.c
@@ -42,6 +42,10 @@
 #include "stm32_lowputc.h"
 #include "stm32_start.h"
 
+#ifdef CONFIG_ARCH_STM32H7_DUALCORE
+#  include "stm32_dualcore.h"
+#endif
+
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
@@ -108,6 +112,7 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
 void __start(void) noinstrument_function;
 #endif
 
+#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
 /****************************************************************************
  * Name: stm32_tcmenable
  *
@@ -157,6 +162,7 @@ static inline void stm32_tcmenable(void)
 #warning Missing logic
 #endif
 }
+#endif
 
 /****************************************************************************
  * Public Functions
@@ -182,11 +188,17 @@ void __start(void)
                    "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
 #endif
 
+#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4
+  /* Wait for CM7 initialization done */
+
+  stm32h7_waitfor_cm7();
+#endif
+
   /* If enabled reset the MPU */
 
   mpu_early_reset();
 
-/* Clear .bss.  We'll do this inline (vs. calling memset) just to be
+  /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
    * certain that there are no issues with the state of global variables.
    */
 
@@ -231,19 +243,23 @@ void __start(void)
   stm32_lowsetup();
   showprogress('A');
 
+#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
   /* Enable/disable tightly coupled memories */
 
   stm32_tcmenable();
+#endif
 
   /* Initialize onboard resources */
 
   stm32_boardinitialize();
   showprogress('B');
 
+#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
   /* Enable I- and D-Caches */
 
   up_enable_icache();
   up_enable_dcache();
+#endif
   showprogress('C');
 
 #if defined(CONFIG_SCHED_IRQMONITOR) || defined(CONFIG_SEGGER_SYSVIEW)
@@ -273,6 +289,15 @@ void __start(void)
   showprogress('\r');
   showprogress('\n');
 
+#if defined(CONFIG_ARCH_STM32H7_DUALCORE) && \
+    defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \
+    defined(CONFIG_STM32H7_CORTEXM4_ENABLED)
+
+  /* Start CM4 core after clock configration is done */
+
+  stm32h7_start_cm4();
+#endif
+
   nx_start();
 
   /* Shouldn't get here */