Add few more EHCI definitions
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Gregory Nutt
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07bd7c2168
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arch/arm/src/sama5/chip/sam_ehci.h
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arch/arm/src/sama5/chip/sam_ehci.h
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/****************************************************************************
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* arch/arm/src/sama5/chip/sam_ehci.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EHCI_H
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#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EHCI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/usb/ohci.h>
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#include "chip.h"
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#include "chip/sam_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* The SAMA5 supports 3 root hub ports */
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#define SAM_EHCI_NRHPORT 3
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/* Registers ****************************************************************/
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/* Traditionally, NuttX specifies register locations using individual
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* register offsets from a base address. That tradition is broken here and,
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* instead, register blocks are represented as structures. This is done here
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* because, in principle, EHCI operational register address may not be known
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* at compile time; the operational registers lie at an offset specified in
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* the 'caplength' byte of the Host Controller Capability Registers.
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*
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* However, for the case of the SAMA5 EHCI, we know apriori that the value
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* of 'caplength' is 0x10. We keep this structure, however, to faciltate
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* porting this driver to other environments where, perhaps, such knowledge
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* is not availaable.
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*/
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/* Host Controller Capability Registers */
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#define HCCR ((struct ehci_hccr_s *)SAM_UHPEHCI_VSECTION
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/* Host Controller Operational Registers */
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#define HCOR ((volatile struct ehci_hcor_s *)(SAM_UHPEHCI_VSECTION + 0x10)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EHCI_H */
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@ -33,8 +33,8 @@
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_USB_H
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#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_USB_H
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#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_OHCI_H
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#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_OHCI_H
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/****************************************************************************
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* Included Files
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@ -51,7 +51,7 @@
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****************************************************************************/
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/* The SAMA5 supports 3 root hub ports */
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#define SAM_USBHOST_NRHPORT 3
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#define SAM_OHCI_NRHPORT 3
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/* Register offsets *********************************************************/
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/* See nuttx/usb/ohci.h */
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@ -109,4 +109,4 @@
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* Public Functions
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_USB_H */
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#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_OHCI_H */
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@ -161,8 +161,8 @@
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* and one for the tail ED for each RHPort:
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*/
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#define SAMA5_OHCI_NEDS (CONFIG_SAMA5_OHCI_NEDS + SAM_USBHOST_NRHPORT)
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#define SAMA5_OHCI_NTDS (CONFIG_SAMA5_OHCI_NTDS + SAM_USBHOST_NRHPORT)
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#define SAMA5_OHCI_NEDS (CONFIG_SAMA5_OHCI_NEDS + SAM_OHCI_NRHPORT)
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#define SAMA5_OHCI_NTDS (CONFIG_SAMA5_OHCI_NTDS + SAM_OHCI_NRHPORT)
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/* TD delay interrupt value */
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@ -228,7 +228,7 @@ struct sam_ohci_s
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/* Root hub ports */
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struct sam_rhport_s rhport[SAM_USBHOST_NRHPORT];
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struct sam_rhport_s rhport[SAM_OHCI_NRHPORT];
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};
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/* The OCHI expects the size of an endpoint descriptor to be 16 bytes.
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@ -505,7 +505,7 @@ static void sam_checkreg(uint32_t addr, uint32_t val, bool iswrite)
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count = 0;
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prevwrite = iswrite;
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/* Show the new regisgter access */
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/* Show the new register access */
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sam_printreg(addr, val, iswrite);
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}
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@ -930,8 +930,8 @@ static void sam_setinttab(uint32_t value, unsigned int interval, unsigned int of
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/* Make sure that the modified table value is flushed to RAM */
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cp15_coherent_dcache(&g_hcca.inttbl[i],
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&g_hcca.inttbl[i] + sizeof(uint32_t) - 1);
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cp15_coherent_dcache((uintptr_t)&g_hcca.inttbl[i],
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(uintptr_t)&g_hcca.inttbl[i] + sizeof(uint32_t) - 1);
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}
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}
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#endif
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@ -1687,7 +1687,7 @@ static void sam_rhsc_interrupt(void)
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/* Handle root hub status change on each root port */
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for (rhpndx = 0; rhpndx < SAM_USBHOST_NRHPORT; rhpndx++)
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for (rhpndx = 0; rhpndx < SAM_OHCI_NRHPORT; rhpndx++)
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{
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rhport = &g_ohci.rhport[rhpndx];
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@ -2028,7 +2028,7 @@ static int sam_wait(FAR struct usbhost_connection_s *conn,
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{
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/* Check for a change in the connection state on any root hub port */
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for (rhpndx = 0; rhpndx < SAM_USBHOST_NRHPORT; rhpndx++)
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for (rhpndx = 0; rhpndx < SAM_OHCI_NRHPORT; rhpndx++)
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{
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/* Has the connection state changed on the RH port? */
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@ -2089,7 +2089,7 @@ static int sam_enumerate(FAR struct usbhost_connection_s *conn, int rhpndx)
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uint32_t regaddr;
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int ret;
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DEBUGASSERT(rhpndx >= 0 && rhpndx < SAM_USBHOST_NRHPORT);
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DEBUGASSERT(rhpndx >= 0 && rhpndx < SAM_OHCI_NRHPORT);
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rhport = &g_ohci.rhport[rhpndx];
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/* Are we connected to a device? The caller should have called the wait()
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@ -2179,7 +2179,7 @@ static int sam_ep0configure(FAR struct usbhost_driver_s *drvr, uint8_t funcaddr,
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struct sam_ed_s *edctrl;
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DEBUGASSERT(rhport &&
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funcaddr >= 0 && funcaddr <= SAM_USBHOST_NRHPORT &&
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funcaddr >= 0 && funcaddr <= SAM_OHCI_NRHPORT &&
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maxpacketsize < 2048);
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edctrl = rhport->ep0.ed;
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@ -3072,7 +3072,7 @@ FAR struct usbhost_connection_s *sam_ohci_initialize(int controller)
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/* Initialize the root hub port structures */
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for (i = 0; i < SAM_USBHOST_NRHPORT; i++)
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for (i = 0; i < SAM_OHCI_NRHPORT; i++)
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{
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struct sam_rhport_s *rhport = &g_ohci.rhport[i];
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@ -3153,7 +3153,7 @@ FAR struct usbhost_connection_s *sam_ohci_initialize(int controller)
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* connected. We need to set the initial connected state accordingly.
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*/
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for (i = 0; i < SAM_USBHOST_NRHPORT; i++)
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for (i = 0; i < SAM_OHCI_NRHPORT; i++)
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{
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regval = sam_getreg(SAM_USBHOST_RHPORTST(i));
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g_ohci.rhport[i].connected = ((regval & OHCI_RHPORTST_CCS) != 0);
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