Add few more EHCI definitions

This commit is contained in:
Gregory Nutt 2013-08-18 13:01:13 -06:00
parent 07bd7c2168
commit a6e6b4ba2d
3 changed files with 106 additions and 16 deletions

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@ -0,0 +1,90 @@
/****************************************************************************
* arch/arm/src/sama5/chip/sam_ehci.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EHCI_H
#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EHCI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/usb/ohci.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The SAMA5 supports 3 root hub ports */
#define SAM_EHCI_NRHPORT 3
/* Registers ****************************************************************/
/* Traditionally, NuttX specifies register locations using individual
* register offsets from a base address. That tradition is broken here and,
* instead, register blocks are represented as structures. This is done here
* because, in principle, EHCI operational register address may not be known
* at compile time; the operational registers lie at an offset specified in
* the 'caplength' byte of the Host Controller Capability Registers.
*
* However, for the case of the SAMA5 EHCI, we know apriori that the value
* of 'caplength' is 0x10. We keep this structure, however, to faciltate
* porting this driver to other environments where, perhaps, such knowledge
* is not availaable.
*/
/* Host Controller Capability Registers */
#define HCCR ((struct ehci_hccr_s *)SAM_UHPEHCI_VSECTION
/* Host Controller Operational Registers */
#define HCOR ((volatile struct ehci_hcor_s *)(SAM_UHPEHCI_VSECTION + 0x10)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EHCI_H */

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@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_USB_H
#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_USB_H
#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_OHCI_H
#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_OHCI_H
/****************************************************************************
* Included Files
@ -51,7 +51,7 @@
****************************************************************************/
/* The SAMA5 supports 3 root hub ports */
#define SAM_USBHOST_NRHPORT 3
#define SAM_OHCI_NRHPORT 3
/* Register offsets *********************************************************/
/* See nuttx/usb/ohci.h */
@ -109,4 +109,4 @@
* Public Functions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_USB_H */
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_OHCI_H */

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@ -161,8 +161,8 @@
* and one for the tail ED for each RHPort:
*/
#define SAMA5_OHCI_NEDS (CONFIG_SAMA5_OHCI_NEDS + SAM_USBHOST_NRHPORT)
#define SAMA5_OHCI_NTDS (CONFIG_SAMA5_OHCI_NTDS + SAM_USBHOST_NRHPORT)
#define SAMA5_OHCI_NEDS (CONFIG_SAMA5_OHCI_NEDS + SAM_OHCI_NRHPORT)
#define SAMA5_OHCI_NTDS (CONFIG_SAMA5_OHCI_NTDS + SAM_OHCI_NRHPORT)
/* TD delay interrupt value */
@ -228,7 +228,7 @@ struct sam_ohci_s
/* Root hub ports */
struct sam_rhport_s rhport[SAM_USBHOST_NRHPORT];
struct sam_rhport_s rhport[SAM_OHCI_NRHPORT];
};
/* The OCHI expects the size of an endpoint descriptor to be 16 bytes.
@ -505,7 +505,7 @@ static void sam_checkreg(uint32_t addr, uint32_t val, bool iswrite)
count = 0;
prevwrite = iswrite;
/* Show the new regisgter access */
/* Show the new register access */
sam_printreg(addr, val, iswrite);
}
@ -930,8 +930,8 @@ static void sam_setinttab(uint32_t value, unsigned int interval, unsigned int of
/* Make sure that the modified table value is flushed to RAM */
cp15_coherent_dcache(&g_hcca.inttbl[i],
&g_hcca.inttbl[i] + sizeof(uint32_t) - 1);
cp15_coherent_dcache((uintptr_t)&g_hcca.inttbl[i],
(uintptr_t)&g_hcca.inttbl[i] + sizeof(uint32_t) - 1);
}
}
#endif
@ -1687,7 +1687,7 @@ static void sam_rhsc_interrupt(void)
/* Handle root hub status change on each root port */
for (rhpndx = 0; rhpndx < SAM_USBHOST_NRHPORT; rhpndx++)
for (rhpndx = 0; rhpndx < SAM_OHCI_NRHPORT; rhpndx++)
{
rhport = &g_ohci.rhport[rhpndx];
@ -2028,7 +2028,7 @@ static int sam_wait(FAR struct usbhost_connection_s *conn,
{
/* Check for a change in the connection state on any root hub port */
for (rhpndx = 0; rhpndx < SAM_USBHOST_NRHPORT; rhpndx++)
for (rhpndx = 0; rhpndx < SAM_OHCI_NRHPORT; rhpndx++)
{
/* Has the connection state changed on the RH port? */
@ -2089,7 +2089,7 @@ static int sam_enumerate(FAR struct usbhost_connection_s *conn, int rhpndx)
uint32_t regaddr;
int ret;
DEBUGASSERT(rhpndx >= 0 && rhpndx < SAM_USBHOST_NRHPORT);
DEBUGASSERT(rhpndx >= 0 && rhpndx < SAM_OHCI_NRHPORT);
rhport = &g_ohci.rhport[rhpndx];
/* Are we connected to a device? The caller should have called the wait()
@ -2179,7 +2179,7 @@ static int sam_ep0configure(FAR struct usbhost_driver_s *drvr, uint8_t funcaddr,
struct sam_ed_s *edctrl;
DEBUGASSERT(rhport &&
funcaddr >= 0 && funcaddr <= SAM_USBHOST_NRHPORT &&
funcaddr >= 0 && funcaddr <= SAM_OHCI_NRHPORT &&
maxpacketsize < 2048);
edctrl = rhport->ep0.ed;
@ -3072,7 +3072,7 @@ FAR struct usbhost_connection_s *sam_ohci_initialize(int controller)
/* Initialize the root hub port structures */
for (i = 0; i < SAM_USBHOST_NRHPORT; i++)
for (i = 0; i < SAM_OHCI_NRHPORT; i++)
{
struct sam_rhport_s *rhport = &g_ohci.rhport[i];
@ -3153,7 +3153,7 @@ FAR struct usbhost_connection_s *sam_ohci_initialize(int controller)
* connected. We need to set the initial connected state accordingly.
*/
for (i = 0; i < SAM_USBHOST_NRHPORT; i++)
for (i = 0; i < SAM_OHCI_NRHPORT; i++)
{
regval = sam_getreg(SAM_USBHOST_RHPORTST(i));
g_ohci.rhport[i].connected = ((regval & OHCI_RHPORTST_CCS) != 0);