TMS570: Add system timer logic
This commit is contained in:
Gregory Nutt
parent
fa36531fee
commit
a76f2b853a
@ -137,53 +137,44 @@
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/* Register Bit-Field Definitions *******************************************************************/
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/* RTI Global Control Register */
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#define RTI_GCTRL_
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#define RTI_GCTRL_CNT0EN (1 << 0) /* Bit 0: Counter 0 enable */
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#define RTI_GCTRL_CNT1EN (1 << 1) /* Bit 1: Counter 1 enable */
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#define RTI_GCTRL_COS (1 << 15) /* Bit 15: Continue on suspend */
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/* RTI Capture Control Register */
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#define RTI_CAPCTRL_
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#define RTI_CAPCTRL_CAPCNTR0 (1 << 0) /* Bit 0: Capture counter 0 */
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#define RTI_CAPCTRL_CAPCNTR1 (1 << 1) /* Bit 1: Capture counter 1 */
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/* RTI Compare Control Register */
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#define RTI_COMPCTRL_
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/* RTI Free Running Counter 0 Register */
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#define RTI_FRC0_
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/* RTI Up Counter 0 Register */
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#define RTI_UC0_
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/* RTI Compare Up Counter 0 Register */
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#define RTI_CPUC0_
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/* RTI Capture Free Running Counter 0 Register */
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#define RTI_CAFRC0_
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/* RTI Capture Up Counter 0 Register */
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#define RTI_CAUC0_
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/* RTI Free Running Counter 1 Register */
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#define RTI_FRC1_
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/* RTI Up Counter 1 Register */
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#define RTI_UC1_
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/* RTI Compare Up Counter 1 Register */
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#define RTI_CPUC1_
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/* RTI Capture Free Running Counter 1 Register */
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#define RTI_CAFRC1_
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/* RTI Capture Up Counter 1 Register */
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#define RTI_CAUC1_
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/* RTI Compare 0 Register Section */
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#define RTI_COMP0_
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/* RTI Update Compare 0 Register */
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#define RTI_UDCP0_
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/* RTI Compare 1 Register */
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#define RTI_COMP1_
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/* RTI Update Compare 1 Register */
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#define RTI_UDCP1_
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/* RTI Compare 2 Register */
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#define RTI_COMP2_
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/* RTI Update Compare 2 Register */
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#define RTI_UDCP2_
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/* RTI Compare 3 Register */
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#define RTI_COMP3_
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/* RTI Update Compare 3 Register */
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#define RTI_UDCP3_
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/* RTI Set Interrupt Enable Register */
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#define RTI_SETINTENA_
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/* RTI Clear Interrupt Enable Register */
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#define RTI_CLEARINTENA_
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/* RTI Interrupt Flag Register */
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#define RTI_INTFLAG_
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#define RTI_COMPCTRL_COMPSEL0 (1 << 0) /* Bit 0: Compare select 0 */
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#define RTI_COMPCTRL_COMPSEL1 (1 << 4) /* Bit 4: Compare select 1 */
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#define RTI_COMPCTRL_COMPSEL2 (1 << 8) /* Bit 8: Compare select 2 */
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#define RTI_COMPCTRL_COMPSEL3 (1 << 12) /* Bit 12: Compare select 3 */
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/* RTI Free Running Counter 0/1 Register (32-bit counter value) */
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/* RTI Up Counter 0/1 Register (32-bit counter value) */
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/* RTI Compare Up Counter 0/1 Register (32-bit counter value) */
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/* RTI Capture Free Running Counter 0/1 Register (32-bit counter value) */
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/* RTI Capture Up Counter 0/1 Register (32-bit counter value) */
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/* RTI Compare 0/1/2/3 Register Section (32-bit counter value) */
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/* RTI Update Compare 0/1/2/3 Register (32-bit counter value) */
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/* RTI Set Interrupt Enable Register, RTI Clear Interrupt Enable Register, and
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* RTI Interrupt Flag Register
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*/
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#define RTI_INT0 (1 << 0) /* Bit 0: Compare interrupt 0 */
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#define RTI_INT1 (1 << 1) /* Bit 1: Compare interrupt 1 */
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#define RTI_INT2 (1 << 2) /* Bit 2: Compare interrupt 2 */
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#define RTI_INT3 (1 << 3) /* Bit 3: Compare interrupt 3 */
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#define RTI_TBINT (1 << 16) /* Bit 16: Timebase interrupt */
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#define RTI_OVL0INT (1 << 17) /* Bit 17: Free running counter 0 overflow interrupt */
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#define RTI_OVL1INT (1 << 18) /* Bit 18: Free running counter 1 overflow interrupt */
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#define RTI_ALLINTS 0x0007000f
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/* Digital Watchdog Control Register */
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#define RTI_DWDCTRL_
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/* Digital Watchdog Preload Register */
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@ -61,6 +61,50 @@
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#include <arch/board/board.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef BOARD_VCLK_DIVIDER
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# error BOARD_VCLK_DIVIDER is not defined
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#endif
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#if BOARD_VCLK_DIVIDER == 1
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# define SYS_CLKCNTL_VCLKR SYS_CLKCNTL_VCLKR_DIV1
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#elif BOARD_VCLK_DIVIDER == 2
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# define SYS_CLKCNTL_VCLKR SYS_CLKCNTL_VCLKR_DIV2
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#else
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# error Invalid value for BOARD_VCLK_DIVIDER
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#endif
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#ifndef BOARD_VCLK2_DIVIDER
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# error BOARD_VCLK2_DIVIDER is not defined
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#endif
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#if BOARD_VCLK2_DIVIDER == 1
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# define SYS_CLKCNTL_VCLKR2 SYS_CLKCNTL_VCLKR2_DIV1
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#elif BOARD_VCLK2_DIVIDER == 2
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# define SYS_CLKCNTL_VCLKR2 SYS_CLKCNTL_VCLKR_DIV2
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#else
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# error Invalid value for SYS_CLKCNTL_VCLKR2_DIV2
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#endif
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#ifndef BOARD_RTICLK_DIVIDER
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# error BOARD_RTICLK_DIVIDER is not defined
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#endif
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#if BOARD_RTICLK_DIVIDER == 1
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# define SYS_RCLKSRC_RTI1DIV SYS_RCLKSRC_RTI1DIV_DIV1
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#elif BOARD_RTICLK_DIVIDER == 2
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# define SYS_RCLKSRC_RTI1DIV SYS_RCLKSRC_RTI1DIV_DIV2
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#elif BOARD_RTICLK_DIVIDER == 4
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# define SYS_RCLKSRC_RTI1DIV SYS_RCLKSRC_RTI1DIV_DIV4
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#elif BOARD_RTICLK_DIVIDER == 78
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# define SYS_RCLKSRC_RTI1DIV SYS_RCLKSRC_RTI1DIV_DIV8
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#else
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# error Invalid value for SYS_CLKCNTL_VCLKR2_DIV2
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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@ -434,12 +478,12 @@ static void tms570_clocksrc_configure(void)
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regval = getreg32(TMS570_SYS_CLKCNTL);
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regval &= ~(SYS_CLKCNTL_VCLKR2_MASK | SYS_CLKCNTL_VCLKR_MASK);
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regval |= SYS_CLKCNTL_VCLKR2_DIV1 | SYS_CLKCNTL_VCLKR_DIV1;
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regval |= SYS_CLKCNTL_VCLKR2 | SYS_CLKCNTL_VCLKR;
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putreg32(regval, TMS570_SYS_CLKCNTL);
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/* Setup RTICLK1 and RTICLK2 clocks */
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regval = SYS_RCLKSRC_RTI1SRC_VCLK | SYS_RCLKSRC_RTI1DIV_DIV2;
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regval = SYS_RCLKSRC_RTI1SRC_VCLK | SYS_RCLKSRC_RTI1DIV;
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putreg32(regval, TMS570_SYS_RCLKSRC);
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/* Setup asynchronous peripheral clock sources for AVCLK1 */
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@ -137,6 +137,10 @@ void up_irqinitialize(void)
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putreg32((uint32_t)tms570_error_handler, TMS570_VIM_FBPARERR);
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/* Assign all interrupt requests to the VIM channel of the same value.
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* NOTE: Nothing need be done. That is the power-on default mapping.
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*/
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/* Assign all channels to IRQs */
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putreg32(0, TMS570_VIM_FIRQPR0);
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@ -184,27 +188,6 @@ void up_irqinitialize(void)
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#endif
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}
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/****************************************************************************
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* Name: tms570_vim_channel
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*
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* Description:
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* Allocate a VIM channel and assign it to the 'request'.
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*
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* Input Parameters:
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* request - The interrupt request to be mapped to a channel
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*
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* Returned Value:
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* One sucess, the allocated channel number is returned. A negated errno
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* value is returned on any failure.
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*
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****************************************************************************/
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int tms570_vim_channel(int request)
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{
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#warning Missing logic
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return -ENOSYS;
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}
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/****************************************************************************
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* Name: arm_decodeirq
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*
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@ -61,23 +61,6 @@ extern "C"
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: tms570_vim_channel
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*
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* Description:
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* Allocate a VIM channel and assign it to the 'request'.
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*
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* Input Parameters:
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* request - The interrupt request to be mapped to a channel
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*
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* Returned Value:
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* One sucess, the allocated channel number is returned. A negated errno
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* value is returned on any failure.
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*
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****************************************************************************/
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int tms570_vim_channel(int request);
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/****************************************************************************
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* Name: up_enable_fiq
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*
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@ -39,10 +39,160 @@
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <nuttx/arch.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip/tms570_rti.h"
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#include <arch/board/board.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* The input clock to the RTI is the RTICLK. The RTI source is always VCLK
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* which may be divided down by 2. The correct RTICLK frequency must be
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* provided by board.h file as BOARD_RTICLK_FREQUENCY.
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*/
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#ifndef BOARD_RTICLK_FREQUENCY
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# error BOARD_RTICLK_FREQUENCY not defined
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#endif
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/* Timing Calculations:
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*
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* FRC0CLK = RTICLK / (CPUC0 + 1) Hz
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* Tcount = 1 / FRC0CLK Seconds
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* = 1,000,000 / FRC0CLK Microseconds
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* CMP0 = Period / Tcount
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* = CONFIG_USEC_PER_TICK * FRC0CLK / 1,000,000
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* = CONFIG_USEC_PER_TICK * RTICLK / (CPUC0 + 1) / 1,000,000
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*
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* For Example:
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* VCLK = 80,000,000 Hz
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* RTICLK = VCLK / 2 Hz
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* = 40,000,000 Hz
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* CPUC0 = 39
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* FR0CLK = 1,000,000 Hz
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* Tcount = 1 Microsecond
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* CONFIG_USEC_PER_TICK = 10,000 Microseconds
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* CMP0 = 10,000 * 40,000,000 / 40 / 1,000,000
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* = 10, 000 = CONFIG_USEC_PER_TICK
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*/
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#if BOARD_RTICLK_FREQUENCY > 10000000
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/* Use FR0CLK = 1MHz with CPUC0 at least 9 */
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# define RTI_FRC0CLK (1000000)
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#elif BOARD_RTICLK_FREQUENCY > 5000000
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/* Use FR0CLK = 500KHz with CPUC0 at least 9 */
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# define RTI_FRC0CLK (500000)
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#elif BOARD_RTICLK_FREQUENCY > 1000000
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/* Use FR0CLK = 100KHz with CPUC0 at least 9 */
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# define RTI_FRC0CLK (100000)
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#else
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# error No logic for this value of RTICLK
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#endif
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/* CPUC0 = RTICLK / FRC0CLK - 1
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*
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* NOTES:
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* - The following calculation performs rounding.
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*/
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#define RTI_CPUC0 (((BOARD_RTICLK_FREQUENCY + RTI_FRC0CLK / 2) / RTI_FRC0CLK) - 1)
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/* CMP0 = CONFIG_USEC_PER_TICK * FRC0CLK / 1,000,000
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*
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* NOTES:
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* - The following calculation performs rounding.
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* - The following calculation avoids integer overflow by depending on
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* FRCLK being a multiple of 100,000
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*/
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#define RTI_CMP0 ((CONFIG_USEC_PER_TICK * (RTI_FRC0CLK / 100000) + 50) / 100)
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_timerisr
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*
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* Description:
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* The timer ISR will perform a variety of services for various portions
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* of the systems.
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*
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****************************************************************************/
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int up_timerisr(int irq, uint32_t *regs)
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{
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/* Cleear the RTI Compare 0 interrupts */
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putreg32(RTI_INT0, TMS570_RTI_INTFLAG);
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/* Process timer interrupt */
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sched_process_timer();
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return 0;
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}
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/****************************************************************************
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* Name: up_timer_initialize
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*
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* Description:
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* This function is called during start-up to initialize the timer
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* interrupt.
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*
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****************************************************************************/
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void up_timer_initialize(void)
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{
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/* Disable all RTI interrupts */
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up_disable_irq(TMS570_REQ_RTICMP0);
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putreg32(RTI_ALLINTS, TMS570_RTI_CLEARINTENA);
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/* Configure RTICOMP0 register and the RTIUDCP0 Register to initialize with
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* the calculated compare value.
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*/
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putreg32(RTI_CMP0, TMS570_RTI_COMP0);
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putreg32(RTI_CMP0, TMS570_RTI_UDCP0);
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/* Configure the FRC0CLK clock by setting the RTICPUC0 register to the
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* calculated value.
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*/
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putreg32(RTI_CMP0, TMS570_RTI_CPUC0);
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/* Initialize the free-running counter and the RTI up-counter */
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putreg32(0, TMS570_RTI_FRC0);
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putreg32(0, TMS570_RTI_UC0);
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/* Clear any pending interrupts */
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putreg32(RTI_ALLINTS, TMS570_RTI_COMP0);
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/* Enable the RTI Compare 0 interrupts (still disabled at the VIM) */
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putreg32(RTI_INT0, TMS570_RTI_SETINTENA);
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/* Enable counter 0 */
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putreg32(RTI_GCTRL_CNT0EN, TMS570_RTI_GCTRL);
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/* Attach the interrupt handler to the RTI Compare 0 interrupt */
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DEBUGVERIFY(irq_attach(TMS570_REQ_RTICMP0, (xcpt_t)up_timerisr));
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/* Enable RTI compare 0 interrupts at the VIM */
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up_enable_irq(TMS570_REQ_RTICMP0);
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}
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