Finish clocking logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3040 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
5f97fe706b
commit
a7840b28c0
arch/avr/src/at91uc3
@ -47,11 +47,24 @@
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#include "up_internal.h"
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#include "at91uc3_internal.h"
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#include "at91uc3_pm.h"
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#include "at91uc3_flashc.h"
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/**************************************************************************
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* Private Definitions
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**************************************************************************/
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#if defined(AVR32_CLOCK_OSC0) || \
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(defined (AVR32_CLOCK_PLL0) && defined(AVR32_CLOCK_PLL0_OSC0)) || \
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(defined (AVR32_CLOCK_PLL0) && defined(AVR32_CLOCK_PLL0_OSC0))
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# define NEED_OSC0
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#endif
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#if defined(AVR32_CLOCK_OSC1) || \
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(defined (AVR32_CLOCK_PLL0) && defined(AVR32_CLOCK_PLL0_OSC1)) || \
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(defined (AVR32_CLOCK_PLL1) && defined(AVR32_CLOCK_PLL0_OSC1))
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# define NEED_OSC1
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#endif
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/**************************************************************************
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* Private Types
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**************************************************************************/
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@ -104,11 +117,11 @@ static inline void up_enableosc32(void)
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* Name: up_enableosc0
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*
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* Description:
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* Initialiaze clock/PLL settings per the definitions in the board.h
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* file.
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* Initialiaze OSC0 settings per the definitions in the board.h file.
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*
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**************************************************************************/
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#ifdef NEED_OSC0
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static inline void up_enableosc0(void)
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{
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uint32_t regval;
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@ -128,7 +141,7 @@ static inline void up_enableosc0(void)
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#endif
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putreg32(regval, AVR32_PM_OSCCTRL0);
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/* Enable CLK 0 using the startup time provided in board.h. This startup time
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/* Enable OSC0 using the startup time provided in board.h. This startup time
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* is critical and depends on the characteristics of the crystal.
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*/
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@ -143,17 +156,229 @@ static inline void up_enableosc0(void)
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regval |= PM_MCCTRL_OSC0EN;
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putreg32(regval, AVR32_PM_MCCTRL);
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/* Wait for CLK0 to be ready */
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/* Wait for OSC0 to be ready */
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while ((getreg32(AVR32_PM_POSCSR) & PM_POSCSR_OSC0RDY) == 0);
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}
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#endif
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/**************************************************************************
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* Name: up_enableosc1
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*
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* Description:
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* Initialiaze OSC0 settings per the definitions in the board.h file.
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*
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**************************************************************************/
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#ifdef NEED_OSC1
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static inline void up_enableosc1(void)
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{
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uint32_t regval;
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/* Enable OSC1 in the correct crystal mode by setting the mode value in OSCCTRL1 */
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regval = getreg32(AVR32_PM_OSCCTRL1);
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regval &= ~PM_OSCCTRL_MODE_MASK;
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#if AVR32_FOSC1 < 900000
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regval |= PM_OSCCTRL_MODE_XTALp9; /* Crystal XIN 0.4-0.9MHz */
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#elif AVR32_FOSC1 < 3000000
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regval |= PM_OSCCTRL_MODE_XTAL3; /* Crystal XIN 0.9-3.0MHz */
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#elif AVR32_FOSC1 < 8000000
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regval |= PM_OSCCTRL_MODE_XTAL8; /* Crystal XIN 3.0-8.0MHz */
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#else
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regval |= PM_OSCCTRL_MODE_XTALHI; /* Crystal XIN above 8.0MHz */
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#endif
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putreg32(regval, AVR32_PM_OSCCTRL1);
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/* Enable OSC1 using the startup time provided in board.h. This startup time
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* is critical and depends on the characteristics of the crystal.
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*/
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regval = getreg32(AVR32_PM_OSCCTRL1);
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regval &= ~PM_OSCCTRL_STARTUP_MASK;
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regval |= (AVR32_OSC1STARTUP << PM_OSCCTRL_STARTUP_SHIFT);
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putreg32(regval, AVR32_PM_OSCCTRL1);
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/* Enable OSC1 */
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regval = getreg32(AVR32_PM_MCCTRL);
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regval |= PM_MCCTRL_OSC1EN;
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putreg32(regval, AVR32_PM_MCCTRL);
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/* Wait for OSC1 to be ready */
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while ((getreg32(AVR32_PM_POSCSR) & PM_POSCSR_OSC1RDY) == 0);
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}
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#endif
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/**************************************************************************
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* Name: up_enablepll0
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*
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* Description:
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* Initialiaze PLL0 settings per the definitions in the board.h file.
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*
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**************************************************************************/
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#ifdef AVR32_CLOCK_PLL0
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static inline void up_enableosc1(void)
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{
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/* Setup PLL0 */
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regval = (AVR32_PLL0_DIV << PM_PLL_PLLDIV_SHIFT) | (AVR32_PLL0_MUL << PM_PLL_PLLMUL_SHIFT) | (16 << PM_PLL_PLLCOUNT_SHIFT)
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/* Select PLL0/1 oscillator */
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#if AVR32_CLOCK_PLL_OSC1
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regval |= PM_PLL_PLLOSC;
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#endif
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putreg32(regval, AVR32_PM_PLL0);
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/* Set PLL0 options */
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regval = getreg32(AVR32_PM_PLL0);
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regval &= ~PM_PLL_PLLOPT_MASK
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#if AVR32_PLL0_FREQ < 160000000
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regval |= PM_PLL_PLLOPT_VCO;
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#endif
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#if AVR32_PLL0_DIV2 != 0
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regval |= PM_PLL_PLLOPT_XTRADIV;
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#endif
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#if AVR32_PLL0_WBWM != 0
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regval |= PM_PLL_PLLOPT_WBWDIS;
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#endif
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putreg32(regval, AVR32_PM_PLL0)
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/* Enable PLL0 */
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regval = getreg32(AVR32_PM_PLL0);
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regval |= PM_PLL_PLLEN;
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putreg32(regval, AVR32_PM_PLL0)
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/* Wait for PLL0 locked. */
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while ((getreg32(AVR32_PM_POSCSR) & PM_POSCSR_LOCK0) == 0);
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}
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#endif
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/**************************************************************************
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* Name: up_enablepll1
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*
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* Description:
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* Initialiaze PLL1 settings per the definitions in the board.h file.
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*
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**************************************************************************/
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#ifdef AVR32_CLOCK_PLL1
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static inline void up_enableosc1(void)
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{
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/* Setup PLL1 */
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regval = (AVR32_PLL1_DIV << PM_PLL_PLLDIV_SHIFT) | (AVR32_PLL1_MUL << PM_PLL_PLLMUL_SHIFT) | (16 << PM_PLL_PLLCOUNT_SHIFT)
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/* Select PLL0/1 oscillator */
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#if AVR32_CLOCK_PLL_OSC1
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regval |= PM_PLL_PLLOSC;
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#endif
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putreg32(regval, AVR32_PM_PLL1);
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/* Set PLL1 options */
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regval = getreg32(AVR32_PM_PLL1);
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regval &= ~PM_PLL_PLLOPT_MASK
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#if AVR32_PLL1_FREQ < 160000000
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regval |= PM_PLL_PLLOPT_VCO;
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#endif
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#if AVR32_PLL1_DIV2 != 0
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regval |= PM_PLL_PLLOPT_XTRADIV;
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#endif
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#if AVR32_PLL1_WBWM != 0
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regval |= PM_PLL_PLLOPT_WBWDIS;
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#endif
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putreg32(regval, AVR32_PM_PLL1)
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/* Enable PLL1 */
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regval = getreg32(AVR32_PM_PLL1);
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regval |= PM_PLL_PLLEN;
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putreg32(regval, AVR32_PM_PLL1)
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/* Wait for PLL1 locked. */
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while ((getreg32(AVR32_PM_POSCSR) & PM_POSCSR_LOCK1) == 0);
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}
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#endif
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/**************************************************************************
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* Name: up_clksel
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*
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* Description:
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* Configure derived clocks.
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*
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**************************************************************************/
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static inline void up_clksel(void)
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{
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uint32_t regval = 0;
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#if AVR32_CKSEL_CPUDIV != 0
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regval |= PM_CKSEL_CPUDIV;
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regval |= (AVR32_CKSEL_CPUDIV << PM_CKSEL_CPUSEL_SHIFT)
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#endif
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#if AVR32_CKSEL_HSBDIV != 0
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regval |= PM_CKSEL_HSBDIV;
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regval |= (AVR32_CKSEL_HSBDIV << PM_CKSEL_HSBSEL_SHIFT)
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#endif
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#if AVR32_CKSEL_PBADIV != 0
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regval |= PM_CKSEL_PBADIV;
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regval |= (AVR32_CKSEL_PBADIV << PM_CKSEL_PBASEL_SHIFT)
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#endif
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#if AVR32_CKSEL_PBBDIV != 0
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regval |= PM_CKSEL_PBBDIV;
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regval |= (AVR32_CKSEL_PBBDIV << PM_CKSEL_PBBSEL_SHIFT)
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#endif
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putreg32(regval, AVR32_PM_CKSEL);
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/* Wait for CLKRDY */
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while ((getreg32(AVR32_PM_POSCSR) & PM_POSCSR_CKRDY) == 0);
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}
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/**************************************************************************
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* Name: up_fws
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*
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* Description:
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* Setup FLASH wait states.
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*
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**************************************************************************/
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static void up_fws(uint32_t cpuclock)
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{
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uint32_t regval;
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regval = getreg32(AVR32_FLASHC_FCR);
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if (cpuclock > AVR32_FLASHC_FWS0_MAXFREQ)
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{
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regval |= FLASHC_FCR_FWS;
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}
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else
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{
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regval &= ~FLASHC_FCR_FWS;
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}
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putreg32(regval, AVR32_FLASHC_FCR);
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}
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/**************************************************************************
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* Name: up_mainclk
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*
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* Description:
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* Initialiaze clock/PLL settings per the definitions in the board.h
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* file.
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* Select the main clock.
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*
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**************************************************************************/
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@ -167,6 +392,41 @@ static inline void up_mainclk(uint32_t mcsel)
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putreg32(regval, AVR32_PM_MCCTRL);
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}
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/**************************************************************************
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* Name: up_usbclock
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*
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* Description:
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* Setup the USBB GCLK.
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*
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**************************************************************************/
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#ifdef CONFIG_USBDEV
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static inline void up_usbclock(void)
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{
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uint32_t regval = 0;
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#if defined(AVR32_CLOCK_USB_PLL0) || defined(AVR32_CLOCK_USB_PLL1)
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regval |= PM_GCCTRL_PLLSEL;
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#endif
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#if defined(AVR32_CLOCK_USB_OSC1) || defined(AVR32_CLOCK_USB_PLL1)
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regval |= PM_GCCTRL_OSCSEL;
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#endif
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#if AVR32_CLOCK_USB_DIV > 0
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u_avr32_pm_gcctrl.GCCTRL.diven = diven;
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u_avr32_pm_gcctrl.GCCTRL.div = div;
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#endif
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putreg32(regval, AVR32_PM_GCCTRL(AVR32_PM_GCLK_USBB))
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/* Enable USB GCLK */
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regval = getreg32(AVR32_PM_GCCTRL(AVR32_PM_GCLK_USBB))
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regval |= PM_GCCTRL_CEN;
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putreg32(regval, AVR32_PM_GCCTRL(AVR32_PM_GCLK_USBB))
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}
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#endif
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/**************************************************************************
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* Public Functions
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**************************************************************************/
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@ -186,19 +446,54 @@ void up_clkinitialize(void)
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up_enableosc32();
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#if defined(AVR32_CLOCK_OSC0)
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#ifdef NEED_OSC0
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/* Enable OSC0 using the settings in board.h */
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up_enableosc0();
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/* Set up FLASH wait states */
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up_fws(AVR32_FOSC0);
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/* Then switch the main clock to OSC0 */
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up_mainclk(PM_MCCTRL_MCSEL_OSC0);
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#endif
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#elif defined(AVR32_CLOCK_PLL0)
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# warning "Missing Logic"
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#else
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# error "No main clock"
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#ifdef NEED_OSC1
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/* Enable OSC1 using the settings in board.h */
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up_enableosc1();
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#endif
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#ifdef AVR32_CLOCK_PLL0
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/* Enable PLL0 using the settings in board.h */
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up_enablepll0();
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/* Set up FLASH wait states */
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up_fws(AVR32_CPU_CLOCK);
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/* Then switch the main clock to PLL0 */
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up_mainclk(PM_MCCTRL_MCSEL_PLL0);
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#endif
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#ifdef AVR32_CLOCK_PLL1
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/* Enable PLL1 using the settings in board.h */
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up_enablepll1();
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#endif
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/* Configure derived clocks */
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up_clksel();
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/* Set up the USBB GCLK */
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#ifdef CONFIG_USBDEV
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void up_usbclock();
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#endif
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}
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@ -56,11 +56,11 @@
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/* Register Addresses ***************************************************************/
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#define AVR32_FLASHC_FCR (AVR32_FLASHC_BASE+AVR32_FLASHC_FCR_OFFSET)
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#define AVR32_FLASHC_FCMD (AVR32_FLASHC_BASE+AVR32_FLASHC_FCMD_OFFSET)
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#define AVR32_FLASHC_FSR (AVR32_FLASHC_BASE+AVR32_FLASHC_FSR_OFFSET)
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#define AVR32_FLASHC_FGPFRHI (AVR32_FLASHC_BASE+AVR32_FLASHC_FGPFRHI_OFFSET)
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#define AVR32_FLASHC_FGPFRLO (AVR32_FLASHC_BASE+AVR32_FLASHC_FGPFRLO_OFFSET)
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#define AVR32_FLASHC_FCR (AVR32_HFLASHC_BASE+AVR32_FLASHC_FCR_OFFSET)
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#define AVR32_FLASHC_FCMD (AVR32_HFLASHC_BASE+AVR32_FLASHC_FCMD_OFFSET)
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#define AVR32_FLASHC_FSR (AVR32_HFLASHC_BASE+AVR32_FLASHC_FSR_OFFSET)
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#define AVR32_FLASHC_FGPFRHI (AVR32_HFLASHC_BASE+AVR32_FLASHC_FGPFRHI_OFFSET)
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#define AVR32_FLASHC_FGPFRLO (AVR32_HFLASHC_BASE+AVR32_FLASHC_FGPFRLO_OFFSET)
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/* Register Bit-field Definitions ***************************************************/
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@ -73,7 +73,6 @@
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/* Flash Command Register */
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#define FLASHC_FCMD_CMD_SHIFT (0) /* Bits 0-5: Command */
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#define FLASHC_FCMD_CMD_MASK (0x3f << FLASHC_FCMD_CMD_SHIFT)
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#define FLASHC_FCMD_PAGEN_SHIFT (8) /* Bits 8-23: Page number */
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@ -207,6 +206,13 @@
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#define FLASH_CMD_EUP 14 /* Erase User Page */
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#define FLASH_CMD_QPRUP 15 /* Quick Page Read User Page */
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/* Other constants ******************************************************************/
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/* Maximum CPU frequency for 0 and 1 FLASH wait states */
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#define AVR32_FLASHC_FWS0_MAXFREQ 33000000
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#define AVR32_FLASHC_FWS1_MAXFREQ 66000000
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/************************************************************************************
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* Public Types
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************************************************************************************/
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@ -65,7 +65,7 @@
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#define AVR32_PM_ISR_OFFSET 0x004c /* Interrupt Status Register */
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#define AVR32_PM_ICR_OFFSET 0x0050 /* Interrupt Clear Register */
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#define AVR32_PM_POSCSR_OFFSET 0x0054 /* Power and Oscillators Status Register */
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#define AVR32_PM_GCCTRL_OFFSET 0x0060 /* 0x0060-0x070 Generic Clock Control Register */
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#define AVR32_PM_GCCTRL_OFFSET(n) (0x0060+((n)<<2)) /* 0x0060-0x070 Generic Clock Control Register */
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#define AVR32_PM_RCCR_OFFSET 0x00c0 /* RC Oscillator Calibration Register */
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#define AVR32_PM_BGCR_OFFSET 0x00c4 /* Bandgap Calibration Register */
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#define AVR32_PM_VREGCR_OFFSET 0x00c8 /* Linear Regulator Calibration Register */
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@ -94,7 +94,7 @@
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#define AVR32_PM_ISR (AVR32_PM_BASE+AVR32_PM_ISR_OFFSET)
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#define AVR32_PM_ICR (AVR32_PM_BASE+AVR32_PM_ICR_OFFSET)
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#define AVR32_PM_POSCSR (AVR32_PM_BASE+AVR32_PM_POSCSR_OFFSET)
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#define AVR32_PM_GCCTRL (AVR32_PM_BASE+AVR32_PM_GCCTRL_OFFSET)
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#define AVR32_PM_GCCTRL(n) (AVR32_PM_BASE+AVR32_PM_GCCTRL_OFFSET(n))
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#define AVR32_PM_RCCR (AVR32_PM_BASE+AVR32_PM_RCCR_OFFSET)
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#define AVR32_PM_BGCR (AVR32_PM_BASE+AVR32_PM_BGCR_OFFSET)
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#define AVR32_PM_VREGCR (AVR32_PM_BASE+AVR32_PM_VREGCR_OFFSET)
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@ -311,6 +311,14 @@
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/* These registers contain a 32-bit value with no smaller bit-field */
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/* GCLK Allocation ******************************************************************/
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#define AVR32_PM_GCLK0 (0) /* GCLK0 pin */
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#define AVR32_PM_GCLK1 (1) /* GCLK2 pin */
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#define AVR32_PM_GCLK2 (2) /* GCLK2 pin */
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#define AVR32_PM_GCLK_USBB (3) /* USBB */
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#define AVR32_PM_GCLK_ABDAC (4) /* ABDAC */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
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Reference in New Issue
Block a user