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STM32 F7: Misc naming fixes

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This commit is contained in:
Gregory Nutt 2015-07-16 19:49:20 -06:00
parent 3583f8c1dc
commit a7a7ec8850
4 changed files with 10 additions and 11 deletions
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2
arch/arm/include/stm32f7/irq.h
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@ -78,7 +78,7 @@
#define STM32_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX)
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include <arch/stm32/stm32f74xx75xx_irq.h>
#elif
#else

10
arch/arm/src/stm32f7/Kconfig
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@ -14,31 +14,31 @@ choice
config ARCH_CHIP_STM32F745
bool "STM32F745xx"
select STM32F7_STM32F74xx
select STM32F7_STM32F74XX
---help---
STM32 F7 Cortex M7, 512 or 1024Kb FLASH, 335 (240++16+54) Kb SRAM
config ARCH_CHIP_STM32F746
bool "STM32F746xx"
select STM32F7_STM32F74xx
select STM32F7_STM32F74XX
select STM32F7_HAVE_LTDC
---help---
STM32 F7 Cortex M7, 512 or 1024Kb FLASH, 335 (240++16+54) Kb SRAM
config ARCH_CHIP_STM32F756
bool "STM32F756xx"
select STM32F7_STM32F75xx
select STM32F7_STM32F75XX
select STM32F7_HAVE_LTDC
---help---
STM32 F7 Cortex M7, 512 or 1024Kb FLASH, 335 (240++16+54) Kb SRAM
endchoice # STM32 F7 Chip Selection
config STM32F7_STM32F74xx
config STM32F7_STM32F74XX
bool
default n
config STM32F7_STM32F75xx
config STM32F7_STM32F75XX
bool
default n

4
arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h
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@ -165,7 +165,7 @@
#define STM32_GPIOJ_BASE 0x40022400 /* 0x40022400-0x400227ff: GPIOJ */
#define STM32_GPIOK_BASE 0x40022800 /* 0x40022800-0x40022bff: GPIOK */
#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */
#define STM32_RRC_BASE 0x40023800 /* 0x40023800-0x40023bff: RCC */
#define STM32_RCC_BASE 0x40023800 /* 0x40023800-0x40023bff: RCC */
#define STM32_FLASHIF_BASE 0x40023c00 /* 0x40023c00-0x40023fff: Flash interface */
#define STM32_BKPSRAM_BASE 0x40024000 /* 0x40024000-0x40024fff: BKPSRAM */
#define STM32_DMA1_BASE 0x40026000 /* 0x40026000-0x400263ff: DMA1 */
@ -188,7 +188,7 @@
#define STM32_FMCBANK2_BASE 0x70000000 /* 0x70000000-0x7fffffff: FMC bank 2 */
#define STM32_FMCBANK3_BASE 0x80000000 /* 0x80000000-0x8fffffff: FMC bank 3 */
#define STM32_FMCBANK4_BASE 0x90000000 /* 0x90000000-0x9fffffff: FMC bank 4 */
#define STM32_FMC_BASE 0xa0000000 /* 0xa0000000-0xa0000fff: FMC control registers */
#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xa0000fff: FMC control registers */
#define STM32_QUADSPI_BASE 0xa0001000 /* 0xa0001000-0xa0001fff: QuadSPI Control */
#define STM32_FMCBANK5_BASE 0xc0000000 /* 0xc0000000-0xcfffffff: FMC bank 5 */
#define STM32_FMCBANK6_BASE 0xd0000000 /* 0xd0000000-0xdfffffff: FMC bank 6 */

5
arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h
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@ -44,8 +44,7 @@
#include "stm32_gpio.h"
#if defined(CONFIG_STM32_STM32F745) || defined(CONFIG_STM32_STM32F746) || \
defined(CONFIG_STM32_STM32F756)
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
/************************************************************************************
* Pre-processor Definitions
@ -1179,5 +1178,5 @@
#define GPIO_UART8_RX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0)
#define GPIO_UART8_TX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
#endif /* CONFIG_STM32_STM32F745 || CONFIG_STM32_STM32F746 */
#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F74XX75XX_PINMAP_H */