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SAMA5D4: Completes PMC modifications for the SAMA5D4

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This commit is contained in:
Gregory Nutt 2014-06-09 07:55:51 -06:00
parent 895851314f
commit a7afdd8e0d
3 changed files with 6 additions and 12 deletions
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6
configs/sama5d4-ek/include/board_384mhz.h
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@ -55,7 +55,7 @@
* the PLLACK be a multiple of 48MHz. This setup results in a CPU clock of 384MHz.
*
* MAINOSC: Frequency = 12MHz (crystal)
* PLLA: PLL Divider = 1, Multiplier = 64 to generate PLLACK = 768MHz
* PLLA: PLL Multiplier = 64 to generate PLLACK = 768MHz
* Master Clock (MCK): Source = PLLACK/2, Prescalar = 1, MDIV = 3 to generate
* MCK = 128MHz
* CPU clock = 384MHz
@ -71,14 +71,12 @@
/* PLLA configuration.
*
* Divider = 1
* Multipler = 64
* Multipler = 64: PLLACK = 64 * 12MHz = 768MHz
*/
#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
#define BOARD_CKGR_PLLAR_OUT (0)
#define BOARD_CKGR_PLLAR_MUL (63 << PMC_CKGR_PLLAR_MUL_SHIFT)
#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
/* PMC master clock register settings.
*

6
configs/sama5d4-ek/include/board_396mhz.h
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@ -54,7 +54,7 @@
* CPU clock of 396MHz:
*
* MAINOSC: Frequency = 12MHz (crystal)
* PLLA: PLL Divider = 1, Multiplier = 66 to generate PLLACK = 792MHz
* PLLA: PLL Multiplier = 66 to generate PLLACK = 792MHz
* Master Clock (MCK): Source = PLLACK/2, Prescalar = 1, MDIV = 3 to generate
* MCK = 132MHz
* CPU clock = 396MHz
@ -70,14 +70,12 @@
/* PLLA configuration.
*
* Divider = 1
* Multipler = 66
* Multipler = 66: PLLACK = 66 * 12MHz = 792MHz
*/
#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
#define BOARD_CKGR_PLLAR_OUT (0)
#define BOARD_CKGR_PLLAR_MUL (65 << PMC_CKGR_PLLAR_MUL_SHIFT)
#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
/* PMC master clock register settings.
*

6
configs/sama5d4-ek/include/board_528mhz.h
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@ -53,7 +53,7 @@
* This is the configuration results in a CPU clock of 528MHz:
*
* MAINOSC: Frequency = 12MHz (crystal)
* PLLA: PLL Divider = 1, Multiplier = 43+1 to generate PLLACK = 528MHz
* PLLA: PLL Multiplier = 43+1 to generate PLLACK = 528MHz
* Master Clock (MCK): Source = PLLACK/1, Prescalar = 1, MDIV = 4 to generate
* MCK = 132MHz
* CPU clock = 528MHz
@ -69,14 +69,12 @@
/* PLLA configuration.
*
* Divider = 1
* Multipler = 43+1
* Multipler = 43+1: PLLACK = 44 * 12MHz = 528MHz
*/
#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
#define BOARD_CKGR_PLLAR_OUT (0)
#define BOARD_CKGR_PLLAR_MUL (43 << PMC_CKGR_PLLAR_MUL_SHIFT)
#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
/* PMC master clock register settings.
*