diff --git a/configs/sama5d4-ek/include/board_384mhz.h b/configs/sama5d4-ek/include/board_384mhz.h
index 91326ce62d..878c82222a 100644
--- a/configs/sama5d4-ek/include/board_384mhz.h
+++ b/configs/sama5d4-ek/include/board_384mhz.h
@@ -55,7 +55,7 @@
  * the PLLACK be a multiple of 48MHz.  This setup results in a CPU clock of 384MHz.
  *
  *   MAINOSC:  Frequency = 12MHz (crystal)
- *   PLLA: PLL Divider = 1, Multiplier = 64 to generate PLLACK = 768MHz
+ *   PLLA: PLL Multiplier = 64 to generate PLLACK = 768MHz
  *   Master Clock (MCK): Source = PLLACK/2, Prescalar = 1, MDIV = 3 to generate
  *     MCK      =  128MHz
  *     CPU clock = 384MHz
@@ -71,14 +71,12 @@
 
 /* PLLA configuration.
  *
- *   Divider = 1
- *   Multipler = 64
+ *   Multipler = 64: PLLACK = 64 * 12MHz = 768MHz
  */
 
 #define BOARD_CKGR_PLLAR_COUNT     (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
 #define BOARD_CKGR_PLLAR_OUT       (0)
 #define BOARD_CKGR_PLLAR_MUL       (63 << PMC_CKGR_PLLAR_MUL_SHIFT)
-#define BOARD_CKGR_PLLAR_DIV       PMC_CKGR_PLLAR_DIV_BYPASS
 
 /* PMC master clock register settings.
  *
diff --git a/configs/sama5d4-ek/include/board_396mhz.h b/configs/sama5d4-ek/include/board_396mhz.h
index 281463d561..a20527403d 100644
--- a/configs/sama5d4-ek/include/board_396mhz.h
+++ b/configs/sama5d4-ek/include/board_396mhz.h
@@ -54,7 +54,7 @@
  * CPU clock of 396MHz:
  *
  *   MAINOSC:  Frequency = 12MHz (crystal)
- *   PLLA: PLL Divider = 1, Multiplier = 66 to generate PLLACK = 792MHz
+ *   PLLA: PLL Multiplier = 66 to generate PLLACK = 792MHz
  *   Master Clock (MCK): Source = PLLACK/2, Prescalar = 1, MDIV = 3 to generate
  *     MCK      =  132MHz
  *     CPU clock = 396MHz
@@ -70,14 +70,12 @@
 
 /* PLLA configuration.
  *
- *   Divider = 1
- *   Multipler = 66
+ *   Multipler = 66: PLLACK = 66 * 12MHz = 792MHz
  */
 
 #define BOARD_CKGR_PLLAR_COUNT     (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
 #define BOARD_CKGR_PLLAR_OUT       (0)
 #define BOARD_CKGR_PLLAR_MUL       (65 << PMC_CKGR_PLLAR_MUL_SHIFT)
-#define BOARD_CKGR_PLLAR_DIV       PMC_CKGR_PLLAR_DIV_BYPASS
 
 /* PMC master clock register settings.
  *
diff --git a/configs/sama5d4-ek/include/board_528mhz.h b/configs/sama5d4-ek/include/board_528mhz.h
index d12f78b1f5..446a480ab2 100644
--- a/configs/sama5d4-ek/include/board_528mhz.h
+++ b/configs/sama5d4-ek/include/board_528mhz.h
@@ -53,7 +53,7 @@
  * This is the configuration results in a CPU clock of 528MHz:
  *
  *   MAINOSC:  Frequency = 12MHz (crystal)
- *   PLLA: PLL Divider = 1, Multiplier = 43+1 to generate PLLACK = 528MHz
+ *   PLLA: PLL Multiplier = 43+1 to generate PLLACK = 528MHz
  *   Master Clock (MCK): Source = PLLACK/1, Prescalar = 1, MDIV = 4 to generate
  *     MCK      =  132MHz
  *     CPU clock = 528MHz
@@ -69,14 +69,12 @@
 
 /* PLLA configuration.
  *
- *   Divider = 1
- *   Multipler = 43+1
+ *   Multipler = 43+1: PLLACK = 44 * 12MHz = 528MHz
  */
 
 #define BOARD_CKGR_PLLAR_COUNT     (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
 #define BOARD_CKGR_PLLAR_OUT       (0)
 #define BOARD_CKGR_PLLAR_MUL       (43 << PMC_CKGR_PLLAR_MUL_SHIFT)
-#define BOARD_CKGR_PLLAR_DIV       PMC_CKGR_PLLAR_DIV_BYPASS
 
 /* PMC master clock register settings.
  *