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stm32_pmw: fix pwm_stop() function to enable multiple PWM start and stop.

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This commit is contained in:
Daniel P. Carvalho 2021-08-04 14:56:05 -03:00 committed by Alan Carvalho de Assis
parent 5025fbef8d
commit a7be1c9a2e
1 changed files with 5 additions and 160 deletions
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165
arch/arm/src/stm32/stm32_pwm.c
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@ -4454,159 +4454,11 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
{
FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
irqstate_t flags = 0;
uint32_t resetbit = 0;
uint32_t regaddr = 0;
uint32_t regval = 0;
uint16_t outputs = 0;
int ret = OK;
pwminfo("TIM%u\n", priv->timid);
/* Determine which timer to reset */
switch (priv->timid)
{
#ifdef CONFIG_STM32_TIM1_PWM
case 1:
{
regaddr = TIMRCCRST_TIM1;
resetbit = TIMRST_TIM1;
break;
}
#endif
#ifdef CONFIG_STM32_TIM2_PWM
case 2:
{
regaddr = TIMRCCRST_TIM2;
resetbit = TIMRST_TIM2;
break;
}
#endif
#ifdef CONFIG_STM32_TIM3_PWM
case 3:
{
regaddr = TIMRCCRST_TIM3;
resetbit = TIMRST_TIM3;
break;
}
#endif
#ifdef CONFIG_STM32_TIM4_PWM
case 4:
{
regaddr = TIMRCCRST_TIM4;
resetbit = TIMRST_TIM4;
break;
}
#endif
#ifdef CONFIG_STM32_TIM5_PWM
case 5:
{
regaddr = TIMRCCRST_TIM5;
resetbit = TIMRST_TIM5;
break;
}
#endif
#ifdef CONFIG_STM32_TIM8_PWM
case 8:
{
regaddr = TIMRCCRST_TIM8;
resetbit = TIMRST_TIM8;
break;
}
#endif
#ifdef CONFIG_STM32_TIM9_PWM
case 9:
{
regaddr = TIMRCCRST_TIM9;
resetbit = TIMRST_TIM9;
break;
}
#endif
#ifdef CONFIG_STM32_TIM10_PWM
case 10:
{
regaddr = TIMRCCRST_TIM10;
resetbit = TIMRST_TIM10;
break;
}
#endif
#ifdef CONFIG_STM32_TIM11_PWM
case 11:
{
regaddr = TIMRCCRST_TIM11;
resetbit = TIMRST_TIM11;
break;
}
#endif
#ifdef CONFIG_STM32_TIM12_PWM
case 12:
{
regaddr = TIMRCCRST_TIM12;
resetbit = TIMRST_TIM12;
break;
}
#endif
#ifdef CONFIG_STM32_TIM13_PWM
case 13:
{
regaddr = TIMRCCRST_TIM13;
resetbit = TIMRST_TIM13;
break;
}
#endif
#ifdef CONFIG_STM32_TIM14_PWM
case 14:
{
regaddr = TIMRCCRST_TIM14;
resetbit = TIMRST_TIM14;
break;
}
#endif
#ifdef CONFIG_STM32_TIM15_PWM
case 15:
{
regaddr = TIMRCCRST_TIM15;
resetbit = TIMRST_TIM15;
break;
}
#endif
#ifdef CONFIG_STM32_TIM16_PWM
case 16:
{
regaddr = TIMRCCRST_TIM16;
resetbit = TIMRST_TIM16;
break;
}
#endif
#ifdef CONFIG_STM32_TIM17_PWM
case 17:
{
regaddr = TIMRCCRST_TIM17;
resetbit = TIMRST_TIM17;
break;
}
#endif
default:
{
ret = -EINVAL;
goto errout;
}
}
/* Disable interrupts momentary to stop any ongoing timer processing and
* to prevent any concurrent access to the reset register.
*/
@ -4622,23 +4474,16 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0);
pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0);
/* Reset the timer - stopping the output and putting the timer back
* into a state where pwm_start() can be called.
*/
/* Disable the timer and timer outputs */
regval = getreg32(regaddr);
regval |= resetbit;
putreg32(regval, regaddr);
pwm_timer_enable(dev, false);
outputs = pwm_outputs_from_channels(priv);
ret = pwm_outputs_enable(dev, outputs, false);
regval &= ~resetbit;
putreg32(regval, regaddr);
leave_critical_section(flags);
pwminfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n",
regaddr, resetbit);
pwm_dumpregs(dev, "After stop");
errout:
return ret;
}