diff --git a/arch/arm/src/stm32/stm32_lowputc.c b/arch/arm/src/stm32/stm32_lowputc.c
index 08b0118beb..1ba29a573f 100644
--- a/arch/arm/src/stm32/stm32_lowputc.c
+++ b/arch/arm/src/stm32/stm32_lowputc.c
@@ -178,7 +178,18 @@
 #  define USART_CR1_PARITY_VALUE 0
 #endif
 
-#define USART_CR1_CLRBITS (USART_CR1_M|USART_CR1_PCE|USART_CR1_PS|USART_CR1_TE|USART_CR1_RE|USART_CR1_ALLINTS)
+#ifdef CONFIG_STM32_STM32F30XX
+#  define USART_CR1_CLRBITS\
+    (USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS |\
+     USART_CR1_PCE |USART_CR1_WAKE | USART_CR1_M | USART_CR1_MME |\
+     USART_CR1_OVER8 | USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK |\
+     USART_CR1_ALLINTS)
+#else
+#  define USART_CR1_CLRBITS\
+    (USART_CR1_M | USART_CR1_PCE |USART_CR1_PS | USART_CR1_TE |\
+     USART_CR1_RE | USART_CR1_ALLINTS)
+#endif
+
 #define USART_CR1_SETBITS (USART_CR1_M_VALUE|USART_CR1_PARITY_VALUE)
 
 /* CR2 settings */
@@ -189,12 +200,34 @@
 #  define USART_CR2_STOP2_VALUE 0
 #endif
 
-#define USART_CR2_CLRBITS (USART_CR2_STOP_MASK|USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL|USART_CR2_LBDIE)
+#ifdef CONFIG_STM32_STM32F30XX
+#  define USART_CR2_CLRBITS \
+    (USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL |\
+     USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK |\
+     USART_CR2_LINEN | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV |\
+     USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMOD_MASK |\
+     USART_CR2_RTOEN | USART_CR2_ADD8_MASK)
+#else
+#  define USART_CR2_CLRBITS \
+    (USART_CR2_STOP_MASK|USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|\
+     USART_CR2_LBCL|USART_CR2_LBDIE)
+#endif
 #define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
 
 /* CR3 settings */
 
-#define USART_CR3_CLRBITS (USART_CR3_CTSIE|USART_CR3_CTSE|USART_CR3_RTSE|USART_CR3_EIE)
+#ifdef CONFIG_STM32_STM32F30XX
+
+#  define USART_CR3_CLRBITS \
+    (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL |\
+     USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT |\
+     USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR1_ONEBIT |\
+     USART_CR1_OVRDIS | USART_CR1_DDRE | USART_CR1_DEM | USART_CR1_DEP |\
+     USART_CR1_SCARCNT_MASK | USART_CR1_WUS_MASK | USART_CR1_WUFIE)
+#else
+#  define USART_CR3_CLRBITS \
+    (USART_CR3_CTSIE|USART_CR3_CTSE|USART_CR3_RTSE|USART_CR3_EIE)
+#endif
 #define USART_CR3_SETBITS 0
 
 /* Only the STM32 F3 supports oversampling by 8 */
@@ -465,14 +498,6 @@ void stm32_lowsetup(void)
 
   putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
 
-  /* Select oversampling by 8 */
-
-#ifdef USE_OVER8
-  cr  = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
-  cr |= USART_CR1_OVER8;
-  putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
-#endif
-
   /* Enable Rx, Tx, and the USART */
 
   cr  = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
@@ -536,9 +561,16 @@ void stm32_lowsetup(void)
 
   putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
 
-  /* Enable Rx, Tx, and the USART */
+  /* Select oversampling by 8 */
 
   cr  = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
+#ifdef USE_OVER8
+  cr |= USART_CR1_OVER8;
+  putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
+#endif
+
+  /* Enable Rx, Tx, and the USART */
+
   cr |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE);
   putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
 #endif
diff --git a/arch/arm/src/stm32/stm32f30xxx_rcc.c b/arch/arm/src/stm32/stm32f30xxx_rcc.c
index f272217a38..c18f1de3e3 100644
--- a/arch/arm/src/stm32/stm32f30xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f30xxx_rcc.c
@@ -90,6 +90,8 @@ static inline void rcc_reset(void)
               RCC_CFGR2_ADC34PRES_MASK);
   putreg32(regval, STM32_RCC_CFGR2);
 
+  putreg32(0, STM32_RCC_CFGR2);             /* Reset fCK source for all U[S]ARTs to PCLK */
+
   regval  = getreg32(STM32_RCC_CR);         /* Reset HSEON, CSSON and PLLON bits */
   regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
   putreg32(regval, STM32_RCC_CR);