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SAMA5: Add configuration to assign an XDMAC channel to an HSMCI

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This commit is contained in:
Gregory Nutt 2014-06-29 08:43:46 -06:00
parent 339c8edf0e
commit a892171b04
4 changed files with 104 additions and 19 deletions
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18
Documentation/acronyms.txt
View File

@ -8,15 +8,22 @@ CP15 Coprocessor 15 (ARM)
DEVIF Device Interface (networking)
DAC Digital to Analog Conversion
DEV Device
DMA Direct Memory Access (hardware)
DMAC DMA Controller (hardware)
DRAM Dynamic RAM
FAT File Allocation Table
FTL FLASH Translation Layer
FAT File Allocation Table (file systems)
FTL FLASH Translation Layer (MTD)
HSMCI High Speed Memory Card Interface (Atmel)
I/O Input/Output
IP Internet Protocol (version 4?) (networking)
IPv6 Internet Protocol Version 6 (networking)
IRQ Interrupt Request
I2C Inter-Integrated Circuit
I2S Inter IC Sound
ICMP Internet Control Message Protocol (networking)
IOB I/O Buffer (networking)
LIBC The "C" Library
MCI Memory Card Interface
MM Memory Management/Manager
MMAP Memory Map
MMC Multi-Media Card
@ -32,8 +39,12 @@ PID Peripheral ID (Atmel SAM)
PWM Pulse Width Modulation
PKT "Raw" Packet socket (networking)
RAM Random Access Memory
RTC Real Time Clock
RTCC Real Time Clock/Calendar
SAIC Secure Advanced Interrupt Controller (Atmel SAM)
SD Secure Digital
SDIO Secure Digital I/O
SMC Static Memory Controller (hardware)
SPI Serial Periperhal Interface
TCP Transmission Control Protocol (networking)
TSC Touchscreen Controller
@ -43,5 +54,4 @@ UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus
USART Universal Synchronous/Asynchronous Receiver/Transmitter
WDT Watchdog Timer
XDMAC Extended DMA Controller (Atmel)

41
arch/arm/src/sama5/Kconfig
View File

@ -413,13 +413,13 @@ config SAMA5_DMAC1
depends on SAMA5_HAVE_DMA
config SAMA5_XDMAC0
bool "XDMA Controller (XDMAC0)"
bool "XDMA Controller (XDMAC0, always secure)"
default n
select ARCH_DMA
depends on SAMA5_HAVE_XDMA
config SAMA5_XDMAC1
bool "XDMA Controller (XDMAC1)"
bool "XDMA Controller (XDMAC1, never secure)"
default n
select ARCH_DMA
depends on SAMA5_HAVE_XDMA
@ -2400,6 +2400,43 @@ endif # SAMA5_SSC0 || SAMA5_SSC1
if SAMA5_HSMCI0 || SAMA5_HSMCI1 || SAMA5_HSMCI2
menu "HSMCI device driver options"
if SAMA5_XDMAC0 || SAMA5_XDMAC1
choice
prompt "HSMCI0 XDMAC Selection"
default SAMA5_HSMCI0_XDMAC0 if SAMA5_XDMAC0
default SAMA5_HSMCI0_XDMAC1 if !SAMA5_XDMAC0 && SAMA5_XDMAC1
depends on SAMA5_HSMCI0
config SAMA5_HSMCI0_XDMAC0
bool "XDMAC0 (always secure)"
depends on SAMA5_XDMAC0
config SAMA5_HSMCI0_XDMAC1
bool "XDMAC1 (never secure)"
depends on SAMA5_XDMAC1
endchoice # HSMCI0 XDMAC Selection
choice
prompt "HSMCI1 XDMAC Selection"
default SAMA5_HSMCI1_XDMAC0 if SAMA5_XDMAC0
default SAMA5_HSMCI1_XDMAC1 if !SAMA5_XDMAC0 && SAMA5_XDMAC1
depends on SAMA5_HSMCI1
config SAMA5_HSMCI1_XDMAC0
bool "XDMAC0 (always secure)"
depends on SAMA5_XDMAC0
config SAMA5_HSMCI1_XDMAC1
bool "XDMAC1 (never secure)"
depends on SAMA5_XDMAC1
endchoice # HSMCI1 XDMAC Selection
# There is no HSMCI2 on the platforms that support XDMAC
endif # SAMA5_XDMAC0 || SAMA5_XDMAC1
config SAMA5_HSMCI_RDPROOF
bool "Read Proof Enable"
default n

4
arch/arm/src/sama5/chip/sam_xdmac.h
View File

@ -384,7 +384,7 @@
#define XDMACH_CDUS_DUBS_MASK (0x00ffffff) /* Bits 0-23: Channel Destination Microblock Stride */
/* XDMA Channel Definitions *************************************************************/
/* XDMA Controller 0 Channel Definitions */
/* XDMA Controller 0 Channel Definitions (always secure) */
#define XDMAC0_CH_HSMCI0 0 /* HSMCI0 Receive/Transmit */
#define XDMAC0_CH_HSMCI1 1 /* HSMCI1 Receive/Transmit */
@ -433,7 +433,7 @@
#define XDMAC0_CH_CATB_TX 46 /* CATB Transmit */
#define XDMAC0_CH_CATB_RX 47 /* CATB Receive */
/* XDMA Controller 1 Channel Definitions */
/* XDMA Controller 1 Channel Definitions (never secure) */
#define XDMAC1_CH_HSMCI0 0 /* HSMCI0 Receive/Transmit */
#define XDMAC1_CH_HSMCI1 1 /* HSMCI1 Receive/Transmit */

60
arch/arm/src/sama5/sam_hsmci.c
View File

@ -79,16 +79,54 @@
/* Configuration ************************************************************/
#if defined(CONFIG_SAMA5_HSMCI0) && !defined(CONFIG_SAMA5_DMAC0)
# warning "HSMCI0 support requires CONFIG_SAMA5_DMAC0"
#endif
#if defined(ATSAMA5D3)
/* The SAMA5D3 has three HSMCI blocks: HSMCI0-2. HSMCI0 requires DMAC0
* support, HSMCI1-2 require DMAC1 support.
*/
#if defined(CONFIG_SAMA5_HSMCI1) && !defined(CONFIG_SAMA5_DMAC1)
# warning "HSMCI1 support requires CONFIG_SAMA5_DMAC1"
#endif
# define HSMCI0_DMAC 0
# define HSMCI1_DMAC 1
# define HSMCI2_DMAC 1
#if defined(CONFIG_SAMA5_HSMCI2) && !defined(CONFIG_SAMA5_DMAC1)
# warning "HSMCI2 support requires CONFIG_SAMA5_DMAC1"
# if defined(CONFIG_SAMA5_HSMCI0) && !defined(CONFIG_SAMA5_DMAC0)
# error "HSMCI0 support requires CONFIG_SAMA5_DMAC0"
# endif
# if defined(CONFIG_SAMA5_HSMCI1) && !defined(CONFIG_SAMA5_DMAC1)
# error "HSMCI1 support requires CONFIG_SAMA5_DMAC1"
# endif
# if defined(CONFIG_SAMA5_HSMCI2) && !defined(CONFIG_SAMA5_DMAC1)
# error "HSMCI2 support requires CONFIG_SAMA5_DMAC1"
# endif
#elif defined(ATSAMA5D4)
/* The SAMA5D3 has two HSMCI blocks: HSMCI0-1. They can be driven
* either by XDMAC0 (secure) or XDMAC1 (unsecure).
*/
# if !defined(CONFIG_SAMA5_XDMAC0) && !defined(CONFIG_SAMA5_XDMAC1)
# error HSMCI0/1 require CONFIG_SAMA5_XDMAC0 and/or CONFIG_SAMA5_XDMAC1
# endif
# if defined(CONFIG_SAMA5_XDMAC0) && defined(SAMA5_HSMCI0_XDMAC0)
# define HSMCI0_DMAC 0
# elif defined(CONFIG_SAMA5_XDMAC1)
# define HSMCI0_DMAC 1
# else
# error No valid DMA configuration for HSMCI0
# endif
# if defined(CONFIG_SAMA5_XDMAC0) && defined(SAMA5_HSMCI1_XDMAC0)
# define HSMCI1_DMAC 0
# elif defined(CONFIG_SAMA5_XDMAC1)
# define HSMCI1_DMAC 1
# else
# error No valid DMA configuration for HSMCI1
# endif
#else
# error Unrecognized SAMA5 architecture
#endif
#ifndef CONFIG_SCHED_WORKQUEUE
@ -2915,7 +2953,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
/* For DMA channel selection */
dmac = 0;
dmac = HSMCI0_DMAC;
pid = SAM_PID_HSMCI0;
}
else
@ -2952,7 +2990,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
/* For DMA channel selection */
dmac = 1;
dmac = HSMCI1_DMAC;
pid = SAM_PID_HSMCI1;
}
else
@ -2989,7 +3027,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
/* For DMA channel selection */
dmac = 1;
dmac = HSMCI2_DMAC;
pid = SAM_PID_HSMCI2;
}
else