Add more PIC32 header files
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3613 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -84,6 +84,7 @@
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/* Timer 1-5 Register Base Addresses */
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# define PIC32MX_TIMER_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00000600 + 0x200*(n-1))
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# define PIC32MX_TIMER1_K1BASE (PIC32MX_SFR_K1BASE + 0x00000600)
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# define PIC32MX_TIMER2_K1BASE (PIC32MX_SFR_K1BASE + 0x00000800)
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# define PIC32MX_TIMER3_K1BASE (PIC32MX_SFR_K1BASE + 0x00000a00)
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@ -92,6 +93,7 @@
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/* Input Capture 1-5 Register Base Addresses */
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# define PIC32MX_INCAP_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00002000 + 0x200*(n-1))
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# define PIC32MX_INCAP1_K1BASE (PIC32MX_SFR_K1BASE + 0x00002000)
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# define PIC32MX_INCAP2_K1BASE (PIC32MX_SFR_K1BASE + 0x00002200)
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# define PIC32MX_INCAP3_K1BASE (PIC32MX_SFR_K1BASE + 0x00002400)
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222
arch/mips/src/pic32mx/pic32mx-timer.h
Executable file
222
arch/mips/src/pic32mx/pic32mx-timer.h
Executable file
@ -0,0 +1,222 @@
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/************************************************************************************
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* arch/mips/src/pic32mx/pic32mx-timer.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_TIMER_H
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#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_TIMER_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "pic32mx-memorymap.h"
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#if CHIP_NTIMERS > 0
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/************************************************************************************
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* Pre-Processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define PIC32MX_TIMER_CON_OFFSET 0x0000 /* Timer control register */
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#define PIC32MX_TIMER_CONCLR_OFFSET 0x0004 /* Timer control clear register */
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#define PIC32MX_TIMER_CONSET_OFFSET 0x0008 /* Timer control set register */
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#define PIC32MX_TIMER_CONINV_OFFSET 0x000c /* Timer control invert register */
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#define PIC32MX_TIMER_CNT_OFFSET 0x0010 /* Timer count register */
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#define PIC32MX_TIMER_CNTCLR_OFFSET 0x0014 /* Timer count clear register */
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#define PIC32MX_TIMER_CNTSET_OFFSET 0x0018 /* Timer count set register */
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#define PIC32MX_TIMER_CNTINV_OFFSET 0x001c /* Timer count invert register */
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#define PIC32MX_TIMER_PR_OFFSET 0x0020 /* Timer period register */
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#define PIC32MX_TIMER_PRCLR_OFFSET 0x0024 /* Timer period clear register */
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#define PIC32MX_TIMER_PRSET_OFFSET 0x0028 /* Timer period set register */
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#define PIC32MX_TIMER_PRINV_OFFSET 0x002c /* Timer period invert register */
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/* Register Addresses ***************************************************************/
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#define PIC32MX_TIMER_CON(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CON_OFFSET)
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#define PIC32MX_TIMER_CONCLR(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CONCLR_OFFSET)
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#define PIC32MX_TIMER_CONSET(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CONSET_OFFSET)
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#define PIC32MX_TIMER_CONINV(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CONINV_OFFSET)
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#define PIC32MX_TIMER_CNT(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CNT_OFFSET)
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#define PIC32MX_TIMER_CNTCLR(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CNTCLR_OFFSET)
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#define PIC32MX_TIMER_CNTSET(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CNTSET_OFFSET)
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#define PIC32MX_TIMER_CNTINV(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CNTINV_OFFSET)
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#define PIC32MX_TIMER_PR(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_PR_OFFSET)
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#define PIC32MX_TIMER_PRCLR(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_PRCLR_OFFSET)
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#define PIC32MX_TIMER_PRSET(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_PRSET_OFFSET)
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#define PIC32MX_TIMER_PRINV(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_PRINV_OFFSET)
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#define PIC32MX_TIMER1_CON (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CON_OFFSET)
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#define PIC32MX_TIMER1_CONCLR (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CONCLR_OFFSET)
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#define PIC32MX_TIMER1_CONSET (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CONSET_OFFSET)
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#define PIC32MX_TIMER1_CONINV (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CONINV_OFFSET)
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#define PIC32MX_TIMER1_CNT (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CNT_OFFSET)
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#define PIC32MX_TIMER1_CNTCLR (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CNTCLR_OFFSET)
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#define PIC32MX_TIMER1_CNTSET (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CNTSET_OFFSET)
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#define PIC32MX_TIMER1_CNTINV (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CNTINV_OFFSET)
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#define PIC32MX_TIMER1_PR (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_PR_OFFSET)
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#define PIC32MX_TIMER1_PRCLR (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_PRCLR_OFFSET)
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#define PIC32MX_TIMER1_PRSET (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_PRSET_OFFSET)
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#define PIC32MX_TIMER1_PRINV (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
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#if CHIP_NTIMERS > 1
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# define PIC32MX_TIMER2_CON (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CON_OFFSET)
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# define PIC32MX_TIMER2_CONCLR (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CONCLR_OFFSET)
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# define PIC32MX_TIMER2_CONSET (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CONSET_OFFSET)
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# define PIC32MX_TIMER2_CONINV (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CONINV_OFFSET)
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# define PIC32MX_TIMER2_CNT (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CNT_OFFSET)
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# define PIC32MX_TIMER2_CNTCLR (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CNTCLR_OFFSET)
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# define PIC32MX_TIMER2_CNTSET (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CNTSET_OFFSET)
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# define PIC32MX_TIMER2_CNTINV (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CNTINV_OFFSET)
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# define PIC32MX_TIMER2_PR (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_PR_OFFSET)
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# define PIC32MX_TIMER2_PRCLR (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_PRCLR_OFFSET)
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# define PIC32MX_TIMER2_PRSET (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_PRSET_OFFSET)
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# define PIC32MX_TIMER2_PRINV (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
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#endif
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#if CHIP_NTIMERS > 2
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# define PIC32MX_TIMER3_CON (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CON_OFFSET)
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# define PIC32MX_TIMER3_CONCLR (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CONCLR_OFFSET)
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# define PIC32MX_TIMER3_CONSET (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CONSET_OFFSET)
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# define PIC32MX_TIMER3_CONINV (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CONINV_OFFSET)
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# define PIC32MX_TIMER3_CNT (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CNT_OFFSET)
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# define PIC32MX_TIMER3_CNTCLR (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CNTCLR_OFFSET)
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# define PIC32MX_TIMER3_CNTSET (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CNTSET_OFFSET)
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# define PIC32MX_TIMER3_CNTINV (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CNTINV_OFFSET)
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# define PIC32MX_TIMER3_PR (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_PR_OFFSET)
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# define PIC32MX_TIMER3_PRCLR (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_PRCLR_OFFSET)
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# define PIC32MX_TIMER3_PRSET (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_PRSET_OFFSET)
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# define PIC32MX_TIMER3_PRINV (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
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#endif
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#if CHIP_NTIMERS > 3
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# define PIC32MX_TIMER4_CON (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CON_OFFSET)
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# define PIC32MX_TIMER4_CONCLR (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CONCLR_OFFSET)
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# define PIC32MX_TIMER4_CONSET (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CONSET_OFFSET)
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# define PIC32MX_TIMER4_CONINV (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CONINV_OFFSET)
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# define PIC32MX_TIMER4_CNT (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CNT_OFFSET)
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# define PIC32MX_TIMER4_CNTCLR (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CNTCLR_OFFSET)
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# define PIC32MX_TIMER4_CNTSET (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CNTSET_OFFSET)
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# define PIC32MX_TIMER4_CNTINV (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CNTINV_OFFSET)
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# define PIC32MX_TIMER4_PR (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_PR_OFFSET)
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# define PIC32MX_TIMER4_PRCLR (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_PRCLR_OFFSET)
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# define PIC32MX_TIMER4_PRSET (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_PRSET_OFFSET)
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# define PIC32MX_TIMER4_PRINV (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
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#endif
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#if CHIP_NTIMERS > 4
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# define PIC32MX_TIMER5_CON (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CON_OFFSET)
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# define PIC32MX_TIMER5_CONCLR (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CONCLR_OFFSET)
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# define PIC32MX_TIMER5_CONSET (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CONSET_OFFSET)
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# define PIC32MX_TIMER5_CONINV (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CONINV_OFFSET)
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# define PIC32MX_TIMER5_CNT (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CNT_OFFSET)
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# define PIC32MX_TIMER5_CNTCLR (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CNTCLR_OFFSET)
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# define PIC32MX_TIMER5_CNTSET (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CNTSET_OFFSET)
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# define PIC32MX_TIMER5_CNTINV (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CNTINV_OFFSET)
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# define PIC32MX_TIMER5_PR (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_PR_OFFSET)
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# define PIC32MX_TIMER5_PRCLR (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_PRCLR_OFFSET)
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# define PIC32MX_TIMER5_PRSET (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_PRSET_OFFSET)
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# define PIC32MX_TIMER5_PRINV (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
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#endif
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/* Register Bit-Field Definitions ***************************************************/
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/* Timer control register */
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#define TIMER_CON_TCS (1 << 1) /* Bit 1: Timer clock source select (all) */
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#define TIMER1_CON_TSYNC (1 << 2) /* Bit 2: Timer external clock input synchronization selection (timer 1 only) */
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#define TIMER_CON_T32 (1 << 3) /* Bit 2: 32-bit timer mode select (even timers only) */
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#define TIMER_CON_TCKPS_SHIFT (4) /* Bits 4-6: Timer input clock prescale select (all except timer 1) */
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#define TIMER_CON_TCKPS_MASK (7 << TIMER_CON_TCKPS_SHIFT)
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# define TIMER_CON_TCKPS_1 (0 << TIMER_CON_TCKPS_SHIFT) /* 1:1 prescale value */
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# define TIMER_CON_TCKPS_2 (1 << TIMER_CON_TCKPS_SHIFT) /* 1:2 prescale value */
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# define TIMER_CON_TCKPS_4 (2 << TIMER_CON_TCKPS_SHIFT) /* 1:4 prescale value */
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# define TIMER_CON_TCKPS_8 (3 << TIMER_CON_TCKPS_SHIFT) /* 1:8 prescale value */
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# define TIMER_CON_TCKPS_16 (4 << TIMER_CON_TCKPS_SHIFT) /* 1:16 prescale value */
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# define TIMER_CON_TCKPS_32 (5 << TIMER_CON_TCKPS_SHIFT) /* 1:32 prescale value */
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# define TIMER_CON_TCKPS_64 (6 << TIMER_CON_TCKPS_SHIFT) /* 1:64 prescale value */
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# define TIMER_CON_TCKPS_256 (7 << TIMER_CON_TCKPS_SHIFT) /* 1:256 prescale value */
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#define TIMER1_CON_TCKPS_SHIFT (4) /* Bits 4-5: Timer input clock prescale select (timer 1 only) */
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#define TIMER1_CON_TCKPS_MASK (3 << TIMER1_CON_TCKPS_SHIFT)
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# define TIMER1_CON_TCKPS_1 (0 << TIMER1_CON_TCKPS_SHIFT) /* 1:1 prescale value */
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# define TIMER1_CON_TCKPS_8 (1 << TIMER1_CON_TCKPS_SHIFT) /* 1:8 prescale value */
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# define TIMER1_CON_TCKPS_64 (2 << TIMER1_CON_TCKPS_SHIFT) /* 1:64 prescale value */
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# define TIMER1_CON_TCKPS_256 (3 << TIMER1_CON_TCKPS_SHIFT) /* 1:256 prescale value */
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#define TIMER_CON_TGATE (1 << 7) /* Bit 7: Timer gated time accumulation enable (all) */
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#define TIMER1_CON_TWIP (1 << 11) /* Bit 11: Asynchronous timer write in progress (timer 1 only) */
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#define TIMER1_CON_TWDIS (1 << 12) /* Bit 12: Asynchronous timer write disable (timer 1 only) */
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#define TIMER_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode (all) */
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#define TIMER_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode (all) */
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#define TIMER_CON_ON (1 << 15) /* Bit 15: Timer on (all) */
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/* Timer count register */
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#define TIMER_CNT_MASK 0xffff /* 16-bit timer counter value */
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/* Timer period register */
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#define TIMER_PR_MASK 0xffff /* 16-bit timer period value */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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#ifndef __ASSEMBLY__
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* CHIP_NTIMERS > 0 */
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#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_TIMER_H */
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