From a94c8657919e2f8d7ac103a90ac62f8ad99e77b7 Mon Sep 17 00:00:00 2001 From: Huang Qi Date: Fri, 15 Apr 2022 18:06:00 +0800 Subject: [PATCH] arch/risc-v: Use fs status definition from csr.h Signed-off-by: Huang Qi --- arch/risc-v/src/common/riscv_fpu.S | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) diff --git a/arch/risc-v/src/common/riscv_fpu.S b/arch/risc-v/src/common/riscv_fpu.S index 3c29465e9b..313e68a4be 100644 --- a/arch/risc-v/src/common/riscv_fpu.S +++ b/arch/risc-v/src/common/riscv_fpu.S @@ -25,21 +25,12 @@ #include #include +#include #include #include #ifdef CONFIG_ARCH_FPU -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -#define FS_MASK 0x6000 -#define FS_OFF 0x0000 -#define FS_INITIAL 0x2000 -#define FS_CLEAN 0x4000 -#define FS_DIRTY 0x6000 - /************************************************************************************ * Public Symbols ************************************************************************************/ @@ -74,7 +65,7 @@ .type riscv_fpuconfig, function riscv_fpuconfig: - li a0, FS_INITIAL + li a0, MSTATUS_FS_INIT csrs CSR_STATUS, a0 csrwi fcsr, 0 ret @@ -102,13 +93,13 @@ riscv_fpuconfig: riscv_savefpu: REGLOAD t0, REG_INT_CTX(a0) - li t1, FS_MASK + li t1, MSTATUS_FS and t2, t0, t1 - li t1, FS_DIRTY + li t1, MSTATUS_FS_DIRTY bne t2, t1, 1f - li t1, ~FS_MASK + li t1, ~MSTATUS_FS and t0, t0, t1 - li t1, FS_CLEAN + li t1, MSTATUS_FS_CLEAN or t0, t0, t1 REGSTORE t0, REG_INT_CTX(a0) @@ -177,9 +168,9 @@ riscv_savefpu: riscv_restorefpu: REGLOAD t0, REG_INT_CTX(a0) - li t1, FS_MASK + li t1, MSTATUS_FS and t2, t0, t1 - li t1, FS_INITIAL + li t1, MSTATUS_FS_INIT ble t2, t1, 1f /* Load all floating point registers */