diff --git a/arch/arm/src/armv7-a/arm_gic.c b/arch/arm/src/armv7-a/arm_gic.c index 19d89120c1..324a447861 100644 --- a/arch/arm/src/armv7-a/arm_gic.c +++ b/arch/arm/src/armv7-a/arm_gic.c @@ -42,6 +42,9 @@ #include #include +#include + +#include "up_arch.h" #include "gic.h" #ifdef CONFIG_ARMV7A_HAVE_GIC @@ -111,7 +114,22 @@ uint32_t *arm_decodeirq(uint32_t *regs) void up_enable_irq(int irq) { -# warning Missing logic + /* Ignore invalid interrupt IDs. Also, in the Cortex-A9 MPCore, SGIs are + * always enabled. The corresponding bits in the ICDISERn are read as + * one, write ignored. + */ + + if (irq > GIC_IRQ_SGI15 && irq < NR_IRQS) + { + uintptr_t regaddr; + + /* Write '1' to the corresponding bit in the distributor Interrupt + * Set-Enable Register (ICDISER) + */ + + regaddr = GIC_ICDISER(irq); + putreg32(GIC_ICDISER_INT(irq), regaddr); + } } /**************************************************************************** @@ -130,7 +148,22 @@ void up_enable_irq(int irq) void up_disable_irq(int irq) { -# warning Missing logic + /* Ignore invalid interrupt IDs. Also, in the Cortex-A9 MPCore, SGIs are + * always enabled. The corresponding bits in the ICDISERn are read as + * one, write ignored. + */ + + if (irq > GIC_IRQ_SGI15 && irq < NR_IRQS) + { + uintptr_t regaddr; + + /* Write '1' to the corresponding bit in the distributor Interrupt + * Clear-Enable Register (ICDISER) + */ + + regaddr = GIC_ICDICER(irq); + putreg32(GIC_ICDICER_INT(irq), regaddr); + } } /**************************************************************************** diff --git a/arch/arm/src/armv7-a/mpcore.h b/arch/arm/src/armv7-a/mpcore.h index 3877e46021..962f127620 100644 --- a/arch/arm/src/armv7-a/mpcore.h +++ b/arch/arm/src/armv7-a/mpcore.h @@ -45,7 +45,7 @@ * Included Files ****************************************************************************/ -#include +#include "chip.h" /* For CHIP_MPCORE_VBASE */ /**************************************************************************** * Pre-processor Definitions