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Costmetic changes from last PR

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This commit is contained in:
Gregory Nutt 2016-04-30 09:04:38 -06:00
parent 696ea25c75
commit a95e426d35
3 changed files with 49 additions and 48 deletions
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6
arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
View File

@ -594,7 +594,7 @@ static void stm32l4_stdclockconfig(void)
/* setting MSIRANGE */
regval = getreg32(STM32L4_RCC_CR);
regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequ */
regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */
putreg32(regval, STM32L4_RCC_CR);
/* Wait until the MSI is ready (or until a timeout elapsed) */
@ -854,7 +854,7 @@ static void stm32l4_stdclockconfig(void)
* and we need to ensure it is first off before doing so.
*/
/* turn on the LSE oscillator
/* Turn on the LSE oscillator
* XXX this will almost surely get moved since we also want to use
* this for automatically trimming MSI, etc.
*/
@ -862,7 +862,7 @@ static void stm32l4_stdclockconfig(void)
stm32l4_rcc_enablelse();
# if defined(STM32L4_BOARD_USEMSI)
/* now that LSE is up, auto trim the MSI */
/* Now that LSE is up, auto trim the MSI */
regval = getreg32(STM32L4_RCC_CR);
regval |= RCC_CR_MSIPLLEN;

38
configs/nucleo-l476rg/include/nucleo-l476rg.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* configs/nucleo-l476rg/include/nucleo-l476rg.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -50,18 +50,18 @@
************************************************************************************/
#if 1
#define HSI_CLOCK_CONFIG /* HSI-16 clock configuration */
# define HSI_CLOCK_CONFIG /* HSI-16 clock configuration */
#elif 0
/* make sure you installed one! */
#define HSE_CLOCK_CONFIG /* HSE with 8 MHz xtal */
/* Make sure you installed one! */
# define HSE_CLOCK_CONFIG /* HSE with 8 MHz xtal */
#else
#define MSI_CLOCK_CONFIG /* MSI @ 4 MHz autotrimmed via LSE */
# define MSI_CLOCK_CONFIG /* MSI @ 4 MHz autotrimmed via LSE */
#endif
/* Clocking *************************************************************************/
#if defined(HSI_CLOCK_CONFIG)
/* The NUCLEOL476RG supports both HSE and LSE crystals (X2 and X3). However, as
* shipped, the X3 crystal is not populated. Therefore the Nucleo-L476RG
* will need to run off the 16MHz HSI clock, or the 32khz-synced MSI.
@ -304,7 +304,7 @@
#elif defined(HSE_CLOCK_CONFIG)
/* use the HSE */
/* Use the HSE */
#define STM32L4_BOARD_USEHSE 1
@ -312,7 +312,7 @@
/* XXX pll source mux = hse */
/* prescaler common to all PLL inputs */
/* Prescaler common to all PLL inputs */
#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
@ -346,22 +346,22 @@
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
/* enable CLK48; get it from PLLSAI1 */
/* Enable CLK48; get it from PLLSAI1 */
#define STM32L4_USE_CLK48
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
/* enable LSE (for the RTC) */
/* Enable LSE (for the RTC) */
#define STM32L4_USE_LSE 1
/* configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* configure the APB1 prescaler */
/* Configure the APB1 prescaler */
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
@ -373,7 +373,7 @@
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
/* configure the APB2 prescaler */
/* Configure the APB2 prescaler */
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
@ -383,7 +383,7 @@
#elif defined(MSI_CLOCK_CONFIG)
/* use the MSI; frequ = 4 MHz; autotrim from LSE */
/* Use the MSI; frequ = 4 MHz; autotrim from LSE */
#define STM32L4_BOARD_USEMSI 1
#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M
@ -426,22 +426,22 @@
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
/* enable CLK48; get it from PLLSAI1 */
/* Enable CLK48; get it from PLLSAI1 */
#define STM32L4_USE_CLK48
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
/* enable LSE (for the RTC) */
/* Enable LSE (for the RTC) */
#define STM32L4_USE_LSE 1
/* configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* configure the APB1 prescaler */
/* Configure the APB1 prescaler */
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
@ -453,7 +453,7 @@
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
/* configure the APB2 prescaler */
/* Configure the APB2 prescaler */
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)

53
configs/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h
View File

@ -52,8 +52,8 @@
/* Clocking *************************************************************************/
/* The stm32l476vg-disco supports both HSE and LSE crystals. As shipped, the HSE
crystal is not populated. Therefore the stm32l476vg-disco will need to run off the
16MHz HSI clock, or the 32khz-synced MSI, unless you install the HSE xtal.
* crystal is not populated. Therefore the stm32l476vg-disco will need to run off the
* 16MHz HSI clock, or the 32khz-synced MSI, unless you install the HSE xtal.
*/
/* HSI - 16 MHz RC factory-trimmed
@ -70,25 +70,26 @@
#define BOARD_AHB_FREQUENCY 80000000ul
/* XXX there needs to be independent selections for the System Clock Mux and
the PLL Source Mux; currently System Clock Mux always is PLL, and PLL
Source Mux is chosen by the following define. This is probably OK in many
cases, but should be separated to support other power configurations.
* the PLL Source Mux; currently System Clock Mux always is PLL, and PLL
* Source Mux is chosen by the following define. This is probably OK in many
* cases, but should be separated to support other power configurations.
*/
#if 0
#define HSI_CLOCK_CONFIG /* HSI-16 clock configuration */
# define HSI_CLOCK_CONFIG /* HSI-16 clock configuration */
#elif 0
/* make sure you actually installed one! */
#define HSE_CLOCK_CONFIG /* HSE with 8 MHz xtal */
/* Make sure you actually installed one! */
# define HSE_CLOCK_CONFIG /* HSE with 8 MHz xtal */
#else
#define MSI_CLOCK_CONFIG /* MSI @ 4 MHz autotrimmed via LSE */
# define MSI_CLOCK_CONFIG /* MSI @ 4 MHz autotrimmed via LSE */
#endif
#if defined(HSI_CLOCK_CONFIG)
#define STM32L4_BOARD_USEHSI 1
#define STM32L4_BOARD_USEHSI 1
/* prescaler common to all PLL inputs; will be 1 (XXX source is implicitly
/* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly
as per comment above HSI) */
#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
@ -144,7 +145,7 @@
#define STM32L4_USE_CLK48 1
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
/* enable the LSE oscillator, used automatically trim the MSI, and for RTC */
/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
#define STM32L4_USE_LSE 1
@ -188,7 +189,7 @@
#elif defined(HSE_CLOCK_CONFIG)
/* use the HSE */
/* Use the HSE */
#define STM32L4_BOARD_USEHSE 1
@ -196,7 +197,7 @@
/* XXX pll source mux = hse */
/* prescaler common to all PLL inputs */
/* Prescaler common to all PLL inputs */
#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
@ -230,22 +231,22 @@
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
/* enable CLK48; get it from PLLSAI1 */
/* Enable CLK48; get it from PLLSAI1 */
#define STM32L4_USE_CLK48
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
/* enable LSE (for the RTC) */
/* Enable LSE (for the RTC) */
#define STM32L4_USE_LSE 1
/* configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* configure the APB1 prescaler */
/* Configure the APB1 prescaler */
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
@ -257,7 +258,7 @@
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
/* configure the APB2 prescaler */
/* Configure the APB2 prescaler */
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
@ -267,7 +268,7 @@
#elif defined(MSI_CLOCK_CONFIG)
/* use the MSI; frequ = 4 MHz; autotrim from LSE */
/* Use the MSI; frequ = 4 MHz; autotrim from LSE */
#define STM32L4_BOARD_USEMSI 1
#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M
@ -276,7 +277,7 @@
/* XXX pll source mux = msi */
/* prescaler common to all PLL inputs */
/* Prescaler common to all PLL inputs */
#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
@ -310,22 +311,22 @@
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
/* enable CLK48; get it from PLLSAI1 */
/* Enable CLK48; get it from PLLSAI1 */
#define STM32L4_USE_CLK48
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
/* enable LSE (for the RTC) */
/* Enable LSE (for the RTC) */
#define STM32L4_USE_LSE 1
/* configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* configure the APB1 prescaler */
/* Configure the APB1 prescaler */
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
@ -337,7 +338,7 @@
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
/* configure the APB2 prescaler */
/* Configure the APB2 prescaler */
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)