diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h index 98fe5c9763..50c2e9329f 100644 --- a/arch/arm/include/stm32/chip.h +++ b/arch/arm/include/stm32/chip.h @@ -165,7 +165,7 @@ # define STM32_NGPIO 37 /* GPIOA-E,H */ # define STM32_NADC 1 /* ADC1, 14-channels */ # define STM32_NDAC 2 /* DAC 1-2, 2 channels */ - /* (2) Comparators */ +# define STM32_NCMP 2 /* (2) Comparators */ # define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ # define STM32_NCRC 0 /* No CRC */ # define STM32_NETHERNET 0 /* No Ethernet */ @@ -191,7 +191,7 @@ # define STM32_NGPIO 51 /* GPIOA-E,H */ # define STM32_NADC 1 /* ADC1, 20-channels */ # define STM32_NDAC 2 /* DAC 1-2, 2 channels */ - /* (2) Comparators */ +# define STM32_NCMP 2 /* (2) Comparators */ # define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ # define STM32_NCRC 0 /* No CRC */ # define STM32_NETHERNET 0 /* No Ethernet */ @@ -217,7 +217,7 @@ # define STM32_NGPIO 83 /* GPIOA-E,H */ # define STM32_NADC 1 /* ADC1, 24-channels */ # define STM32_NDAC 2 /* DAC 1-2, 2 channels */ - /* (2) Comparators */ +# define STM32_NCMP 2 /* (2) Comparators */ # define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ # define STM32_NCRC 0 /* No CRC */ # define STM32_NETHERNET 0 /* No Ethernet */ @@ -243,7 +243,7 @@ # define STM32_NGPIO 37 /* GPIOA-E,H */ # define STM32_NADC 1 /* ADC1, 14-channels */ # define STM32_NDAC 2 /* DAC 1-2, 2 channels */ - /* (2) Comparators */ +# define STM32_NCMP 2 /* (2) Comparators */ # define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ # define STM32_NCRC 0 /* No CRC */ # define STM32_NETHERNET 0 /* No Ethernet */ @@ -269,7 +269,7 @@ # define STM32_NGPIO 51 /* GPIOA-E,H */ # define STM32_NADC 1 /* ADC1, 20-channels */ # define STM32_NDAC 2 /* DAC 1-2, 2 channels */ - /* (2) Comparators */ +# define STM32_NCMP 2 /* (2) Comparators */ # define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ # define STM32_NCRC 0 /* No CRC */ # define STM32_NETHERNET 0 /* No Ethernet */ @@ -295,7 +295,7 @@ # define STM32_NGPIO 83 /* GPIOA-E,H */ # define STM32_NADC 1 /* ADC1, 24-channels */ # define STM32_NDAC 2 /* DAC 1-2, 2 channels */ - /* (2) Comparators */ +# define STM32_NCMP 2 /* (2) Comparators */ # define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ # define STM32_NCRC 0 /* No CRC */ # define STM32_NETHERNET 0 /* No Ethernet */ @@ -320,7 +320,7 @@ # define STM32_NGPIO 37 /* GPIOA-E,H */ # define STM32_NADC 1 /* ADC1, 14-channels */ # define STM32_NDAC 2 /* DAC 1-2, 2 channels */ - /* (2) Comparators */ +# define STM32_NCMP 2 /* (2) Comparators */ # define STM32_NCAPSENSE 16 /* Capacitive sensing channels */ # define STM32_NCRC 1 /* CRC */ # define STM32_NETHERNET 0 /* No ethernet */ @@ -345,7 +345,7 @@ # define STM32_NGPIO 51 /* GPIOA-E,H */ # define STM32_NADC 1 /* ADC1, 21-channels */ # define STM32_NDAC 2 /* DAC 1-2, 2 channels */ - /* (2) Comparators */ +# define STM32_NCMP 2 /* (2) Comparators */ # define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ # define STM32_NCRC 1 /* CRC */ # define STM32_NETHERNET 0 /* No ethernet */ @@ -370,7 +370,7 @@ # define STM32_NGPIO 83 /* GPIOA-E,H */ # define STM32_NADC 1 /* ADC1, 25-channels */ # define STM32_NDAC 2 /* DAC 1-2, 2 channels */ - /* (2) Comparators */ +# define STM32_NCMP 2 /* (2) Comparators */ # define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ # define STM32_NCRC 1 /* CRC */ # define STM32_NETHERNET 0 /* No ethernet */ @@ -395,7 +395,7 @@ # define STM32_NGPIO 51 /* GPIOA-E,H */ # define STM32_NADC 1 /* ADC1, 25-channels */ # define STM32_NDAC 2 /* DAC 1-2, 2 channels */ - /* (2) Comparators */ +# define STM32_NCMP 2 /* (2) Comparators */ # define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ # define STM32_NCRC 1 /* CRC */ # define STM32_NETHERNET 0 /* No ethernet */ @@ -420,7 +420,7 @@ # define STM32_NGPIO 83 /* GPIOA-E,H */ # define STM32_NADC 1 /* ADC1, 25-channels */ # define STM32_NDAC 2 /* DAC 1-2, 2 channels */ - /* (2) Comparators */ +# define STM32_NCMP 2 /* (2) Comparators */ # define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ # define STM32_NCRC 1 /* CRC */ # define STM32_NETHERNET 0 /* No ethernet */ @@ -445,7 +445,7 @@ # define STM32_NGPIO 109 /* GPIOA-E,H */ # define STM32_NADC 1 /* ADC1, 25-channels */ # define STM32_NDAC 2 /* DAC 1-2, 2 channels */ - /* (2) Comparators */ +# define STM32_NCMP 2 /* (2) Comparators */ # define STM32_NCAPSENSE 33 /* Capacitive sensing channels */ # define STM32_NCRC 1 /* CRC */ # define STM32_NETHERNET 0 /* No ethernet */ @@ -470,7 +470,7 @@ # define STM32_NGPIO 115 /* GPIOA-E,H */ # define STM32_NADC 1 /* ADC1, 25-channels */ # define STM32_NDAC 2 /* DAC 1-2, 2 channels */ - /* (2) Comparators */ +# define STM32_NCMP 2 /* (2) Comparators */ # define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ # define STM32_NCRC 1 /* CRC */ # define STM32_NETHERNET 0 /* No ethernet */ @@ -496,7 +496,7 @@ # define STM32_NGPIO 115 /* GPIOA-G,H */ # define STM32_NADC 1 /* ADC1, 40-channels */ # define STM32_NDAC 2 /* DAC 1-2, 2 channels */ - /* (2) Comparators */ +# define STM32_NCMP 2 /* (2) Comparators */ # define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ # define STM32_NCRC 1 /* CRC */ # define STM32_NETHERNET 0 /* No ethernet */ @@ -523,14 +523,13 @@ # define STM32_NADC 1 /* ADC1, 25-channels */ # define STM32_NDAC 2 /* DAC 1-2, 2 channels */ - /* (2) Comparators */ +# define STM32_NCMP 2 /* (2) Comparators */ # define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ # define STM32_NCRC 1 /* CRC */ # define STM32_NETHERNET 0 /* No ethernet */ # define STM32_NRNG 0 /* No random number generator (RNG) */ # define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - /* STM32 F100 Value Line ************************************************************/ #elif defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \ diff --git a/arch/arm/src/stm32/chip/stm32_pwr.h b/arch/arm/src/stm32/chip/stm32_pwr.h index e67f81112b..6fa55afc6e 100644 --- a/arch/arm/src/stm32/chip/stm32_pwr.h +++ b/arch/arm/src/stm32/chip/stm32_pwr.h @@ -166,7 +166,7 @@ #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define PWR_CSR_ODRDY (1 << 16) /* Git 16: Over Drive generator ready */ +# define PWR_CSR_ODRDY (1 << 16) /* Bit 16: Over Drive generator ready */ # define PWR_CSR_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */ #endif diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_i2c.h b/arch/arm/src/stm32/chip/stm32f30xxx_i2c.h index 310bc10234..40a0bee37e 100644 --- a/arch/arm/src/stm32/chip/stm32f30xxx_i2c.h +++ b/arch/arm/src/stm32/chip/stm32f30xxx_i2c.h @@ -36,6 +36,10 @@ #ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_I2C_H #define __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_I2C_H +/* This file provide definitions for the STM32 I2C IP core 2 (F0, F3, F7, H7, and + * L4). + */ + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ diff --git a/arch/arm/src/stm32/chip/stm32l15xxx_rcc.h b/arch/arm/src/stm32/chip/stm32l15xxx_rcc.h index 29925e56e4..a3782614fb 100644 --- a/arch/arm/src/stm32/chip/stm32l15xxx_rcc.h +++ b/arch/arm/src/stm32/chip/stm32l15xxx_rcc.h @@ -144,7 +144,7 @@ # define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ # define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ # define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ -#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 18-10: APB Low speed prescaler (APB1) */ +#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 8-10: APB Low speed prescaler (APB1) */ #define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT) # define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */ # define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */ diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c index 3ead08e804..414c440dba 100644 --- a/arch/arm/src/stm32/stm32_allocateheap.c +++ b/arch/arm/src/stm32/stm32_allocateheap.c @@ -53,10 +53,12 @@ #include #include "chip.h" -#include "mpu.h" +#ifdef CONFIG_ARM_MPU +# include "mpu.h" +# include "stm32_mpuinit.h" +#endif #include "up_arch.h" #include "up_internal.h" -#include "stm32_mpuinit.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c index dfd1969e9a..3a54fa92d5 100644 --- a/arch/arm/src/stm32/stm32_irq.c +++ b/arch/arm/src/stm32/stm32_irq.c @@ -48,7 +48,9 @@ #include #include "nvic.h" -#include "ram_vectors.h" +#ifdef CONFIG_ARCH_RAMVECTORS +# include "ram_vectors.h" +#endif #include "up_arch.h" #include "up_internal.h" #include "stm32.h" diff --git a/arch/arm/src/stm32/stm32f33xxx_rcc.c b/arch/arm/src/stm32/stm32f33xxx_rcc.c index d3fb82b0fa..a2685a937d 100644 --- a/arch/arm/src/stm32/stm32f33xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f33xxx_rcc.c @@ -144,7 +144,7 @@ static inline void rcc_enableahb(void) #endif #ifdef CONFIG_STM32_TSC - /* CRC clock enable */ + /* TSC clock enable */ regval |= RCC_AHBENR_TSCEN; #endif