diff --git a/Kconfig b/Kconfig
index e18f2b3f15..b47091e1db 100644
--- a/Kconfig
+++ b/Kconfig
@@ -936,7 +936,7 @@ config DEBUG_ANALOG
 	default n
 	depends on ANALOG
 	---help---
-		Enable  debug features.
+		Enable analog devic debug features.
 		Enable low level debug features the analog device drivers such as
 		A/D and D/A converters (disabled by default).  Support for this
 		debug option is architecture-specific and may not be available for
@@ -977,13 +977,39 @@ config DEBUG_CAN
 		be available for some MCUs.
 
 config DEBUG_GPIO
-	bool "GPIO Debug Output"
+	bool "GPIO Debug Features"
 	default n
 	---help---
-		Enable GPIO-releated debug SYSLOG output (disabled by default).
+		Enable GPIO debug features.
+
 		Support for this debug option is architecture-specific and may not
 		be available for some MCUs.
 
+if DEBUG_GPIO
+
+config DEBUG_GPIO_ERROR
+	bool "GPIO Error Output"
+	default n
+	depends on DEBUG_ERROR
+	---help---
+		Enable GPIO error output to SYSLOG.
+
+config DEBUG_GPIO_WARN
+	bool "GPIO Warnings Output"
+	default n
+	depends on DEBUG_WARN
+	---help---
+		Enable GPIO warning output to SYSLOG.
+
+config DEBUG_GPIO_INFO
+	bool "GPIO Informational Output"
+	default n
+	depends on DEBUG_INFO
+	---help---
+		Enable GPIO informational output to SYSLOG.
+
+endif # DEBUG_GPIO
+
 config DEBUG_I2C
 	bool "I2C Debug Output"
 	default n
diff --git a/arch/arm/src/efm32/efm32_gpio.c b/arch/arm/src/efm32/efm32_gpio.c
index 77bc980481..7ffc58cf34 100644
--- a/arch/arm/src/efm32/efm32_gpio.c
+++ b/arch/arm/src/efm32/efm32_gpio.c
@@ -390,7 +390,7 @@ bool efm32_gpioread(gpio_pinset_t pinset)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int efm32_dumpgpio(uint32_t pinset, const char *msg)
 {
 #warning Missing logic
diff --git a/arch/arm/src/efm32/efm32_gpio.h b/arch/arm/src/efm32/efm32_gpio.h
index 50c239954a..7dc6624975 100644
--- a/arch/arm/src/efm32/efm32_gpio.h
+++ b/arch/arm/src/efm32/efm32_gpio.h
@@ -50,10 +50,6 @@
  ************************************************************************************/
 /* Configuration ********************************************************************/
 
-#ifndef CONFIG_DEBUG_FEATURES
-#  undef CONFIG_DEBUG_GPIO
-#endif
-
 #define EFM32_NGPIO                5 /* (5) GPIOA-F */
 
 /* Bit-encoded input to efm32_configgpio() *******************************************/
@@ -350,7 +346,7 @@ void efm32_gpioirqclear(int irq);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int efm32_dumpgpio(uint32_t pinset, const char *msg);
 #else
 #  define efm32_dumpgpio(p,m)
diff --git a/arch/arm/src/imx6/imx_gpio.h b/arch/arm/src/imx6/imx_gpio.h
index 2c3acd9abe..23ca29c318 100644
--- a/arch/arm/src/imx6/imx_gpio.h
+++ b/arch/arm/src/imx6/imx_gpio.h
@@ -288,7 +288,7 @@ void imx_gpioirq_disable(int irq);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int imx_dump_gpio(uint32_t pinset, const char *msg);
 #else
 #  define imx_dumpgpio(p,m)
diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs
index ed4311a721..662dd61873 100644
--- a/arch/arm/src/kinetis/Make.defs
+++ b/arch/arm/src/kinetis/Make.defs
@@ -107,7 +107,7 @@ ifeq ($(CONFIG_GPIO_IRQ),y)
 CHIP_CSRCS += kinetis_pinirq.c
 endif
 
-ifeq ($(CONFIG_DEBUG_GPIO),y)
+ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)
 CHIP_CSRCS += kinetis_pindump.c
 endif
 
diff --git a/arch/arm/src/kinetis/kinetis.h b/arch/arm/src/kinetis/kinetis.h
index 325b88d697..ae02ce7e4f 100644
--- a/arch/arm/src/kinetis/kinetis.h
+++ b/arch/arm/src/kinetis/kinetis.h
@@ -566,7 +566,7 @@ void kinetis_pindmadisable(uint32_t pinset);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 void kinetis_pindump(uint32_t pinset, const char *msg);
 #else
 #  define kinetis_pindump(p,m)
diff --git a/arch/arm/src/kinetis/kinetis_pindump.c b/arch/arm/src/kinetis/kinetis_pindump.c
index de750115e7..579c01bb4d 100644
--- a/arch/arm/src/kinetis/kinetis_pindump.c
+++ b/arch/arm/src/kinetis/kinetis_pindump.c
@@ -49,7 +49,7 @@
 #include "kinetis_gpio.h"
 #include "kinetis_port.h"
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 
 /****************************************************************************
  * Private Data
@@ -115,14 +115,14 @@ void kinetis_pindump(uint32_t pinset, const char *msg)
 
   flags = enter_critical_section();
 
-  llerr("GPIO%c pinset: %08x base: %08x -- %s\n",
-        g_portchar[port], pinset, base, msg);
-  llerr("  PDOR: %08x  PDIR: %08x  PDDR: %08x\n",
-        getreg32(base + KINETIS_GPIO_PDOR_OFFSET),
-        getreg32(base + KINETIS_GPIO_PDIR_OFFSET),
-        getreg32(base + KINETIS_GPIO_PDDR_OFFSET));
+  gpioinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
+           g_portchar[port], pinset, base, msg);
+  gpioinfo("  PDOR: %08x  PDIR: %08x  PDDR: %08x\n",
+           getreg32(base + KINETIS_GPIO_PDOR_OFFSET),
+           getreg32(base + KINETIS_GPIO_PDIR_OFFSET),
+           getreg32(base + KINETIS_GPIO_PDDR_OFFSET));
 
   leave_critical_section(flags);
 }
 
-#endif /* CONFIG_DEBUG_GPIO */
+#endif /* CONFIG_DEBUG_GPIO_INFO */
diff --git a/arch/arm/src/lpc11xx/lpc11_gpio.h b/arch/arm/src/lpc11xx/lpc11_gpio.h
index 3bff062e07..a0e1c2d899 100644
--- a/arch/arm/src/lpc11xx/lpc11_gpio.h
+++ b/arch/arm/src/lpc11xx/lpc11_gpio.h
@@ -180,7 +180,7 @@ void lpc11_gpioirqdisable(int irq);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg);
 #else
 #  define lpc11_dumpgpio(p,m)
diff --git a/arch/arm/src/lpc11xx/lpc11_gpiodbg.c b/arch/arm/src/lpc11xx/lpc11_gpiodbg.c
index d88aeb7362..86b3098dcd 100644
--- a/arch/arm/src/lpc11xx/lpc11_gpiodbg.c
+++ b/arch/arm/src/lpc11xx/lpc11_gpiodbg.c
@@ -54,15 +54,7 @@
 #include "chip.h"
 #include "lpc11_gpio.h"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#ifndef CONFIG_DEBUG_FEATURES
-#  undef CONFIG_DEBUG_GPIO
-#endif
-
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 
 /****************************************************************************
  * Private Functions
@@ -154,35 +146,34 @@ int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg)
   /* The following requires exclusive access to the GPIO registers */
 
   flags = enter_critical_section();
-  llinfo("GPIO%c pin%d (pinset: %08x) -- %s\n",
-        port + '0', pin, pinset, msg);
+  gpioinfo("GPIO%c pin%d (pinset: %08x) -- %s\n",
+           port + '0', pin, pinset, msg);
 
 #if defined(LPC176x)
-  llinfo("  PINSEL[%08x]: %08x PINMODE[%08x]: %08x ODMODE[%08x]: %08x\n",
-         pinsel,  pinsel  ? getreg32(pinsel) : 0,
-         pinmode, pinmode ? getreg32(pinmode) : 0,
-         g_odmode[port],    getreg32(g_odmode[port]));
+  gpioinfo("  PINSEL[%08x]: %08x PINMODE[%08x]: %08x ODMODE[%08x]: %08x\n",
+           pinsel,  pinsel  ? getreg32(pinsel) : 0,
+           pinmode, pinmode ? getreg32(pinmode) : 0,
+           g_odmode[port],    getreg32(g_odmode[port]));
 #elif defined(LPC178x)
-  llinfo("  IOCON[%08x]: %08x\n", iocon, getreg32(iocon));
+  gpioinfo("  IOCON[%08x]: %08x\n", iocon, getreg32(iocon));
 #endif
 
   base = g_fiobase[port];
-  llinfo("  FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n",
-         base+LPC11_FIO_DIR_OFFSET,  getreg32(base+LPC11_FIO_DIR_OFFSET),
-         base+LPC11_FIO_MASK_OFFSET, getreg32(base+LPC11_FIO_MASK_OFFSET),
-         base+LPC11_FIO_PIN_OFFSET,  getreg32(base+LPC11_FIO_PIN_OFFSET));
+  gpioinfo("  FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n",
+           base+LPC11_FIO_DIR_OFFSET,  getreg32(base+LPC11_FIO_DIR_OFFSET),
+           base+LPC11_FIO_MASK_OFFSET, getreg32(base+LPC11_FIO_MASK_OFFSET),
+           base+LPC11_FIO_PIN_OFFSET,  getreg32(base+LPC11_FIO_PIN_OFFSET));
 
   base = g_intbase[port];
-  llinfo("  IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n",
-         LPC11_GPIOINT_IOINTSTATUS,          getreg32(LPC11_GPIOINT_IOINTSTATUS),
-         base+LPC11_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC11_GPIOINT_INTSTATR_OFFSET),
-         base+LPC11_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC11_GPIOINT_INTSTATF_OFFSET));
-  llinfo("  INTENR[%08x]: %08x INTENF[%08x]: %08x\n",
-         base+LPC11_GPIOINT_INTENR_OFFSET,   getreg32(base+LPC11_GPIOINT_INTENR_OFFSET),
-         base+LPC11_GPIOINT_INTENF_OFFSET,   getreg32(base+LPC11_GPIOINT_INTENF_OFFSET));
+  gpioinfo("  IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n",
+           LPC11_GPIOINT_IOINTSTATUS,          getreg32(LPC11_GPIOINT_IOINTSTATUS),
+           base+LPC11_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC11_GPIOINT_INTSTATR_OFFSET),
+           base+LPC11_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC11_GPIOINT_INTSTATF_OFFSET));
+  gpioinfo("  INTENR[%08x]: %08x INTENF[%08x]: %08x\n",
+           base+LPC11_GPIOINT_INTENR_OFFSET,   getreg32(base+LPC11_GPIOINT_INTENR_OFFSET),
+           base+LPC11_GPIOINT_INTENF_OFFSET,   getreg32(base+LPC11_GPIOINT_INTENF_OFFSET));
 
   leave_critical_section(flags);
   return OK;
 }
-#endif /* CONFIG_DEBUG_GPIO */
-
+#endif /* CONFIG_DEBUG_GPIO_INFO */
diff --git a/arch/arm/src/lpc17xx/Make.defs b/arch/arm/src/lpc17xx/Make.defs
index 2d6193a41d..919f70e757 100644
--- a/arch/arm/src/lpc17xx/Make.defs
+++ b/arch/arm/src/lpc17xx/Make.defs
@@ -137,7 +137,7 @@ ifeq ($(CONFIG_GPIO_IRQ),y)
 CHIP_CSRCS += lpc17_gpioint.c
 endif
 
-ifeq ($(CONFIG_DEBUG_GPIO),y)
+ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)
 CHIP_CSRCS += lpc17_gpiodbg.c
 endif
 
diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c
index 369112368b..ef4957cba7 100644
--- a/arch/arm/src/lpc17xx/lpc17_ethernet.c
+++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c
@@ -365,7 +365,7 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac);
 
 /* Initialization functions */
 
-#if defined(CONFIG_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO)
+#if defined(CONFIG_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO)
 static void lpc17_showpins(void);
 #else
 #  define lpc17_showpins()
@@ -2292,7 +2292,7 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO)
+#if defined(CONFIG_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO)
 static void lpc17_showpins(void)
 {
   lpc17_dumpgpio(GPIO_PORT1 | GPIO_PIN0, "P1[1-15]");
diff --git a/arch/arm/src/lpc17xx/lpc17_gpio.h b/arch/arm/src/lpc17xx/lpc17_gpio.h
index e8ec133789..1129a26235 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpio.h
+++ b/arch/arm/src/lpc17xx/lpc17_gpio.h
@@ -181,7 +181,7 @@ void lpc17_gpioirqdisable(int irq);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int lpc17_dumpgpio(lpc17_pinset_t pinset, const char *msg);
 #else
 #  define lpc17_dumpgpio(p,m)
diff --git a/arch/arm/src/lpc17xx/lpc17_gpiodbg.c b/arch/arm/src/lpc17xx/lpc17_gpiodbg.c
index abe2534cdc..00d0f8fade 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpiodbg.c
+++ b/arch/arm/src/lpc17xx/lpc17_gpiodbg.c
@@ -54,15 +54,7 @@
 #include "chip.h"
 #include "lpc17_gpio.h"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#ifndef CONFIG_DEBUG_FEATURES
-#  undef CONFIG_DEBUG_GPIO
-#endif
-
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 
 /****************************************************************************
  * Private Functions
@@ -154,35 +146,36 @@ int lpc17_dumpgpio(lpc17_pinset_t pinset, const char *msg)
   /* The following requires exclusive access to the GPIO registers */
 
   flags = enter_critical_section();
-  llinfo("GPIO%c pin%d (pinset: %08x) -- %s\n",
-         port + '0', pin, pinset, msg);
+
+  gpioinfo("GPIO%c pin%d (pinset: %08x) -- %s\n",
+           port + '0', pin, pinset, msg);
 
 #if defined(LPC176x)
-  llinfo("  PINSEL[%08x]: %08x PINMODE[%08x]: %08x ODMODE[%08x]: %08x\n",
-         pinsel,  pinsel  ? getreg32(pinsel) : 0,
-         pinmode, pinmode ? getreg32(pinmode) : 0,
-         g_odmode[port],    getreg32(g_odmode[port]));
+  gpioinfo("  PINSEL[%08x]: %08x PINMODE[%08x]: %08x ODMODE[%08x]: %08x\n",
+           pinsel,  pinsel  ? getreg32(pinsel) : 0,
+           pinmode, pinmode ? getreg32(pinmode) : 0,
+           g_odmode[port],    getreg32(g_odmode[port]));
 #elif defined(LPC178x)
-  llinfo("  IOCON[%08x]: %08x\n", iocon, getreg32(iocon));
+  gpioinfo("  IOCON[%08x]: %08x\n", iocon, getreg32(iocon));
 #endif
 
   base = g_fiobase[port];
-  llinfo("  FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n",
-         base+LPC17_FIO_DIR_OFFSET,  getreg32(base+LPC17_FIO_DIR_OFFSET),
-         base+LPC17_FIO_MASK_OFFSET, getreg32(base+LPC17_FIO_MASK_OFFSET),
-         base+LPC17_FIO_PIN_OFFSET,  getreg32(base+LPC17_FIO_PIN_OFFSET));
+  gpioinfo("  FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n",
+           base+LPC17_FIO_DIR_OFFSET,  getreg32(base+LPC17_FIO_DIR_OFFSET),
+           base+LPC17_FIO_MASK_OFFSET, getreg32(base+LPC17_FIO_MASK_OFFSET),
+           base+LPC17_FIO_PIN_OFFSET,  getreg32(base+LPC17_FIO_PIN_OFFSET));
 
   base = g_intbase[port];
-  llinfo("  IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n",
-         LPC17_GPIOINT_IOINTSTATUS,          getreg32(LPC17_GPIOINT_IOINTSTATUS),
-         base+LPC17_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATR_OFFSET),
-         base+LPC17_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATF_OFFSET));
-  llinfo("  INTENR[%08x]: %08x INTENF[%08x]: %08x\n",
-         base+LPC17_GPIOINT_INTENR_OFFSET,   getreg32(base+LPC17_GPIOINT_INTENR_OFFSET),
-         base+LPC17_GPIOINT_INTENF_OFFSET,   getreg32(base+LPC17_GPIOINT_INTENF_OFFSET));
+  gpioinfo("  IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n",
+           LPC17_GPIOINT_IOINTSTATUS,          getreg32(LPC17_GPIOINT_IOINTSTATUS),
+           base+LPC17_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATR_OFFSET),
+           base+LPC17_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATF_OFFSET));
+  gpioinfo("  INTENR[%08x]: %08x INTENF[%08x]: %08x\n",
+           base+LPC17_GPIOINT_INTENR_OFFSET,   getreg32(base+LPC17_GPIOINT_INTENR_OFFSET),
+           base+LPC17_GPIOINT_INTENF_OFFSET,   getreg32(base+LPC17_GPIOINT_INTENF_OFFSET));
 
   leave_critical_section(flags);
   return OK;
 }
-#endif /* CONFIG_DEBUG_GPIO */
+#endif /* CONFIG_DEBUG_GPIO_INFO */
 
diff --git a/arch/arm/src/lpc17xx/lpc17_usbdev.c b/arch/arm/src/lpc17xx/lpc17_usbdev.c
index ef796bb0de..f96e91f6aa 100644
--- a/arch/arm/src/lpc17xx/lpc17_usbdev.c
+++ b/arch/arm/src/lpc17xx/lpc17_usbdev.c
@@ -112,7 +112,7 @@
 
 /* Dump GPIO registers */
 
-#if defined(CONFIG_LPC17_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_GPIO)
+#if defined(CONFIG_LPC17_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO)
 #  define usbdev_dumpgpio() \
    do { \
      lpc17_dumpgpio(GPIO_USB_DP, "D+ P0.29; D- P0.30"); \
diff --git a/arch/arm/src/lpc17xx/lpc17_usbhost.c b/arch/arm/src/lpc17xx/lpc17_usbhost.c
index c128b18217..7825df9672 100644
--- a/arch/arm/src/lpc17xx/lpc17_usbhost.c
+++ b/arch/arm/src/lpc17xx/lpc17_usbhost.c
@@ -114,7 +114,7 @@
 
 /* Dump GPIO registers */
 
-#if defined(CONFIG_LPC17_USBHOST_REGDEBUG) && defined(CONFIG_DEBUG_GPIO)
+#if defined(CONFIG_LPC17_USBHOST_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO)
 #  define usbhost_dumpgpio() \
    do { \
      lpc17_dumpgpio(GPIO_USB_DP, "D+ P0.29; D- P0.30"); \
diff --git a/arch/arm/src/sam34/sam4l_gpio.c b/arch/arm/src/sam34/sam4l_gpio.c
index efd97ee1b7..02394a543f 100644
--- a/arch/arm/src/sam34/sam4l_gpio.c
+++ b/arch/arm/src/sam34/sam4l_gpio.c
@@ -59,7 +59,7 @@
  * Private Data
  ****************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 static const char g_portchar[4]   = { 'A', 'B', 'C', 'D' };
 #endif
 
@@ -522,7 +522,7 @@ bool sam_gpioread(gpio_pinset_t pinset)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int sam_dumpgpio(uint32_t pinset, const char *msg)
 {
   irqstate_t    flags;
@@ -539,23 +539,25 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
   /* The following requires exclusive access to the GPIO registers */
 
   flags = enter_critical_section();
-  llerr("GPIO%c pinset: %08x base: %08x -- %s\n",
-        g_portchar[port], pinset, base, msg);
-  llerr("    GPER: %08x  PMR0: %08x  PMR1: %08x  PMR2: %08x\n",
-        getreg32(base + SAM_GPIO_GPER_OFFSET), getreg32(base + SAM_GPIO_PMR0_OFFSET),
-        getreg32(base + SAM_GPIO_PMR1_OFFSET), getreg32(base + SAM_GPIO_PMR2_OFFSET));
-  llerr("   ODER: %08x   OVR: %08x   PVR:  %08x  PUER: %08x\n",
-        getreg32(base + SAM_GPIO_ODER_OFFSET), getreg32(base + SAM_GPIO_OVR_OFFSET),
-        getreg32(base + SAM_GPIO_PVR_OFFSET), getreg32(base + SAM_GPIO_PUER_OFFSET));
-  llerr("   PDER: %08x    IER: %08x  IMR0: %08x  IMR1: %08x\n",
-        getreg32(base + SAM_GPIO_PDER_OFFSET), getreg32(base + SAM_GPIO_IER_OFFSET),
-        getreg32(base + SAM_GPIO_IMR0_OFFSET), getreg32(base + SAM_GPIO_IMR1_OFFSET));
-  llerr("   GFER: %08x    IFR: %08x ODCR0: %08x ODCR1: %08x\n",
-        getreg32(base + SAM_GPIO_GFER_OFFSET), getreg32(base + SAM_GPIO_IFR_OFFSET),
-        getreg32(base + SAM_GPIO_ODCR0_OFFSET), getreg32(base + SAM_GPIO_ODCR1_OFFSET));
-  llerr("  OSRR0: %08x   EVER: %08x PARAM: %08x  VERS: %08x\n",
-        getreg32(base + SAM_GPIO_OSRR0_OFFSET), getreg32(base + SAM_GPIO_EVER_OFFSET),
-        getreg32(base + SAM_GPIO_PARAMETER_OFFSET), getreg32(base + SAM_GPIO_VERSION_OFFSET));
+
+  gpioinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
+           g_portchar[port], pinset, base, msg);
+  gpioinfo("    GPER: %08x  PMR0: %08x  PMR1: %08x  PMR2: %08x\n",
+           getreg32(base + SAM_GPIO_GPER_OFFSET), getreg32(base + SAM_GPIO_PMR0_OFFSET),
+           getreg32(base + SAM_GPIO_PMR1_OFFSET), getreg32(base + SAM_GPIO_PMR2_OFFSET));
+  gpioinfo("   ODER: %08x   OVR: %08x   PVR:  %08x  PUER: %08x\n",
+           getreg32(base + SAM_GPIO_ODER_OFFSET), getreg32(base + SAM_GPIO_OVR_OFFSET),
+           getreg32(base + SAM_GPIO_PVR_OFFSET), getreg32(base + SAM_GPIO_PUER_OFFSET));
+  gpioinfo("   PDER: %08x    IER: %08x  IMR0: %08x  IMR1: %08x\n",
+           getreg32(base + SAM_GPIO_PDER_OFFSET), getreg32(base + SAM_GPIO_IER_OFFSET),
+           getreg32(base + SAM_GPIO_IMR0_OFFSET), getreg32(base + SAM_GPIO_IMR1_OFFSET));
+  gpioinfo("   GFER: %08x    IFR: %08x ODCR0: %08x ODCR1: %08x\n",
+           getreg32(base + SAM_GPIO_GFER_OFFSET), getreg32(base + SAM_GPIO_IFR_OFFSET),
+           getreg32(base + SAM_GPIO_ODCR0_OFFSET), getreg32(base + SAM_GPIO_ODCR1_OFFSET));
+  gpioinfo("  OSRR0: %08x   EVER: %08x PARAM: %08x  VERS: %08x\n",
+           getreg32(base + SAM_GPIO_OSRR0_OFFSET), getreg32(base + SAM_GPIO_EVER_OFFSET),
+           getreg32(base + SAM_GPIO_PARAMETER_OFFSET), getreg32(base + SAM_GPIO_VERSION_OFFSET));
+
   leave_critical_section(flags);
   return OK;
 }
diff --git a/arch/arm/src/sam34/sam_gpio.c b/arch/arm/src/sam34/sam_gpio.c
index 78f5e1aff1..89461c5836 100644
--- a/arch/arm/src/sam34/sam_gpio.c
+++ b/arch/arm/src/sam34/sam_gpio.c
@@ -70,7 +70,7 @@
  * Private Data
  ****************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 static const char g_portchar[4]   = { 'A', 'B', 'C', 'D' };
 #endif
 
@@ -473,7 +473,7 @@ bool sam_gpioread(gpio_pinset_t pinset)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int sam_dumpgpio(uint32_t pinset, const char *msg)
 {
   irqstate_t    flags;
@@ -488,44 +488,46 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
   /* The following requires exclusive access to the GPIO registers */
 
   flags = enter_critical_section();
-  llerr("PIO%c pinset: %08x base: %08x -- %s\n",
+
+  gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n",
         g_portchar[port], pinset, base, msg);
-  llerr("    PSR: %08x    OSR: %08x   IFSR: %08x   ODSR: %08x\n",
-        getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
-        getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET));
-  llerr("   PDSR: %08x    IMR: %08x    ISR: %08x   MDSR: %08x\n",
-        getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
-        getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
+  gpioinfo("    PSR: %08x    OSR: %08x   IFSR: %08x   ODSR: %08x\n",
+           getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
+           getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET));
+  gpioinfo("   PDSR: %08x    IMR: %08x    ISR: %08x   MDSR: %08x\n",
+           getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
+           getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
 #if defined(CONFIG_ARCH_CHIP_SAM3U)
-  llerr("   ABSR: %08x SCIFSR: %08x  DIFSR: %08x IFDGSR: %08x\n",
-        getreg32(base + SAM_PIO_ABSR_OFFSET), getreg32(base + SAM_PIO_SCIFSR_OFFSET),
-        getreg32(base + SAM_PIO_DIFSR_OFFSET), getreg32(base + SAM_PIO_IFDGSR_OFFSET));
+  gpioinfo("   ABSR: %08x SCIFSR: %08x  DIFSR: %08x IFDGSR: %08x\n",
+           getreg32(base + SAM_PIO_ABSR_OFFSET), getreg32(base + SAM_PIO_SCIFSR_OFFSET),
+           getreg32(base + SAM_PIO_DIFSR_OFFSET), getreg32(base + SAM_PIO_IFDGSR_OFFSET));
 #elif defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
-  llerr(" ABCDSR: %08x %08x         IFSCSR: %08x  PPDSR: %08x\n",
-        getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
-        getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_PPDSR_OFFSET));
+  gpioinfo(" ABCDSR: %08x %08x         IFSCSR: %08x  PPDSR: %08x\n",
+           getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
+           getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_PPDSR_OFFSET));
 #endif
-  llerr("   PUSR: %08x   SCDR: %08x   OWSR: %08x  AIMMR: %08x\n",
-        getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
-        getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET));
-  llerr("    ESR: %08x    LSR: %08x   ELSR: %08x FELLSR: %08x\n",
-        getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET),
-        getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET));
-  llerr(" FRLHSR: %08x LOCKSR: %08x   WPMR: %08x   WPSR: %08x\n",
-        getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
-        getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
+  gpioinfo("   PUSR: %08x   SCDR: %08x   OWSR: %08x  AIMMR: %08x\n",
+           getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
+           getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET));
+  gpioinfo("    ESR: %08x    LSR: %08x   ELSR: %08x FELLSR: %08x\n",
+           getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET),
+           getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET));
+  gpioinfo(" FRLHSR: %08x LOCKSR: %08x   WPMR: %08x   WPSR: %08x\n",
+           getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
+           getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
 #if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
-  llerr("   PCMR: %08x  PCIMR: %08x  PCISR: %08x   PCRHR: %08x\n",
-        getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
-        getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
+  gpioinfo("   PCMR: %08x  PCIMR: %08x  PCISR: %08x   PCRHR: %08x\n",
+           getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
+           getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
 #ifdef CONFIG_ARCH_CHIP_SAM4E
-  llerr("SCHMITT: %08x DELAYR:%08x\n",
-        getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DELAYR_OFFSET));
+  gpioinfo("SCHMITT: %08x DELAYR:%08x\n",
+           getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DELAYR_OFFSET));
 #else
-  llerr("SCHMITT: %08x\n",
-        getreg32(base + SAM_PIO_SCHMITT_OFFSET));
+  gpioinfo("SCHMITT: %08x\n",
+           getreg32(base + SAM_PIO_SCHMITT_OFFSET));
 #endif
 #endif
+
   leave_critical_section(flags);
   return OK;
 }
diff --git a/arch/arm/src/sam34/sam_gpio.h b/arch/arm/src/sam34/sam_gpio.h
index 32d579a12c..a5cbe6e3e3 100644
--- a/arch/arm/src/sam34/sam_gpio.h
+++ b/arch/arm/src/sam34/sam_gpio.h
@@ -77,24 +77,12 @@
 #  undef CONFIG_SAM34_GPIO_IRQ
 #endif
 
-#ifndef CONFIG_DEBUG_FEATURES
-#  undef CONFIG_DEBUG_GPIO
-#endif
-
 /************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Inline Functions
+ * Public Function Prototypes
  ************************************************************************************/
 
 #ifndef __ASSEMBLY__
 
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
 #undef EXTERN
 #if defined(__cplusplus)
 #define EXTERN extern "C"
@@ -104,10 +92,6 @@ extern "C"
 #define EXTERN extern
 #endif
 
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
 /************************************************************************************
  * Name: sam_gpioirqinitialize
  *
@@ -202,7 +186,7 @@ void sam_gpioirqdisable(int irq);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int sam_dumpgpio(uint32_t pinset, const char *msg);
 #else
 #  define sam_dumpgpio(p,m)
diff --git a/arch/arm/src/sama5/sam_pio.h b/arch/arm/src/sama5/sam_pio.h
index 2b867ea05a..fbcf94d034 100644
--- a/arch/arm/src/sama5/sam_pio.h
+++ b/arch/arm/src/sama5/sam_pio.h
@@ -214,7 +214,7 @@ void sam_pio_forceclk(pio_pinset_t pinset, bool enable);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int sam_dumppio(uint32_t pinset, const char *msg);
 #else
 #  define sam_dumppio(p,m)
diff --git a/arch/arm/src/sama5/sama5d2x_pio.c b/arch/arm/src/sama5/sama5d2x_pio.c
index 1ca67e45bd..3a87d3da66 100644
--- a/arch/arm/src/sama5/sama5d2x_pio.c
+++ b/arch/arm/src/sama5/sama5d2x_pio.c
@@ -118,7 +118,7 @@ const uintptr_t g_spiobase[SAM_NPIO] =
  ****************************************************************************/
 /* Maps a port number to the standard port character */
 
-#if defined(CONFIG_DEBUG_GPIO) && SAM_NPIO > 0
+#if defined(CONFIG_DEBUG_GPIO_INFO) && SAM_NPIO > 0
 static const char g_portchar[SAM_NPIO] =
 {
   'A'
@@ -610,7 +610,7 @@ void sam_pio_forceclk(pio_pinset_t pinset, bool enable)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int sam_dumppio(uint32_t pinset, const char *msg)
 {
   irqstate_t    flags;
@@ -630,32 +630,32 @@ int sam_dumppio(uint32_t pinset, const char *msg)
 
   if (secure)
     {
-      llerr("SPIO%c pinset: %08x base: %08x -- %s\n",
+      gpioinfo("SPIO%c pinset: %08x base: %08x -- %s\n",
              g_portchar[port], pinset, base, msg);
     }
   else
     {
-      llerr("PIO%c pinset: %08x base: %08x -- %s\n",
+      gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n",
              g_portchar[port], pinset, base, msg);
     }
 
-  llerr("   MSKR: %08x   CFGR: %08x   PDSR: %08x LOCKSR: %08x\n",
-        getreg32(base + SAM_PIO_MSKR_OFFSET), getreg32(base + SAM_PIO_CFGR_OFFSET),
-        getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET));
-  llerr("   ODSR: %08x    IMR: %08x    ISR: %08x\n",
-        getreg32(base + SAM_PIO_ODSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
-        getreg32(base + SAM_PIO_ISR_OFFSET));
+  gpioinfo("   MSKR: %08x   CFGR: %08x   PDSR: %08x LOCKSR: %08x\n",
+          getreg32(base + SAM_PIO_MSKR_OFFSET), getreg32(base + SAM_PIO_CFGR_OFFSET),
+          getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET));
+  gpioinfo("   ODSR: %08x    IMR: %08x    ISR: %08x\n",
+          getreg32(base + SAM_PIO_ODSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
+          getreg32(base + SAM_PIO_ISR_OFFSET));
 
   if (secure)
     {
-      llerr("   SCDR: %08x   WPMR: %08x   WPSR: %08x  IOSSR: %08x\n",
-            getreg32(SAM_SPIO_SCDR), getreg32(SAM_SPIO_WPMR),
-            getreg32(SAM_SPIO_WPSR), getreg32(base + SAM_SPIO_IOSSR_OFFSET));
+      gpioinfo("   SCDR: %08x   WPMR: %08x   WPSR: %08x  IOSSR: %08x\n",
+              getreg32(SAM_SPIO_SCDR), getreg32(SAM_SPIO_WPMR),
+              getreg32(SAM_SPIO_WPSR), getreg32(base + SAM_SPIO_IOSSR_OFFSET));
     }
   else
     {
-      llerr("   WPMR: %08x   WPSR: %08x\n",
-            getreg32(SAM_PIO_WPMR), getreg32(SAM_PIO_WPSR));
+      gpioinfo("   WPMR: %08x   WPSR: %08x\n",
+              getreg32(SAM_PIO_WPMR), getreg32(SAM_PIO_WPSR));
     }
 
   leave_critical_section(flags);
diff --git a/arch/arm/src/sama5/sama5d2x_pio.h b/arch/arm/src/sama5/sama5d2x_pio.h
index 6f4f28f9a4..4b0324dc96 100644
--- a/arch/arm/src/sama5/sama5d2x_pio.h
+++ b/arch/arm/src/sama5/sama5d2x_pio.h
@@ -58,10 +58,6 @@
 #  undef CONFIG_SAMA5_PIO_IRQ
 #endif
 
-#ifndef CONFIG_DEBUG_FEATURES
-#  undef CONFIG_DEBUG_GPIO
-#endif
-
 #define PIO_HAVE_PULLDOWN         1
 #define PIO_HAVE_PERIPHCD         1
 #define PIO_HAVE_SCHMITT          1
diff --git a/arch/arm/src/sama5/sama5d3x4x_pio.c b/arch/arm/src/sama5/sama5d3x4x_pio.c
index 5bd0e765f2..0165a382ac 100644
--- a/arch/arm/src/sama5/sama5d3x4x_pio.c
+++ b/arch/arm/src/sama5/sama5d3x4x_pio.c
@@ -40,13 +40,6 @@
 
 #include <nuttx/config.h>
 
-#ifdef CONFIG_DEBUG_GPIO
-/* Output informational debug info even if debug output is not enabled. */
-
-#  undef  CONFIG_DEBUG_INFO
-#  define CONFIG_DEBUG_INFO 1
-#endif
-
 #include <stdint.h>
 #include <time.h>
 #include <errno.h>
@@ -102,7 +95,7 @@ const uintptr_t g_piobase[SAM_NPIO] =
  ****************************************************************************/
 /* Maps a port number to the standard port character */
 
-#if defined(CONFIG_DEBUG_GPIO) && SAM_NPIO > 0
+#if defined(CONFIG_DEBUG_GPIO_INFO) && SAM_NPIO > 0
 static const char g_portchar[SAM_NPIO] =
 {
   'A'
@@ -857,7 +850,7 @@ void sam_pio_forceclk(pio_pinset_t pinset, bool enable)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int sam_dumppio(uint32_t pinset, const char *msg)
 {
   irqstate_t    flags;
@@ -872,41 +865,42 @@ int sam_dumppio(uint32_t pinset, const char *msg)
   /* The following requires exclusive access to the PIO registers */
 
   flags = enter_critical_section();
-  llinfo("PIO%c pinset: %08x base: %08x -- %s\n",
+
+  gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n",
          g_portchar[port], pinset, base, msg);
 
 #ifdef SAM_PIO_ISLR_OFFSET
-  llinfo("    PSR: %08x   ISLR: %08x    OSR: %08x   IFSR: %08x\n",
-         getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_ISLR_OFFSET),
-         getreg32(base + SAM_PIO_OSR_OFFSET), getreg32(base + SAM_PIO_IFSR_OFFSET));
+  gpioinfo("    PSR: %08x   ISLR: %08x    OSR: %08x   IFSR: %08x\n",
+           getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_ISLR_OFFSET),
+           getreg32(base + SAM_PIO_OSR_OFFSET), getreg32(base + SAM_PIO_IFSR_OFFSET));
 #else
-  llinfo("    PSR: %08x    OSR: %08x   IFSR: %08x\n",
-         getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
-         getreg32(base + SAM_PIO_IFSR_OFFSET));
+  gpioinfo("    PSR: %08x    OSR: %08x   IFSR: %08x\n",
+           getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
+           getreg32(base + SAM_PIO_IFSR_OFFSET));
 #endif
-  llinfo("   ODSR: %08x   PDSR: %08x    IMR: %08x    ISR: %08x\n",
-         getreg32(base + SAM_PIO_ODSR_OFFSET), getreg32(base + SAM_PIO_PDSR_OFFSET),
-         getreg32(base + SAM_PIO_IMR_OFFSET), getreg32(base + SAM_PIO_ISR_OFFSET));
-  llinfo("   MDSR: %08x   PUSR: %08x ABDCSR: %08x %08x\n",
-         getreg32(base + SAM_PIO_MDSR_OFFSET), getreg32(base + SAM_PIO_PUSR_OFFSET),
-         getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET));
-  llinfo(" IFSCSR: %08x   SCDR: %08x  PPDSR: %08x   OWSR: %08x\n",
-         getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
-         getreg32(base + SAM_PIO_PPDSR_OFFSET), getreg32(base + SAM_PIO_OWSR_OFFSET));
+  gpioinfo("   ODSR: %08x   PDSR: %08x    IMR: %08x    ISR: %08x\n",
+           getreg32(base + SAM_PIO_ODSR_OFFSET), getreg32(base + SAM_PIO_PDSR_OFFSET),
+           getreg32(base + SAM_PIO_IMR_OFFSET), getreg32(base + SAM_PIO_ISR_OFFSET));
+  gpioinfo("   MDSR: %08x   PUSR: %08x ABDCSR: %08x %08x\n",
+           getreg32(base + SAM_PIO_MDSR_OFFSET), getreg32(base + SAM_PIO_PUSR_OFFSET),
+           getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET));
+  gpioinfo(" IFSCSR: %08x   SCDR: %08x  PPDSR: %08x   OWSR: %08x\n",
+           getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
+           getreg32(base + SAM_PIO_PPDSR_OFFSET), getreg32(base + SAM_PIO_OWSR_OFFSET));
 #ifdef SAM_PIO_LOCKSR_OFFSET
-  llinfo("  AIMMR: %08x   ELSR: %08x FRLHSR: %08x LOCKSR: %08x\n",
-         getreg32(base + SAM_PIO_AIMMR_OFFSET), getreg32(base + SAM_PIO_ELSR_OFFSET),
-         getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET));
+  gpioinfo("  AIMMR: %08x   ELSR: %08x FRLHSR: %08x LOCKSR: %08x\n",
+           getreg32(base + SAM_PIO_AIMMR_OFFSET), getreg32(base + SAM_PIO_ELSR_OFFSET),
+           getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET));
 #else
-  llinfo("  AIMMR: %08x   ELSR: %08x FRLHSR: %08x\n",
-         getreg32(base + SAM_PIO_AIMMR_OFFSET), getreg32(base + SAM_PIO_ELSR_OFFSET),
-         getreg32(base + SAM_PIO_FRLHSR_OFFSET));
+  gpioinfo("  AIMMR: %08x   ELSR: %08x FRLHSR: %08x\n",
+           getreg32(base + SAM_PIO_AIMMR_OFFSET), getreg32(base + SAM_PIO_ELSR_OFFSET),
+           getreg32(base + SAM_PIO_FRLHSR_OFFSET));
 #endif
-  llinfo("SCHMITT: %08x DRIVER: %08x %08x\n",
-         getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DRIVER1_OFFSET),
-         getreg32(base + SAM_PIO_DRIVER2_OFFSET));
-  llinfo("   WPMR: %08x   WPSR: %08x\n",
-         getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
+  gpioinfo("SCHMITT: %08x DRIVER: %08x %08x\n",
+           getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DRIVER1_OFFSET),
+           getreg32(base + SAM_PIO_DRIVER2_OFFSET));
+  gpioinfo("   WPMR: %08x   WPSR: %08x\n",
+           getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
 
   leave_critical_section(flags);
   return OK;
diff --git a/arch/arm/src/sama5/sama5d3x4x_pio.h b/arch/arm/src/sama5/sama5d3x4x_pio.h
index 86ae201745..cd5f1d3a59 100644
--- a/arch/arm/src/sama5/sama5d3x4x_pio.h
+++ b/arch/arm/src/sama5/sama5d3x4x_pio.h
@@ -52,10 +52,6 @@
 #  undef CONFIG_SAMA5_PIO_IRQ
 #endif
 
-#ifndef CONFIG_DEBUG_FEATURES
-#  undef CONFIG_DEBUG_GPIO
-#endif
-
 #define PIO_HAVE_PULLDOWN         1
 #define PIO_HAVE_PERIPHCD         1
 #define PIO_HAVE_SCHMITT          1
diff --git a/arch/arm/src/samv7/sam_gpio.c b/arch/arm/src/samv7/sam_gpio.c
index eeb716686e..9b322f8381 100644
--- a/arch/arm/src/samv7/sam_gpio.c
+++ b/arch/arm/src/samv7/sam_gpio.c
@@ -86,7 +86,7 @@
  * Private Data
  ****************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 static const char g_portchar[SAMV7_NPIO] =
 {
     'A'
@@ -563,7 +563,7 @@ bool sam_gpioread(gpio_pinset_t pinset)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int sam_dumpgpio(uint32_t pinset, const char *msg)
 {
   irqstate_t    flags;
@@ -578,40 +578,42 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
   /* The following requires exclusive access to the GPIO registers */
 
   flags = enter_critical_section();
-  llerr("PIO%c pinset: %08x base: %08x -- %s\n",
-        g_portchar[port], pinset, base, msg);
-  llerr("    PSR: %08x    OSR: %08x   IFSR: %08x   ODSR: %08x\n",
-        getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
-        getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET));
-  llerr("   PDSR: %08x    IMR: %08x    ISR: %08x   MDSR: %08x\n",
-        getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
-        getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
-  llerr(" ABCDSR: %08x %08x         IFSCSR: %08x  PPDSR: %08x\n",
-        getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
-        getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_PPDSR_OFFSET));
-  llerr("   PUSR: %08x   SCDR: %08x   OWSR: %08x  AIMMR: %08x\n",
-        getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
-        getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET));
-  llerr("    ESR: %08x    LSR: %08x   ELSR: %08x FELLSR: %08x\n",
-        getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET),
-        getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET));
-  llerr(" FRLHSR: %08x LOCKSR: %08x   WPMR: %08x   WPSR: %08x\n",
-        getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
-        getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
-  llerr("   PCMR: %08x  PCIMR: %08x  PCISR: %08x   PCRHR: %08x\n",
-        getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
-        getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
-  llerr("SCHMITT: %08x DRIVER:%08x\n",
-        getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DRIVER_OFFSET));
-  llerr("    KER: %08x   KRCR: %08x    KDR: %08x   KIMR: %08x\n",
-        getreg32(base + SAM_PIO_KER_OFFSET), getreg32(base + SAM_PIO_KRCR_OFFSET),
-        getreg32(base + SAM_PIO_KDR_OFFSET), getreg32(base + SAM_PIO_KIMR_OFFSET));
-  llerr("    KSR: %08x   KKPR: %08x    KKRR: %08x\n",
-        getreg32(base + SAM_PIO_KSR_OFFSET), getreg32(base + SAM_PIO_KKPR_OFFSET),
-        getreg32(base + SAM_PIO_KKRR_OFFSET));
-  llerr("   PCMR: %08x  PCIMR: %08x  PCISR: %08x  PCRHR: %08x\n",
-        getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
-        getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
+
+  gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n",
+           g_portchar[port], pinset, base, msg);
+  gpioinfo("    PSR: %08x    OSR: %08x   IFSR: %08x   ODSR: %08x\n",
+           getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
+           getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET));
+  gpioinfo("   PDSR: %08x    IMR: %08x    ISR: %08x   MDSR: %08x\n",
+           getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
+           getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
+  gpioinfo(" ABCDSR: %08x %08x         IFSCSR: %08x  PPDSR: %08x\n",
+           getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
+           getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_PPDSR_OFFSET));
+  gpioinfo("   PUSR: %08x   SCDR: %08x   OWSR: %08x  AIMMR: %08x\n",
+           getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
+           getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET));
+  gpioinfo("    ESR: %08x    LSR: %08x   ELSR: %08x FELLSR: %08x\n",
+           getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET),
+           getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET));
+  gpioinfo(" FRLHSR: %08x LOCKSR: %08x   WPMR: %08x   WPSR: %08x\n",
+           getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
+           getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
+  gpioinfo("   PCMR: %08x  PCIMR: %08x  PCISR: %08x   PCRHR: %08x\n",
+           getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
+           getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
+  gpioinfo("SCHMITT: %08x DRIVER:%08x\n",
+           getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DRIVER_OFFSET));
+  gpioinfo("    KER: %08x   KRCR: %08x    KDR: %08x   KIMR: %08x\n",
+           getreg32(base + SAM_PIO_KER_OFFSET), getreg32(base + SAM_PIO_KRCR_OFFSET),
+           getreg32(base + SAM_PIO_KDR_OFFSET), getreg32(base + SAM_PIO_KIMR_OFFSET));
+  gpioinfo("    KSR: %08x   KKPR: %08x    KKRR: %08x\n",
+           getreg32(base + SAM_PIO_KSR_OFFSET), getreg32(base + SAM_PIO_KKPR_OFFSET),
+           getreg32(base + SAM_PIO_KKRR_OFFSET));
+  gpioinfo("   PCMR: %08x  PCIMR: %08x  PCISR: %08x  PCRHR: %08x\n",
+           getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
+           getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
+
   leave_critical_section(flags);
   return OK;
 }
diff --git a/arch/arm/src/samv7/sam_gpio.h b/arch/arm/src/samv7/sam_gpio.h
index 2e564ec787..e6746da397 100644
--- a/arch/arm/src/samv7/sam_gpio.h
+++ b/arch/arm/src/samv7/sam_gpio.h
@@ -377,7 +377,7 @@ void sam_gpioirqdisable(int irq);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int sam_dumpgpio(uint32_t pinset, const char *msg);
 #else
 #  define sam_dumpgpio(p,m)
diff --git a/arch/arm/src/tiva/Make.defs b/arch/arm/src/tiva/Make.defs
index cb56488175..fdedfefe4c 100644
--- a/arch/arm/src/tiva/Make.defs
+++ b/arch/arm/src/tiva/Make.defs
@@ -78,6 +78,8 @@ endif
 CHIP_ASRCS  =
 CHIP_CSRCS  = tiva_allocateheap.c tiva_start.c tiva_irq.c tiva_gpio.c
 CHIP_CSRCS += tiva_gpioirq.c tiva_lowputc.c tiva_serial.c tiva_ssi.c
+
+ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)
 CHIP_CSRCS += tiva_dumpgpio.c
 
 ifeq ($(CONFIG_ARCH_CHIP_TM4C129),y)
diff --git a/arch/arm/src/tiva/tiva_dumpgpio.c b/arch/arm/src/tiva/tiva_dumpgpio.c
index dff948c376..b50e8fa0f5 100644
--- a/arch/arm/src/tiva/tiva_dumpgpio.c
+++ b/arch/arm/src/tiva/tiva_dumpgpio.c
@@ -139,9 +139,9 @@ static inline uint8_t tiva_gpioport(int port)
  *
  ****************************************************************************/
 
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int tiva_dumpgpio(uint32_t pinset, const char *msg)
 {
-#ifdef CONFIG_DEBUG_FEATURES
   irqstate_t   flags;
   unsigned int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
   uintptr_t    base;
@@ -168,35 +168,34 @@ int tiva_dumpgpio(uint32_t pinset, const char *msg)
   enabled  = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0);
 #endif
 
-  llinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
-        tiva_gpioport(port), pinset, base, msg);
+  gpioinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
+           tiva_gpioport(port), pinset, base, msg);
 #ifdef TIVA_SYSCON_RCGCGPIO
-  llinfo("RCGCGPIO: %08x (%s)\n",
-        rcgcgpio, enabled ? "enabled" : "disabled");
+  gpioinfo("RCGCGPIO: %08x (%s)\n",
+           rcgcgpio, enabled ? "enabled" : "disabled");
 #else
-  llinfo("   RCGC2: %08x (%s)\n",
-        rcgc2, enabled ? "enabled" : "disabled");
+  gpioinfo("   RCGC2: %08x (%s)\n",
+           rcgc2, enabled ? "enabled" : "disabled");
 #endif
 
   /* Don't bother with the rest unless the port is enabled */
 
   if (enabled)
     {
-      llinfo("   AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n",
-             getreg32(base + TIVA_GPIO_AFSEL_OFFSET), getreg32(base + TIVA_GPIO_DEN_OFFSET),
-             getreg32(base + TIVA_GPIO_DIR_OFFSET), getreg32(base + TIVA_GPIO_DATA_OFFSET + 0x3fc));
-      llinfo("      IS:  %02x IBE: %02x IEV: %02x IM:  %02x RIS: %08x MIS: %08x\n",
-             getreg32(base + TIVA_GPIO_IEV_OFFSET), getreg32(base + TIVA_GPIO_IM_OFFSET),
-             getreg32(base + TIVA_GPIO_RIS_OFFSET), getreg32(base + TIVA_GPIO_MIS_OFFSET));
-      llinfo("     2MA:  %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n",
-             getreg32(base + TIVA_GPIO_DR2R_OFFSET), getreg32(base + TIVA_GPIO_DR4R_OFFSET),
-             getreg32(base + TIVA_GPIO_DR8R_OFFSET), getreg32(base + TIVA_GPIO_ODR_OFFSET),
-             getreg32(base + TIVA_GPIO_PUR_OFFSET), getreg32(base + TIVA_GPIO_PDR_OFFSET),
-             getreg32(base + TIVA_GPIO_SLR_OFFSET));
+      gpioinfo("   AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n",
+               getreg32(base + TIVA_GPIO_AFSEL_OFFSET), getreg32(base + TIVA_GPIO_DEN_OFFSET),
+               getreg32(base + TIVA_GPIO_DIR_OFFSET), getreg32(base + TIVA_GPIO_DATA_OFFSET + 0x3fc));
+      gpioinfo("      IS:  %02x IBE: %02x IEV: %02x IM:  %02x RIS: %08x MIS: %08x\n",
+               getreg32(base + TIVA_GPIO_IEV_OFFSET), getreg32(base + TIVA_GPIO_IM_OFFSET),
+               getreg32(base + TIVA_GPIO_RIS_OFFSET), getreg32(base + TIVA_GPIO_MIS_OFFSET));
+      gpioinfo("     2MA:  %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n",
+               getreg32(base + TIVA_GPIO_DR2R_OFFSET), getreg32(base + TIVA_GPIO_DR4R_OFFSET),
+               getreg32(base + TIVA_GPIO_DR8R_OFFSET), getreg32(base + TIVA_GPIO_ODR_OFFSET),
+               getreg32(base + TIVA_GPIO_PUR_OFFSET), getreg32(base + TIVA_GPIO_PDR_OFFSET),
+               getreg32(base + TIVA_GPIO_SLR_OFFSET));
     }
 
   leave_critical_section(flags);
-#endif /* CONFIG_DEBUG_FEATURES */
-
   return OK;
 }
+#endif /* CONFIG_DEBUG_GPIO_INFO */
diff --git a/arch/arm/src/tiva/tiva_gpio.c b/arch/arm/src/tiva/tiva_gpio.c
index 4acbc6076e..5d009d7864 100644
--- a/arch/arm/src/tiva/tiva_gpio.c
+++ b/arch/arm/src/tiva/tiva_gpio.c
@@ -732,13 +732,17 @@ static inline void tiva_interrupt(uint32_t pinset)
 
   modifyreg32(base + TIVA_GPIO_IEV_OFFSET, ievclr, ievset);
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
   uint32_t regval;
+
   gpioinfo("reg expected actual: [interrupt type=%d]\n", inttype);
+
   regval = (getreg32(base+TIVA_GPIO_IS_OFFSET) & pin) ? pin : 0;
   gpioinfo("IS  0x%08x 0x%08x\n", isset, regval);
+
   regval = (getreg32(base+TIVA_GPIO_IBE_OFFSET) & pin) ? pin : 0;
   gpioinfo("IBE 0x%08x 0x%08x\n", ibeset, regval);
+
   regval = (getreg32(base+TIVA_GPIO_IEV_OFFSET) & pin) ? pin : 0;
   gpioinfo("IEV 0x%08x 0x%08x\n", ievset, regval);
 #endif
@@ -987,16 +991,12 @@ void tiva_gpio_lockport(uint32_t pinset, bool lock)
 
   if (lock)
     {
-#ifdef CONFIG_DEBUG_GPIO
       gpioinfo("  locking port=%d pin=%d\n", port, pinno);
-#endif
       modifyreg32(base + TIVA_GPIO_CR_OFFSET, pinmask, 0);
     }
   else
     {
-#ifdef CONFIG_DEBUG_GPIO
       gpioinfo("unlocking port=%d pin=%d\n", port, pinno);
-#endif
       modifyreg32(base + TIVA_GPIO_CR_OFFSET, 0, pinmask);
     }
 
diff --git a/arch/arm/src/tiva/tiva_gpio.h b/arch/arm/src/tiva/tiva_gpio.h
index 17f3957f07..a20dccc15f 100644
--- a/arch/arm/src/tiva/tiva_gpio.h
+++ b/arch/arm/src/tiva/tiva_gpio.h
@@ -319,47 +319,17 @@
 #  define GPIO_PIN_6                  (6 << GPIO_PIN_SHIFT)
 #  define GPIO_PIN_7                  (7 << GPIO_PIN_SHIFT)
 
-/* Debug ********************************************************************/
-
-#ifndef CONFIG_DEBUG_FEATURES
-#  undef CONFIG_DEBUG_GPIO
-#endif
-
-#ifdef CONFIG_DEBUG_GPIO
-# define gpioerr(format, ...)    err(format, ##__VA_ARGS__)
-# define gpiollerr(format, ...)  llerr(format, ##__VA_ARGS__)
-# define gpioinfo(format, ...)   info(format, ##__VA_ARGS__)
-# define gpiollinfo(format, ...) llinfo(format, ##__VA_ARGS__)
-#else
-# define gpioerr(x...)
-# define gpiollerr(x...)
-# define gpioinfo(x...)
-# define gpiollinfo(x...)
-#endif
-
 /****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline Functions
+ * Public Function Prototypes
  ****************************************************************************/
 
 #ifndef __ASSEMBLY__
 
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
 #if defined(__cplusplus)
 extern "C"
 {
 #endif
 
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
 uintptr_t tiva_gpiobaseaddress(unsigned int port);
 
 /****************************************************************************
@@ -413,8 +383,18 @@ int tiva_dumpgpio(uint32_t pinset, const char *msg);
 
 void tiva_gpio_lockport(uint32_t pinset, bool lock);
 
-#ifdef CONFIG_DEBUG_GPIO
+/****************************************************************************
+ * Function:  tiva_dumpgpio
+ *
+ * Description:
+ *   Dump all GPIO registers associated with the provided base address
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_GPIO_INFO
 void tiva_gpio_dumpconfig(uint32_t pinset);
+#else
+# define tiva_gpio_dumpconfig(p)
 #endif
 
 #ifdef CONFIG_TIVA_GPIO_IRQS
diff --git a/arch/hc/src/m9s12/Make.defs b/arch/hc/src/m9s12/Make.defs
index 809a0696c3..97fc4861a9 100644
--- a/arch/hc/src/m9s12/Make.defs
+++ b/arch/hc/src/m9s12/Make.defs
@@ -50,6 +50,6 @@ ifneq ($(CONFIG_SCHED_TICKLESS),y)
 CHIP_CSRCS += m9s12_timerisr.c
 endif
 
-ifeq ($(CONFIG_DEBUG_GPIO),y)
+ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)
 CHIP_CSRCS+= m9s12_dumpgpio.c
 endif
diff --git a/arch/hc/src/m9s12/m9s12.h b/arch/hc/src/m9s12/m9s12.h
index e6c98244de..9a1c971159 100644
--- a/arch/hc/src/m9s12/m9s12.h
+++ b/arch/hc/src/m9s12/m9s12.h
@@ -294,7 +294,7 @@ void hcs12_gpioirqdisable(int irq);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int hcs12_dumpgpio(uint16_t pinset, const char *msg);
 #else
 #  define hcs12_dumpgpio(p,m)
diff --git a/arch/hc/src/m9s12/m9s12_dumpgpio.c b/arch/hc/src/m9s12/m9s12_dumpgpio.c
index 9a4ae61a65..ad6ce5860f 100644
--- a/arch/hc/src/m9s12/m9s12_dumpgpio.c
+++ b/arch/hc/src/m9s12/m9s12_dumpgpio.c
@@ -55,7 +55,7 @@
 #include "m9s12_pim.h"
 #include "m9s12_mebi.h"
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -172,39 +172,39 @@ static inline void hcs12_pimdump(uint8_t portndx)
 
   if (portndx >= HCS12_PIM_NPORTS)
     {
-      llinfo("  Illegal PIM port index: %d\n", portndx);
+      gpioinfo("  Illegal PIM port index: %d\n", portndx);
       return;
     }
 
   ptr = &piminfo[portndx];
-  llinfo(" PIM Port%c:\n", ptr->name);
-  llinfo("   IO:%02x  INP:%02x DDR:%02x RDR:%02x\n",
-         getreg8(ptr->base+HCS12_PIM_IO_OFFSET),
-         getreg8(ptr->base+HCS12_PIM_INPUT_OFFSET),
-         getreg8(ptr->base+HCS12_PIM_DDR_OFFSET),
-         getreg8(ptr->base+HCS12_PIM_RDR_OFFSET));
+  gpioinfo(" PIM Port%c:\n", ptr->name);
+  gpioinfo("   IO:%02x  INP:%02x DDR:%02x RDR:%02x\n",
+           getreg8(ptr->base+HCS12_PIM_IO_OFFSET),
+           getreg8(ptr->base+HCS12_PIM_INPUT_OFFSET),
+           getreg8(ptr->base+HCS12_PIM_DDR_OFFSET),
+           getreg8(ptr->base+HCS12_PIM_RDR_OFFSET));
 
   switch (ptr->form)
     {
     case PIMPORT_FORM1:
-      llinfo("  PER:%02x  PS:%02x\n",
-             getreg8(ptr->base+HCS12_PIM_PER_OFFSET),
-             getreg8(ptr->base+HCS12_PIM_PS_OFFSET));
+      gpioinfo("  PER:%02x  PS:%02x\n",
+               getreg8(ptr->base+HCS12_PIM_PER_OFFSET),
+               getreg8(ptr->base+HCS12_PIM_PS_OFFSET));
       break;
 
     case PIMPORT_FORM2:
-      llinfo("  PER:%02x  PS:%02x WOM:%02x\n",
-             getreg8(ptr->base+HCS12_PIM_PER_OFFSET),
-             getreg8(ptr->base+HCS12_PIM_PS_OFFSET),
-             getreg8(ptr->base+HCS12_PIM_WOM_OFFSET));
+      gpioinfo("  PER:%02x  PS:%02x WOM:%02x\n",
+               getreg8(ptr->base+HCS12_PIM_PER_OFFSET),
+               getreg8(ptr->base+HCS12_PIM_PS_OFFSET),
+               getreg8(ptr->base+HCS12_PIM_WOM_OFFSET));
       break;
 
     case PIMPORT_FORM3:
-      llinfo("  PER:%02x  PS:%02x  IE:%02x  IF:%02x\n",
-             getreg8(ptr->base+HCS12_PIM_PER_OFFSET),
-             getreg8(ptr->base+HCS12_PIM_PS_OFFSET),
-             getreg8(ptr->base+HCS12_PIM_IE_OFFSET),
-             getreg8(ptr->base+HCS12_PIM_IF_OFFSET));
+      gpioinfo("  PER:%02x  PS:%02x  IE:%02x  IF:%02x\n",
+               getreg8(ptr->base+HCS12_PIM_PER_OFFSET),
+               getreg8(ptr->base+HCS12_PIM_PS_OFFSET),
+               getreg8(ptr->base+HCS12_PIM_IE_OFFSET),
+               getreg8(ptr->base+HCS12_PIM_IF_OFFSET));
       break;
 
     default:
@@ -226,30 +226,30 @@ static inline void hcs12_mebidump(uint8_t portndx)
 
   if (portndx >= HCS12_MEBI_NPORTS)
     {
-      llinfo("  Illegal MEBI port index: %d\n", portndx);
+      gpioinfo("  Illegal MEBI port index: %d\n", portndx);
       return;
     }
 
   ptr = &mebiinfo[portndx];
-  llinfo(" MEBI Port%c:\n", ptr->name);
+  gpioinfo(" MEBI Port%c:\n", ptr->name);
 
   switch (ptr->form)
     {
     case MEBIPORT_AB:
-      llinfo("   DATA:%02x DDR:%02x\n",
-            getreg8(ptr->data), getreg8(ptr->ddr));
+      gpioinfo("   DATA:%02x DDR:%02x\n",
+              getreg8(ptr->data), getreg8(ptr->ddr));
       break;
 
     case MEBIPORT_E:
-      llinfo("   DATA:%02x DDR:%02x MODE:%02x PEAR:%02x\n",
-             getreg8(ptr->data), getreg8(ptr->ddr),
-             getreg8(HCS12_MEBI_MODE), getreg8(HCS12_MEBI_PEAR));
+      gpioinfo("   DATA:%02x DDR:%02x MODE:%02x PEAR:%02x\n",
+               getreg8(ptr->data), getreg8(ptr->ddr),
+               getreg8(HCS12_MEBI_MODE), getreg8(HCS12_MEBI_PEAR));
       break;
 
     case MEBIPORT_K:
-      llinfo("   DATA:%02x DDR:%02x MODE:%02x\n",
-             getreg8(ptr->data), getreg8(ptr->ddr),
-             getreg8(HCS12_MEBI_MODE));
+      gpioinfo("   DATA:%02x DDR:%02x MODE:%02x\n",
+               getreg8(ptr->data), getreg8(ptr->ddr),
+               getreg8(HCS12_MEBI_MODE));
       break;
 
     default:
@@ -274,7 +274,7 @@ int hcs12_dumpgpio(uint16_t pinset, const char *msg)
   uint8_t portndx = HCS12_PORTNDX(pinset);
   irqstate_t flags = enter_critical_section();
 
-  llinfo("pinset: %08x -- %s\n", pinset, msg);
+  gpioinfo("pinset: %08x -- %s\n", pinset, msg);
 
   if (HCS12_PIMPORT(pinset))
     {
@@ -289,4 +289,4 @@ int hcs12_dumpgpio(uint16_t pinset, const char *msg)
   return OK;
 }
 
-#endif /* CONFIG_DEBUG_GPIO */
+#endif /* CONFIG_DEBUG_GPIO_INFO */
diff --git a/arch/mips/src/pic32mx/pic32mx-gpio.c b/arch/mips/src/pic32mx/pic32mx-gpio.c
index 61ecde9e8c..a672cb35e0 100644
--- a/arch/mips/src/pic32mx/pic32mx-gpio.c
+++ b/arch/mips/src/pic32mx/pic32mx-gpio.c
@@ -303,7 +303,7 @@ bool pic32mx_gpioread(uint16_t pinset)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DEBUG_FEATURES) && defined(CONFIG_DEBUG_INFO) && defined(CONFIG_DEBUG_GPIO)
+#ifdef CONFIG_DEBUG_GPIO_INFO
 void pic32mx_dumpgpio(uint32_t pinset, const char *msg)
 {
   unsigned int port = pic32mx_portno(pinset);
@@ -321,17 +321,17 @@ void pic32mx_dumpgpio(uint32_t pinset, const char *msg)
       /* The following requires exclusive access to the GPIO registers */
 
       sched_lock();
-      llinfo("IOPORT%c pinset: %04x base: %08x -- %s\n",
-             'A'+port, pinset, base, msg);
-      llinfo("   TRIS: %08x   PORT: %08x    LAT: %08x    ODC: %08x\n",
-             getreg32(base + PIC32MX_IOPORT_TRIS_OFFSET),
-             getreg32(base + PIC32MX_IOPORT_PORT_OFFSET),
-             getreg32(base + PIC32MX_IOPORT_LAT_OFFSET),
-             getreg32(base + PIC32MX_IOPORT_ODC_OFFSET));
-      llinfo("  CNCON: %08x   CNEN: %08x  CNPUE: %08x\n",
-             getreg32(PIC32MX_IOPORT_CNCON),
-             getreg32(PIC32MX_IOPORT_CNEN),
-             getreg32(PIC32MX_IOPORT_CNPUE));
+      gpioinfo("IOPORT%c pinset: %04x base: %08x -- %s\n",
+               'A'+port, pinset, base, msg);
+      gpioinfo("   TRIS: %08x   PORT: %08x    LAT: %08x    ODC: %08x\n",
+               getreg32(base + PIC32MX_IOPORT_TRIS_OFFSET),
+               getreg32(base + PIC32MX_IOPORT_PORT_OFFSET),
+               getreg32(base + PIC32MX_IOPORT_LAT_OFFSET),
+               getreg32(base + PIC32MX_IOPORT_ODC_OFFSET));
+      gpioinfo("  CNCON: %08x   CNEN: %08x  CNPUE: %08x\n",
+               getreg32(PIC32MX_IOPORT_CNCON),
+               getreg32(PIC32MX_IOPORT_CNEN),
+               getreg32(PIC32MX_IOPORT_CNPUE));
       sched_unlock();
     }
 }
diff --git a/arch/mips/src/pic32mx/pic32mx.h b/arch/mips/src/pic32mx/pic32mx.h
index d636293703..c2dccffab9 100644
--- a/arch/mips/src/pic32mx/pic32mx.h
+++ b/arch/mips/src/pic32mx/pic32mx.h
@@ -378,7 +378,7 @@ void pic32mx_gpioirqdisable(unsigned int cn);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 void pic32mx_dumpgpio(uint32_t pinset, const char *msg);
 #else
 #  define pic32mx_dumpgpio(p,m)
diff --git a/arch/mips/src/pic32mz/pic32mz-gpio.c b/arch/mips/src/pic32mz/pic32mz-gpio.c
index e4123eb0ce..3d247edc5b 100644
--- a/arch/mips/src/pic32mz/pic32mz-gpio.c
+++ b/arch/mips/src/pic32mz/pic32mz-gpio.c
@@ -307,7 +307,7 @@ bool pic32mz_gpioread(pinset_t pinset)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_DEBUG_INFO) && defined(CONFIG_DEBUG_GPIO)
+#ifdef CONFIG_DEBUG_GPIO_INFO
 void pic32mz_dumpgpio(uint32_t pinset, const char *msg)
 {
   unsigned int port = pic32mz_portno(pinset);
@@ -325,17 +325,17 @@ void pic32mz_dumpgpio(uint32_t pinset, const char *msg)
       /* The following requires exclusive access to the GPIO registers */
 
       sched_lock();
-      llinfo("IOPORT%c pinset: %04x base: %08x -- %s\n",
-             'A'+port, pinset, base, msg);
-      llinfo("   TRIS: %08x   PORT: %08x    LAT: %08x    ODC: %08x\n",
-             getreg32(base + PIC32MZ_IOPORT_TRIS_OFFSET),
-             getreg32(base + PIC32MZ_IOPORT_PORT_OFFSET),
-             getreg32(base + PIC32MZ_IOPORT_LAT_OFFSET),
-             getreg32(base + PIC32MZ_IOPORT_ODC_OFFSET));
-      llinfo("  CNCON: %08x   CNEN: %08x  CNPUE: %08x\n",
-             getreg32(PIC32MZ_IOPORT_CNCON),
-             getreg32(PIC32MZ_IOPORT_CNEN),
-             getreg32(PIC32MZ_IOPORT_CNPUE));
+      gpioinfo("IOPORT%c pinset: %04x base: %08x -- %s\n",
+               'A'+port, pinset, base, msg);
+      gpioinfo("   TRIS: %08x   PORT: %08x    LAT: %08x    ODC: %08x\n",
+               getreg32(base + PIC32MZ_IOPORT_TRIS_OFFSET),
+               getreg32(base + PIC32MZ_IOPORT_PORT_OFFSET),
+               getreg32(base + PIC32MZ_IOPORT_LAT_OFFSET),
+               getreg32(base + PIC32MZ_IOPORT_ODC_OFFSET));
+      gpioinfo("  CNCON: %08x   CNEN: %08x  CNPUE: %08x\n",
+               getreg32(PIC32MZ_IOPORT_CNCON),
+               getreg32(PIC32MZ_IOPORT_CNEN),
+               getreg32(PIC32MZ_IOPORT_CNPUE));
       sched_unlock();
     }
 }
diff --git a/arch/mips/src/pic32mz/pic32mz-gpio.h b/arch/mips/src/pic32mz/pic32mz-gpio.h
index f7464a59d4..d2c6389a99 100644
--- a/arch/mips/src/pic32mz/pic32mz-gpio.h
+++ b/arch/mips/src/pic32mz/pic32mz-gpio.h
@@ -253,7 +253,7 @@ void pic32mz_gpioirqdisable(pinset_t pinset);
  *
  ************************************************************************************/
 
-#if defined(CONFIG_DEBUG_INFO) && defined(CONFIG_DEBUG_GPIO)
+#ifdef CONFIG_DEBUG_GPIO_INFO
 void pic32mz_dumpgpio(uint32_t pinset, const char *msg);
 #else
 #  define pic32mz_dumpgpio(p,m)
diff --git a/arch/x86/src/qemu/qemu.h b/arch/x86/src/qemu/qemu.h
index 6148180aa9..85ea4bde35 100644
--- a/arch/x86/src/qemu/qemu.h
+++ b/arch/x86/src/qemu/qemu.h
@@ -187,7 +187,7 @@ void i486_gpioirqdisable(int irq);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_DEBUG_GPIO
+#ifdef CONFIG_DEBUG_GPIO_INFO
 int i486_dumpgpio(uint16_t pinset, const char *msg);
 #else
 #  define i486_dumpgpio(p,m)
diff --git a/include/debug.h b/include/debug.h
index e96fcbeb0d..707a78c2d5 100644
--- a/include/debug.h
+++ b/include/debug.h
@@ -550,11 +550,11 @@
 #endif
 
 #ifdef CONFIG_DEBUG_IRQ_ERROR
-#  define dmaerr(format, ...)    err(format, ##__VA_ARGS__)
-#  define dmallerr(format, ...)  llerr(format, ##__VA_ARGS__)
+#  define irqerr(format, ...)    err(format, ##__VA_ARGS__)
+#  define irqllerr(format, ...)  llerr(format, ##__VA_ARGS__)
 #else
-#  define dmaerr(x...)
-#  define dmallerr(x...)
+#  define irqerr(x...)
+#  define irqllerr(x...)
 #endif
 
 #ifdef CONFIG_DEBUG_IRQ_WARN
@@ -573,6 +573,30 @@
 #  define irqllinfo(x...)
 #endif
 
+#ifdef CONFIG_DEBUG_GPIO_ERROR
+#  define gpioerr(format, ...)   err(format, ##__VA_ARGS__)
+#  define gpiollerr(format, ...) llerr(format, ##__VA_ARGS__)
+#else
+#  define gpioerr(x...)
+#  define gpiollerr(x...)
+#endif
+
+#ifdef CONFIG_DEBUG_GPIO_WARN
+#  define gpiowarn(format, ...)   warn(format, ##__VA_ARGS__)
+#  define gpiollwarn(format, ...) llwarn(format, ##__VA_ARGS__)
+#else
+#  define gpiowarn(x...)
+#  define gpiollwarn(x...)
+#endif
+
+#ifdef CONFIG_DEBUG_GPIO_INFO
+#  define gpioinfo(format, ...)   info(format, ##__VA_ARGS__)
+#  define gpiollinfo(format, ...) llinfo(format, ##__VA_ARGS__)
+#else
+#  define gpioinfo(x...)
+#  define gpiollinfo(x...)
+#endif
+
 #else /* CONFIG_CPP_HAVE_VARARGS */
 
 /* Variadic macros NOT supported */
@@ -994,6 +1018,30 @@
 #  define irqllinfo   (void)
 #endif
 
+#ifdef CONFIG_DEBUG_GPIO_ERROR
+#  define gpioerr     err
+#  define gpiollerr   llerr
+#else
+#  define gpioerr     (void)
+#  define gpiollerr   (void)
+#endif
+
+#ifdef CONFIG_DEBUG_GPIO_WARN
+#  define gpiowarn    warn
+#  define gpiollwarn  llwarn
+#else
+#  define gpiowarn    (void)
+#  define gpiollwarn  (void)
+#endif
+
+#ifdef CONFIG_DEBUG_GPIO_INFO
+#  define gpioinfo    info
+#  define gpiollinfo  llinfo
+#else
+#  define gpioinfo    (void)
+#  define gpiollinfo  (void)
+#endif
+
 #endif /* CONFIG_CPP_HAVE_VARARGS */
 
 /* Buffer dumping macros do not depend on varargs */
@@ -1036,14 +1084,6 @@
 #  define pginfodumpbuffer(m,b,n)
 #endif
 
-#ifdef CONFIG_DEBUG_DMA
-#  define dmaerrdumpbuffer(m,b,n)  errdumpbuffer(m,b,n)
-#  define dmainfodumpbuffer(m,b,n) infodumpbuffer(m,b,n)
-#else
-#  define dmaerrdumpbuffer(m,b,n)
-#  define dmainfodumpbuffer(m,b,n)
-#endif
-
 #ifdef CONFIG_DEBUG_NET
 #  define nerrdumpbuffer(m,b,n)  errdumpbuffer(m,b,n)
 #  define ninfodumpbuffer(m,b,n) infodumpbuffer(m,b,n)
@@ -1108,6 +1148,30 @@
 #  define audinfodumpbuffer(m,b,n)
 #endif
 
+#ifdef CONFIG_DEBUG_DMA
+#  define dmaerrdumpbuffer(m,b,n)  errdumpbuffer(m,b,n)
+#  define dmainfodumpbuffer(m,b,n) infodumpbuffer(m,b,n)
+#else
+#  define dmaerrdumpbuffer(m,b,n)
+#  define dmainfodumpbuffer(m,b,n)
+#endif
+
+#ifdef CONFIG_DEBUG_IRQ
+#  define irqerrdumpbuffer(m,b,n)  errdumpbuffer(m,b,n)
+#  define irqinfodumpbuffer(m,b,n) infodumpbuffer(m,b,n)
+#else
+#  define irqerrdumpbuffer(m,b,n)
+#  define irqinfodumpbuffer(m,b,n)
+#endif
+
+#ifdef CONFIG_DEBUG_GPIO
+#  define gpioerrdumpbuffer(m,b,n)  errdumpbuffer(m,b,n)
+#  define gpioinfodumpbuffer(m,b,n) infodumpbuffer(m,b,n)
+#else
+#  define gpioerrdumpbuffer(m,b,n)
+#  define gpioinfodumpbuffer(m,b,n)
+#endif
+
 /****************************************************************************
  * Public Type Declarations
  ****************************************************************************/