Add STM32F0 USB device header file; Update TODO list.
This commit is contained in:
Gregory Nutt
parent
547f6c7cc3
commit
a98cdc7a45
24
TODO
24
TODO
@ -14,7 +14,7 @@ nuttx/:
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(1) Memory Management (mm/)
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(0) Power Management (drivers/pm)
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(3) Signals (sched/signal, arch/)
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(4) pthreads (sched/pthread)
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(3) pthreads (sched/pthread)
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(0) Message Queues (sched/mqueue)
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(8) Kernel/Protected Build
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(3) C++ Support
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@ -47,8 +47,8 @@ o Task/Scheduler (sched/)
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Priority: Medium, required for good emulation of process/pthread model.
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Title: pause() NON-COMPLIANCE
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Description: In the POSIX description of this function is the pause() function
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will suspend the calling thread until delivery of a signal whose
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Description: In the POSIX description of this function the pause() function
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must suspend the calling thread until delivery of a signal whose
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action is either to execute a signal-catching function or to
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terminate the process. The current implementation only waits for
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any non-blocked signal to be received. It should only wake up if
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@ -500,20 +500,6 @@ o pthreads (sched/pthreads)
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Priority: Medium-low. Priority may be higher if system call overheade becomes
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an issue.
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Title: ROBUST MUTEX ATTRIBUTE NOT SUPPORTED
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Description: In NuttX, all mutexes are 'robust' in the sense that an attmpt
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to lock a mutex will return EOWNDERDEAD if the holder of the
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mutex has died. Unlocking of a mutex will fail if the caller
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is not the holder of the mutex.
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POSIX, however, requires that there be a mutex attribute called
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robust that determines which behavior is supported. non-robust
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should be the default. NuttX does not support this attribute
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and robust behavior is the default and only supported behavior.
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Status: Open
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Priority: Low. The non-robust behavior is dangerous and really should never
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be used.
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o Message Queues (sched/mqueue)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -1092,7 +1078,8 @@ o Network (net/, drivers/net)
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Title: ETHERNET WITH MULTIPLE LPWORK THREADS
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Description: Recently, Ethernet drivers were modified to support multiple
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work queue structures. The question was raised: "My only
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reservation would be, how would this interact in the case of having CONFIG_STM32_ETHMAC_LPWORK and CONFIG_SCHED_LPNTHREADS
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reservation would be, how would this interact in the case of
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having CONFIG_STM32_ETHMAC_LPWORK and CONFIG_SCHED_LPNTHREADS
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> 1? Can it be guaranteed that one work item won't be
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interrupted and execution switched to another? I think so but
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am not 100% confident."
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@ -2124,4 +2111,3 @@ o Other Applications & Tests (apps/examples/)
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the artifact is larger.
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Status: Open
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Priority: Medium.
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@ -3,7 +3,6 @@
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Alan Carvalho de Assis <acassis@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -44,6 +43,9 @@
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#include <nuttx/config.h>
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#include <chip.h>
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#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) \
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|| defined(CONFIG_STM32_STM32F37XX)
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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@ -52,70 +54,72 @@
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/* Endpoint Registers */
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#define STM32F0_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */
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#define STM32F0_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */
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#define STM32F0_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */
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#define STM32F0_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */
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#define STM32F0_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */
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#define STM32F0_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */
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#define STM32F0_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */
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#define STM32F0_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */
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#define STM32F0_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */
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#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */
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#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */
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#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */
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#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */
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#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */
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#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */
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#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */
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#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */
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#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */
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/* Common Registers */
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#define STM32F0_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */
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#define STM32F0_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */
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#define STM32F0_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */
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#define STM32F0_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */
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#define STM32F0_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */
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#define STM32F0_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */
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#define STM32F0_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */
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#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */
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#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */
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#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */
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#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */
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#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */
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#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register (16-bits) */
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#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector (16-bits) */
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/* Buffer Descriptor Table (Relatative to BTABLE address) */
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#define STM32F0_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */
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#define STM32F0_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */
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#define STM32F0_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */
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#define STM32F0_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */
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#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */
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#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */
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#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */
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#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */
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#define STM32F0_USB_BTABLE_RADDR(ep,o) ((((uint32_t)getreg16(STM32F0_USB_BTABLE) + ((ep) << 3)) + (o)) << 1)
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#define STM32F0_USB_ADDR_TX_OFFSET(ep) STM32F0_USB_BTABLE_RADDR(ep,STM32F0_USB_ADDR_TX_WOFFSET)
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#define STM32F0_USB_COUNT_TX_OFFSET(ep) STM32F0_USB_BTABLE_RADDR(ep,STM32F0_USB_COUNT_TX_WOFFSET)
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#define STM32F0_USB_ADDR_RX_OFFSET(ep) STM32F0_USB_BTABLE_RADDR(ep,STM32F0_USB_ADDR_RX_WOFFSET)
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#define STM32F0_USB_COUNT_RX_OFFSET(ep) STM32F0_USB_BTABLE_RADDR(ep,STM32F0_USB_COUNT_RX_WOFFSET)
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#define STM32_USB_BTABLE_RADDR(ep,o) ((((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) << 1)
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#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET)
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#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET)
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#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET)
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#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET)
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/* Register Addresses ***************************************************************/
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/* Endpoint Registers */
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#define STM32F0_USB_EPR(n) (STM32F0_USB_BASE+STM32F0_USB_EPR_OFFSET(n))
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#define STM32F0_USB_EP0R (STM32F0_USB_BASE+STM32F0_USB_EP0R_OFFSET)
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#define STM32F0_USB_EP1R (STM32F0_USB_BASE+STM32F0_USB_EP1R_OFFSET)
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#define STM32F0_USB_EP2R (STM32F0_USB_BASE+STM32F0_USB_EP2R_OFFSET)
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#define STM32F0_USB_EP3R (STM32F0_USB_BASE+STM32F0_USB_EP3R_OFFSET)
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#define STM32F0_USB_EP4R (STM32F0_USB_BASE+STM32F0_USB_EP4R_OFFSET)
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#define STM32F0_USB_EP5R (STM32F0_USB_BASE+STM32F0_USB_EP5R_OFFSET)
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#define STM32F0_USB_EP6R (STM32F0_USB_BASE+STM32F0_USB_EP6R_OFFSET)
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#define STM32F0_USB_EP7R (STM32F0_USB_BASE+STM32F0_USB_EP7R_OFFSET)
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#define STM32_USB_EPR(n) (STM32_USB_BASE+STM32_USB_EPR_OFFSET(n))
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#define STM32_USB_EP0R (STM32_USB_BASE+STM32_USB_EP0R_OFFSET)
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#define STM32_USB_EP1R (STM32_USB_BASE+STM32_USB_EP1R_OFFSET)
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#define STM32_USB_EP2R (STM32_USB_BASE+STM32_USB_EP2R_OFFSET)
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#define STM32_USB_EP3R (STM32_USB_BASE+STM32_USB_EP3R_OFFSET)
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#define STM32_USB_EP4R (STM32_USB_BASE+STM32_USB_EP4R_OFFSET)
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#define STM32_USB_EP5R (STM32_USB_BASE+STM32_USB_EP5R_OFFSET)
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#define STM32_USB_EP6R (STM32_USB_BASE+STM32_USB_EP6R_OFFSET)
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#define STM32_USB_EP7R (STM32_USB_BASE+STM32_USB_EP7R_OFFSET)
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/* Common Registers */
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#define STM32F0_USB_CNTR (STM32F0_USB_BASE+STM32F0_USB_CNTR_OFFSET)
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#define STM32F0_USB_ISTR (STM32F0_USB_BASE+STM32F0_USB_ISTR_OFFSET)
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#define STM32F0_USB_FNR (STM32F0_USB_BASE+STM32F0_USB_FNR_OFFSET)
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#define STM32F0_USB_DADDR (STM32F0_USB_BASE+STM32F0_USB_DADDR_OFFSET)
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#define STM32F0_USB_BTABLE (STM32F0_USB_BASE+STM32F0_USB_BTABLE_OFFSET)
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#define STM32F0_USB_LPMCSR_OFFSET (STM32F0_USB_BASE+STM32F0_USB_LPMCSR_OFFSET)
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#define STM32F0_USB_BCDR_OFFSET (STM32F0_USB_BASE+STM32F0_USB_BCDR_OFFSET)
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#define STM32_USB_CNTR (STM32_USB_BASE+STM32_USB_CNTR_OFFSET)
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#define STM32_USB_ISTR (STM32_USB_BASE+STM32_USB_ISTR_OFFSET)
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#define STM32_USB_FNR (STM32_USB_BASE+STM32_USB_FNR_OFFSET)
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#define STM32_USB_DADDR (STM32_USB_BASE+STM32_USB_DADDR_OFFSET)
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#define STM32_USB_BTABLE (STM32_USB_BASE+STM32_USB_BTABLE_OFFSET)
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#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register (16-bits) */
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#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register (16-bits) */
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#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector (16-bits) */
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#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector (16-bits) */
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/* Buffer Descriptor Table (Relatative to BTABLE address) */
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#define STM32F0_USB_BTABLE_ADDR(ep,o) (STM32F0_USBRAM_BASE+STM32F0_USB_BTABLE_RADDR(ep,o))
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#define STM32F0_USB_ADDR_TX(ep) STM32F0_USB_BTABLE_ADDR(ep,STM32F0_USB_ADDR_TX_WOFFSET)
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#define STM32F0_USB_COUNT_TX(ep) STM32F0_USB_BTABLE_ADDR(ep,STM32F0_USB_COUNT_TX_WOFFSET)
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#define STM32F0_USB_ADDR_RX(ep) STM32F0_USB_BTABLE_ADDR(ep,STM32F0_USB_ADDR_RX_WOFFSET)
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#define STM32F0_USB_COUNT_RX(ep) STM32F0_USB_BTABLE_ADDR(ep,STM32F0_USB_COUNT_RX_WOFFSET)
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#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USBRAM_BASE+STM32_USB_BTABLE_RADDR(ep,o))
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#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET)
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#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET)
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#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET)
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#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET)
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/* Register Bitfield Definitions ****************************************************/
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@ -160,27 +164,28 @@
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#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */
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#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */
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#define USB_CNTR_L1RESUME (1 << 5) /* Bit 5: LPM L1 Resume request */
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#define USB_CNTR_L1REQM (1 << 7) /* Bit 6: LPM L1 state request interrupt mask */
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#define USB_CNTR_L1REQ (1 << 7) /* Bit 7: LPM L1 state request interrupt mask */
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#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected Start Of Frame Interrupt Mask */
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#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start Of Frame Interrupt Mask */
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#define USB_CNTR_RESETM (1 << 10) /* Bit 10: USB Reset Interrupt Mask */
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#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend mode Interrupt Mask */
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#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wakeup Interrupt Mask */
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#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error Interrupt Mask */
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#define USB_CNTR_PMAOVRNM (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */
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#define USB_CNTR_PMAOVRM (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */
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#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */
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#define USB_CNTR_ALLINTS (USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|USB_CNTR_SUSPM|\
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USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_DMAOVRNM|USB_CNTR_CTRM)
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#define USB_CNTR_ALLINTS (USB_CNTR_L1REQ|USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|\
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USB_CNTR_SUSPM|USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_PMAOVRNM|\
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USB_CNTR_CTRM)
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/* USB interrupt status register */
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#define USB_ISTR_EPID_SHIFT (0) /* Bits 3-0: Endpoint Identifier */
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#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT)
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#define USB_ISTR_DIR (1 << 4) /* Bit 4: Direction of transaction */
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#define USB_ISTR_L1REQ (1 << 7) /* Bit 7: LPM L1 state request */
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#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected Start Of Frame */
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#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start Of Frame */
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#define USB_ISTR_DIR (1 << 4) /* Bit 4: Direction of transaction */
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#define USB_ISTR_L1REQ (1 << 7) /* Bit 7: LPM L1 state request */
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#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected Start Of Frame */
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#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start Of Frame */
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#define USB_ISTR_RESET (1 << 10) /* Bit 10: USB RESET request */
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#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend mode request */
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#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wake up */
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@ -188,8 +193,9 @@
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#define USB_ISTR_PMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */
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#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */
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#define USB_ISTR_ALLINTS (USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|USB_ISTR_SUSP|\
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USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_DMAOVRN|USB_ISTR_CTR)
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#define USB_ISTR_ALLINTS (USB_ISTR_L1REQ|USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|\
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USB_ISTR_SUSP|USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_PMAOVRN|\
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USB_ISTR_CTR)
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/* USB frame number register */
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@ -212,24 +218,24 @@
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#define USB_BTABLE_SHIFT (3) /* Bits 15:3: Buffer Table */
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#define USB_BTABLE_MASK (0x1fff << USB_BTABLE_SHIFT)
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/* LPM control and status register */
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/* LPM control and status register (16-bits) */
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#define USB_LPMCSR_LPMEN (1 << 0) /* Bit 0: LPM support enable */
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#define USB_LPMCSR_LPMACK (1 << 1) /* Bit 1: LPM Token acknowledge enable */
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#define USB_LPMCSR_REMWAKE (1 << 3) /* Bit 3: bRemoteWake value */
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#define USB_LPMCSR_BESL_OFFSET (4) /* Bits 4-7: BESL value */
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#define USB_LPMCSR_BESL_MASK (0xf << USB_LPMCSR_BESL_OFFSET)
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#define USB_LPMCSR_LPMEN (1 << 0) /* Bit 0: LPM support enable */
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#define USB_LPMCSR_LPMACK (1 << 1) /* Bit 1: LPM Token acknowledge enable */
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#define USB_LPMCSR_REMWAKE (1 << 3) /* Bit 3: bRemoteWake value */
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#define USB_LPMCSR_BESL_SHIFT (4) /* Bits 4-7: BESL value */
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#define USB_LPMCSR_BESL_MASK (15 << USB_LPMCSR_BESL_SHIFT)
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/* Battery charging detector */
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/* Battery charging detector (16-bits) */
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#define USB_BCDR_BCDEN (1 << 0) /* Bit 0: Battery charging detector (BCD) enable */
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#define USB_BCDR_DCDEN (1 << 1) /* Bit 1: Data contact detection (DCD) mode enable */
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#define USB_BCDR_PDEN (1 << 2) /* Bit 2: Primary detection (PD) mode enable */
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#define USB_BCDR_SDEN (1 << 3) /* Bit 3: Secondary detection (SD) mode enable */
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#define USB_BCDR_DCDET (1 << 4) /* Bit 4: Data contact detection (DCD) status */
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#define USB_BCDR_PDET (1 << 5) /* Bit 5: Primary detection (PD) status */
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#define USB_BCDR_SDET (1 << 6) /* Bit 6: Secondary detection (SD) status */
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#define USB_BCDR_PS2DET (1 << 7) /* Bit 7: DM pull-up detection status */
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#define USB_BCDR_BCDEN (1 << 0) /* Bit 0: Battery charging detector (BCD) enable */
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#define USB_BCDR_DCDEN (1 << 1) /* Bit 1: Data contact detection (DCD) mode enable */
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#define USB_BCDR_PDEN (1 << 2) /* Bit 2: Primary detection (PD) mode enable */
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#define USB_BCDR_SDEN (1 << 3) /* Bit 3: Secondary detection (SD) mode enable */
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#define USB_BCDR_DCDET (1 << 4) /* Bit 4: Data contact detection (DCD) status */
|
||||
#define USB_BCDR_PDET (1 << 5) /* Bit 5: Primary detection (PD) status */
|
||||
#define USB_BCDR_SDET (1 << 6) /* Bit 6: Secondary detection (SD) status */
|
||||
#define USB_BCDR_PS2DET (1 << 7) /* Bit 7: DM pull-up detection status */
|
||||
#define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */
|
||||
|
||||
/* Transmission buffer address */
|
||||
@ -240,11 +246,8 @@
|
||||
|
||||
/* Transmission byte count */
|
||||
|
||||
#define USB_COUNT_TX_SHIFT (0) /* Bits 0-9: Transmission Byte Count */
|
||||
#define USB_COUNT_TX_SHIFT (0) /* Bits 9-0: Transmission Byte Count */
|
||||
#define USB_COUNT_TX_MASK (0x03ff << USB_COUNT_COUNT_TX_SHIFT)
|
||||
#define USB_COUNT_NUMBLOCK_OFFSET (10) /* Bits 10-14: Number of blocks */
|
||||
#define USB_COUNT_NUMBLOCK_MASK (1 << USB_COUNT_NUMBLOCK_OFFSET)
|
||||
#define USB_COUNT_BLSIZE (1 << 15) /* Bit 15: Block size */
|
||||
|
||||
/* Reception buffer address */
|
||||
|
||||
@ -260,4 +263,5 @@
|
||||
#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */
|
||||
#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT)
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F37XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F0_USBDEV_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user