Xtensa: Add interrupt enable/disable controls. Add dummy timer and IRQ initialization.

arch/xtensa/include/irq.h

@@ -46,9 +46,12 @@
 
 /* Include NuttX-specific IRQ definitions */
 
+#include <nuttx/config.h>
 #include <nuttx/irq.h>
 #include <arch/types.h>
 #include <arch/chip/core-isa.h>
+#include <arch/xtensa/specregs.h>
+#include <arch/xtensa/corebits.h>
 
 /* Include architecture-specific IRQ definitions */
 
@@ -168,6 +171,69 @@ struct xcptcontext
  * Inline functions
  ****************************************************************************/
 
+/* Return the current value of the PS register */
+
+static inline uint32_t xtensa_getps(void)
+{
+  uint32_t ps;
+
+  __asm__ __volatile__
+  (
+    "rsr %0, PS"  : "=r"(ps)
+  );
+
+  return ps;
+}
+
+/* Set the value of the PS register */
+
+static inline void xtensa_setps(uint32_t ps)
+{
+  __asm__ __volatile__
+  (
+    "wsr %0, PS"  : : "=r"(ps)
+  );
+}
+
+/* Restore the value of the PS register */
+
+static inline void up_irq_restore(uint32_t ps)
+{
+  __asm__ __volatile__
+  (
+    "wsr %0, PS"  : : "=r"(ps)
+  );
+}
+
+/* Disable interrupts and return the previous value of the PS register */
+
+static inline uint32_t up_irq_save(void)
+{
+  /* Get the current value of the PS for return */
+
+  uint32_t ps = xtensa_getps();
+
+  /* Disable all low- and medium-priority interrupts.  High priority
+   * interrupts should not interfere with ongoing RTOS operations and
+   * are not disabled.
+   *
+   * NOTE: We also assume that since we were called from C logic, the
+   * EXCM must already be cleared.
+   */
+
+#ifdef CONFIG_XTENSA_CALL0_ABI
+  xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM);
+#else
+  xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE);
+#endif
+
+  /* Return the previous PS value so that it can be restored with
+   * up_irq_restore().
+   */
+
+  return ps;
+}
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/

arch/xtensa/include/xtensa/xtensa_corebits.h

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/xtensa/src/common/xtensa_corebits.h
+ * arch/xtensa/include/xtensa/xtensa_corebits.h
  * Xtensa Special Register field positions, masks, values.
  * NOTE: This file may be processor configuration dependent.
  *
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_EXTENSA_SRC_COMMON_XTENSA_COREBITS_H
-#define __ARCH_EXTENSA_SRC_COMMON_XTENSA_COREBITS_H
+#ifndef __ARCH_EXTENSA_INCLUDE_XTENSA_XTENSA_COREBITS_H
+#define __ARCH_EXTENSA_INCLUDE_XTENSA_XTENSA_COREBITS_H
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -203,4 +203,4 @@
 #define MEMCTL_DCW_CLR_MASK        (MEMCTL_DCWU_CLR_MASK | MEMCTL_DCWA_CLR_MASK)
 #define MEMCTL_IDCW_CLR_MASK       (MEMCTL_DCW_CLR_MASK | MEMCTL_ICWU_CLR_MASK)
 
-#endif /*__ARCH_EXTENSA_SRC_COMMON_XTENSA_COREBITS_H*/
+#endif /*__ARCH_EXTENSA_INCLUDE_XTENSA_XTENSA_COREBITS_H*/

arch/xtensa/include/xtensa/xtensa_specregs.h

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/xtensa/src/common/xtensa_macros.h
+ * arch/xtensa/include/xtensa/xtensa_specregs.h
  * Xtensa Special Register symbolic names
  *
  * Adapted from use in NuttX by:
@@ -32,8 +32,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_SPECREGS_H
-#define __ARCH_XTENSA_SRC_COMMON_XTENSA_SPECREGS_H
+#ifndef __ARCH_XTENSA_INCLUDE_XTENSA_XTENSA_SPECREGS_H
+#define __ARCH_XTENSA_INCLUDE_XTENSA_XTENSA_SPECREGS_H
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -151,4 +151,4 @@
 #define CEND          247    /* VectraLX */
 #endif
 
-#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_SPECREGS_H */
+#endif /* __ARCH_XTENSA_INCLUDE_XTENSA_XTENSA_SPECREGS_H */

arch/xtensa/src/common/xtensa_context.S

@@ -60,10 +60,9 @@
 
 #include <nuttx/config.h>
 
-#include <arch/chip/core-isa.h>
 #include <arch/irq.h>
-
-#include "xtensa_specregs.h"
+#include <arch/chip/core-isa.h>
+#include <arch/xtensa/xtensa_specregs.h>
 
 #warning REVIST XTENSA_EXTRA_SA_SIZE is not yet provided
 #define XTENSA_EXTRA_SA_SIZE 0 /* REMOVE ME */

arch/xtensa/src/common/xtensa_initialstate.c

@@ -46,9 +46,9 @@
 #include <nuttx/arch.h>
 #include <arch/irq.h>
 #include <arch/chip/core-isa.h>
+#include <arch/xtensa/xtensa_corebits.h>
 
 #include "xtensa.h"
-#include "xtensa_corebits.h"
 
 /****************************************************************************
  * Public Functions

arch/xtensa/src/common/xtensa_inthandlers.S

@@ -59,10 +59,10 @@
 
 #include <nuttx/config.h>
 
-#include <arch/chip/core-isa.h>
 #include <arch/irq.h>
+#include <arch/chip/core-isa.h>
+#include <arch/xtensa/xtensa_specreg.h>
 
-#include "xtensa_specregs.h"
 #include "xtensa_macros.h"
 #include "xtensa_timer.h"
 

arch/xtensa/src/common/xtensa_intvectors.S

@@ -39,8 +39,8 @@
 #include <nuttx/config.h>
 
 #include <arch/chip/core-isa.h>
+#include <arch/xtensa/xtensa_specreg.h>
 
-#include "xtensa_specregs.h"
 #include "xtensa_macros.h"
 
 /****************************************************************************

arch/xtensa/src/common/xtensa_timer.h

@@ -37,7 +37,7 @@
 #include    <xtensa/coreasm.h>
 #endif
 
-#include    <xtensa/corebits.h>
+#include    <arch/xtensa/xtensa_corebits.h>
 #include    <xtensa/config/system.h>
 
 /* Select timer to use for periodic tick, and determine its interrupt number

arch/xtensa/src/esp32/Make.defs

@@ -75,7 +75,8 @@ endif
 # Required ESP32 files (arch/xtensa/src/lx6)
 
 CHIP_ASRCS  =
-CHIP_CSRCS  = esp32_allocateheap.c esp32_intdecode.c esp32_start.c
+CHIP_CSRCS  = esp32_allocateheap.c esp32_intdecode.c esp32_irq.c
+CHIP_CSRCS += esp32_start.c esp32_timerisr.c
 
 # Configuration-dependent ESP32 files
 

arch/xtensa/src/esp32/esp32_irq.c

@@ -0,0 +1,202 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32/esp32_irq.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+
+#include "xtensa.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure.  If is non-NULL only during interrupt
+ * processing.  Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+volatile uint32_t *g_current_regs[1];
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32_irq_dump
+ *
+ * Description:
+ *   Dump some interesting NVIC registers
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_DEBUG_IRQ_INFO)
+static void esp32_irq_dump(const char *msg, int irq)
+{
+  irqstate_t flags;
+
+  flags = enter_critical_section();
+#warning Missing logic
+  leave_critical_section(flags);
+}
+#else
+#  define esp32_irq_dump(msg, irq)
+#endif
+
+/****************************************************************************
+ * Name: esp32_nmi
+ *
+ * Description:
+ *   Handlers for various execptions.  None are handled and all are fatal
+ *   error conditions.  The only advantage these provided over the default
+ *   unexpected interrupt handler is that they provide a diagnostic output.
+ *
+ ****************************************************************************/
+
+static int esp32_nmi(int irq, FAR void *context)
+{
+  (void)up_irq_save();
+  _err("PANIC!!! NMI received\n");
+  PANIC();
+  return 0;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+  int i;
+
+  /* Disable all interrupts */
+#warning Missing logic
+
+#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
+  /* Colorize the interrupt stack for debug purposes */
+
+#warning Missing logic
+#endif
+
+  /* Set all interrupts (and exceptions) to the default priority */
+#warning Missing logic
+
+  /* Attach all other processor exceptions (except reset and sys tick) */
+#warning Missing logic
+
+  esp32_irq_dump("initial", NR_IRQS);
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+
+  /* And finally, enable interrupts */
+
+  up_irq_enable();
+#endif
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ *   Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+#warning Missing logic
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ *   Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+#warning Missing logic
+}
+
+/****************************************************************************
+ * Name: up_ack_irq
+ *
+ * Description:
+ *   Acknowledge the IRQ
+ *
+ ****************************************************************************/
+
+void up_ack_irq(int irq)
+{
+}
+
+/****************************************************************************
+ * Name: up_prioritize_irq
+ *
+ * Description:
+ *   Set the priority of an IRQ.
+ *
+ *   Since this API is not supported on all architectures, it should be
+ *   avoided in common implementations where possible.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_IRQPRIO
+int up_prioritize_irq(int irq, int priority)
+{
+#warning Missing logic
+  return OK;
+}
+#endif

arch/xtensa/src/esp32/esp32_timerisr.c

@@ -0,0 +1,107 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32/esp32_timerisr.c
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <time.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "clock/clock.h"
+#include "xtensa.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  esp32_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for various portions
+ *   of the systems.
+ *
+ ****************************************************************************/
+
+static int esp32_timerisr(int irq, uint32_t *regs)
+{
+  /* Process timer interrupt */
+
+  sched_process_timer();
+  return 0;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  up_timer_initialize
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ****************************************************************************/
+
+void up_timer_initialize(void)
+{
+  uint32_t regval;
+
+  /* Configured the timer0 as the system timer */
+#warning Missing logic
+
+  /* Attach the timer interrupt vector */
+
+  (void)irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32_timerisr);
+
+  /* Enable SysTick interrupts */
+#warning Missing logic
+
+  /* And enable the timer interrupt */
+
+  up_enable_irq(XTENSA_IRQ_TIMER0);
+}