diff --git a/arch/arm/src/xmc4/chip/xmc4_pinmux.h b/arch/arm/src/xmc4/chip/xmc4_pinmux.h
index b4ba4b0e24..daece1f509 100644
--- a/arch/arm/src/xmc4/chip/xmc4_pinmux.h
+++ b/arch/arm/src/xmc4/chip/xmc4_pinmux.h
@@ -748,8 +748,8 @@
 #define GPIO_U2C1_HWIN3          (GPIO_INPUT | GPIO_PINCTRL_HW0 | GPIO_PORT4 | GPIO_PIN4)
 #define GPIO_U2C1_MCLKOUT        (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN4)
 #define GPIO_U2C1_SCLKOUT_1      (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN13)
-#define GPIO_U2C1_SCLKOUT_1      (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN6)
-#define GPIO_U2C1_SCLKOUT_1      (GPIO_OUTPUT_ALT4 | GPIO_PORT4 | GPIO_PIN2)
+#define GPIO_U2C1_SCLKOUT_2      (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN6)
+#define GPIO_U2C1_SCLKOUT_3      (GPIO_OUTPUT_ALT4 | GPIO_PORT4 | GPIO_PIN2)
 #define GPIO_U2C1_SELO0_1        (GPIO_OUTPUT_ALT1 | GPIO_PORT3 | GPIO_PIN0)
 #define GPIO_U2C1_SELO0_2        (GPIO_OUTPUT_ALT1 | GPIO_PORT4 | GPIO_PIN1)
 #define GPIO_U2C1_SELO1          (GPIO_OUTPUT_ALT1 | GPIO_PORT4 | GPIO_PIN2)
diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h
index 0618e7e02b..49b74a3e48 100644
--- a/arch/arm/src/xmc4/chip/xmc4_scu.h
+++ b/arch/arm/src/xmc4/chip/xmc4_scu.h
@@ -990,7 +990,7 @@
 #define SCU_CGATSTAT2_DMA1          (1 << 5)  /* Bit 5:  DMA1 Gating Status */
 #define SCU_CGATSTAT2_FCE           (1 << 6)  /* Bit 6:  FCE Gating Status */
 #define SCU_CGATSTAT2_USB           (1 << 7)  /* Bit 7:  USB Gating Status */
-#define SCU_CGATSTAT2_USB           (1 << 10) /* Bit 10: ECAT Gating Status */
+#define SCU_CGATSTAT2_ECAT          (1 << 10) /* Bit 10: ECAT Gating Status */
 
 /* Peripheral 3 Clock Gating Status, Peripheral 3 Clock Gating Set, Peripheral 3 Clock Gating Clear */
 
diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h
index 0b49ebfff4..12d4bda2bc 100644
--- a/arch/arm/src/xmc4/chip/xmc4_usic.h
+++ b/arch/arm/src/xmc4/chip/xmc4_usic.h
@@ -433,9 +433,9 @@
 #  define USIC_FDR_STEP(n)          ((uint32_t)(n) << USIC_FDR_STEP_SHIFT)
 #define USIC_FDR_DM_SHIFT           (14)      /* Bits 14-15: Divider Mode */
 #define USIC_FDR_DM_MASK            (3 << USIC_FDR_DM_SHIFT)
-#  define USIC_FDR_DM_ OFF          (0 << USIC_FDR_DM_SHIFT) /* Divider switched off */
-#  define USIC_FDR_DM_ NORMAL       (1 << USIC_FDR_DM_SHIFT) /* Normal divider mode selected */
-#  define USIC_FDR_DM_ FRACTIONAL   (2 << USIC_FDR_DM_SHIFT) /* Fractional divider mode selected */
+#  define USIC_FDR_DM_OFF           (0 << USIC_FDR_DM_SHIFT) /* Divider switched off */
+#  define USIC_FDR_DM_NORMAL        (1 << USIC_FDR_DM_SHIFT) /* Normal divider mode selected */
+#  define USIC_FDR_DM_FRACTIONAL    (2 << USIC_FDR_DM_SHIFT) /* Fractional divider mode selected */
 #define USIC_FDR_RESULT_SHIFT       (16)      /* Bits 16-25: Result Value */
 #define USIC_FDR_RESULT_MASK        (0x3ff << USIC_FDR_RESULT_SHIFT)
 
@@ -550,7 +550,7 @@
 #define USIC_SCTR_HPCDIR            (1 << 4)  /* Bit 4:  Port Control Direction */
 #define USIC_SCTR_DOCFG_SHIFT       (6)       /* Bits 6-7: Data Output Configuration */
 #define USIC_SCTR_DOCFG_MASK        (3 << USIC_SCTR_DOCFG_SHIFT)
-  #define USIC_SCTR_DOCFG_SHIFT     (0 << USIC_SCTR_DOCFG_SHIFT) /* DOUTx = shift data value */
+  #define USIC_SCTR_DOCFG_NORMAL    (0 << USIC_SCTR_DOCFG_SHIFT) /* DOUTx = shift data value */
   #define USIC_SCTR_DOCFG_INVERT    (1 << USIC_SCTR_DOCFG_SHIFT) /* DOUTx = inverted shift data value */
 #define USIC_SCTR_TRM_SHIFT         (8)       /* Bits 8-9: Transmission Mode */
 #define USIC_SCTR_TRM_MASK          (3 << USIC_SCTR_TRM_SHIFT)
@@ -717,9 +717,9 @@
 #  define USIC_CCR_HPCEN_DX0_2      (3 << USIC_CCR_HPCEN_SHIFT) /* Port control enabled for DX0, DX[5:3] and DOUT[3:0] */
 #define USIC_CCR_PM_SHIFT           (8)       /* Bits 8-9: Parity Mode */
 #define USIC_CCR_PM_MASK            (3 << USIC_CCR_PM_SHIFT)
-#  define USIC_CCR_PM_ DISABLE      (0 << USIC_CCR_PM_SHIFT) /* Parity generation is disabled */
-#  define USIC_CCR_PM_ EVEN         (2 << USIC_CCR_PM_SHIFT) /* Even parity is selected */
-#  define USIC_CCR_PM_ ODD          (3 << USIC_CCR_PM_SHIFT) /* Odd parity is selected */
+#  define USIC_CCR_PM_DISABLE       (0 << USIC_CCR_PM_SHIFT) /* Parity generation is disabled */
+#  define USIC_CCR_PM_EVEN          (2 << USIC_CCR_PM_SHIFT) /* Even parity is selected */
+#  define USIC_CCR_PM_ODD           (3 << USIC_CCR_PM_SHIFT) /* Odd parity is selected */
 #define USIC_CCR_RSIEN              (1 << 10) /* Bit 10: Receiver Start Interrupt Enable */
 #define USIC_CCR_DLIEN              (1 << 11) /* Bit 11: Data Lost Interrupt Enable */
 #define USIC_CCR_TSIEN              (1 << 12) /* Bit 12: Transmit Shift Interrupt Enable */
diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c
index ec44caba54..28ae38195b 100644
--- a/arch/arm/src/xmc4/xmc4_lowputc.c
+++ b/arch/arm/src/xmc4/xmc4_lowputc.c
@@ -50,6 +50,7 @@
 #include "xmc4_config.h"
 #include "chip/xmc4_usic.h"
 #include "chip/xmc4_pinmux.h"
+#include "xmc4_lowputc.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -232,4 +233,3 @@ void xmc4_uart_configure(uintptr_t uart_base, uint32_t baud,
 #warning Missing logic
 }
 #endif
-
diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c
index 509cca5615..4992ddaeb8 100644
--- a/arch/arm/src/xmc4/xmc4_serial.c
+++ b/arch/arm/src/xmc4/xmc4_serial.c
@@ -57,9 +57,10 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "xmc4_config.h"
 #include "chip.h"
+#include "xmc4_config.h"
 #include "chip/xmc4_usic.h"
+#include "xmc4_lowputc.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c
index 7bf76f1fae..aade30978f 100644
--- a/arch/arm/src/xmc4/xmc4_start.c
+++ b/arch/arm/src/xmc4/xmc4_start.c
@@ -52,6 +52,7 @@
 #include "chip/xmc4_flash.h"
 
 #include "xmc4_userspace.h"
+#include "xmc4_lowputc.h"
 #include "xmc4_start.h"
 
 #ifdef CONFIG_ARCH_FPU