Rename sam_spi.h to samd_spi.h; Add saml_spi.h for the SAML21
This commit is contained in:
Gregory Nutt
parent
9d0db0aa4f
commit
aa74609424
@ -1,7 +1,7 @@
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/********************************************************************************************
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* arch/arm/src/samdl/chip/sam_spi.h
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* arch/arm/src/samdl/chip/samd_spi.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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@ -37,8 +37,8 @@
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAM_SPI_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAM_SPI_H
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_SPI_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_SPI_H
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/********************************************************************************************
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* Included Files
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@ -49,6 +49,8 @@
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#include "chip.h"
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#include "chip/sam_sercom.h"
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#ifdef CONFIG_ARCH_FAMILY_SAMD20
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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@ -229,4 +231,5 @@
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* Public Functions
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********************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAM_SPI_H */
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#endif /* CONFIG_ARCH_FAMILY_SAMD20 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_SPI_H */
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251
arch/arm/src/samdl/chip/saml_spi.h
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251
arch/arm/src/samdl/chip/saml_spi.h
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@ -0,0 +1,251 @@
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/********************************************************************************************
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* arch/arm/src/samdl/chip/saml_spi.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAML_SPI_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAML_SPI_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_sercom.h"
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#ifdef CONFIG_ARCH_FAMILY_SAML21
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* SPI register offsets *********************************************************************/
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#define SAM_SPI_CTRLA_OFFSET 0x0000 /* Control A register */
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#define SAM_SPI_CTRLB_OFFSET 0x0004 /* Control B register */
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#define SAM_SPI_BAUD_OFFSET 0x000a /* Baud register */
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#define SAM_SPI_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */
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#define SAM_SPI_INTENSET_OFFSET 0x000d /* Interrupt enable set register */
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#define SAM_SPI_INTFLAG_OFFSET 0x000e /* Interrupt flag and status clear register */
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#define SAM_SPI_STATUS_OFFSET 0x0010 /* Status register */
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#define SAM_SPI_SYNCBUSY_OFFSET 0x0010 /* Synchronization busy register */
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#define SAM_SPI_ADDR_OFFSET 0x0014 /* Address register */
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#define SAM_SPI_DATA_OFFSET 0x0018 /* Data register */
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#define SAM_SPI_DBGCTRL_OFFSET 0x0008 /* Debug control register */
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/* SPI register addresses *******************************************************************/
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#define SAM_SPI0_CTRLA (SAM_SERCOM0_BASE+SAM_SPI_CTRLA_OFFSET)
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#define SAM_SPI0_CTRLB (SAM_SERCOM0_BASE+SAM_SPI_CTRLB_OFFSET)
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#define SAM_SPI0_BAUD (SAM_SERCOM0_BASE+SAM_SPI_BAUD_OFFSET)
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#define SAM_SPI0_INTENCLR (SAM_SERCOM0_BASE+SAM_SPI_INTENCLR_OFFSET)
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#define SAM_SPI0_INTENSET (SAM_SERCOM0_BASE+SAM_SPI_INTENSET_OFFSET)
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#define SAM_SPI0_INTFLAG (SAM_SERCOM0_BASE+SAM_SPI_INTFLAG_OFFSET)
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#define SAM_SPI0_STATUS (SAM_SERCOM0_BASE+SAM_SPI_STATUS_OFFSET)
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#define SAM_SPI0_SYNCBUSY (SAM_SERCOM0_BASE+SAM_SPI_SYNCBUSY_OFFSET)
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#define SAM_SPI0_ADDR (SAM_SERCOM0_BASE+SAM_SPI_ADDR_OFFSET)
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#define SAM_SPI0_DATA (SAM_SERCOM0_BASE+SAM_SPI_DATA_OFFSET)
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#define SAM_SPI0_DBGCTRL (SAM_SERCOM0_BASE+SAM_SPI_DBGCTRL_OFFSET)
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#define SAM_SPI1_CTRLA (SAM_SERCOM1_BASE+SAM_SPI_CTRLA_OFFSET)
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#define SAM_SPI1_CTRLB (SAM_SERCOM1_BASE+SAM_SPI_CTRLB_OFFSET)
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#define SAM_SPI1_BAUD (SAM_SERCOM1_BASE+SAM_SPI_BAUD_OFFSET)
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#define SAM_SPI1_INTENCLR (SAM_SERCOM1_BASE+SAM_SPI_INTENCLR_OFFSET)
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#define SAM_SPI1_INTENSET (SAM_SERCOM1_BASE+SAM_SPI_INTENSET_OFFSET)
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#define SAM_SPI1_INTFLAG (SAM_SERCOM1_BASE+SAM_SPI_INTFLAG_OFFSET)
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#define SAM_SPI1_STATUS (SAM_SERCOM1_BASE+SAM_SPI_STATUS_OFFSET)
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#define SAM_SPI1_SYNCBUSY (SAM_SERCOM1_BASE+SAM_SPI_SYNCBUSY_OFFSET)
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#define SAM_SPI1_ADDR (SAM_SERCOM1_BASE+SAM_SPI_ADDR_OFFSET)
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#define SAM_SPI1_DATA (SAM_SERCOM1_BASE+SAM_SPI_DATA_OFFSET)
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#define SAM_SPI1_DBGCTRL (SAM_SERCOM1_BASE+SAM_SPI_DBGCTRL_OFFSET)
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#define SAM_SPI2_CTRLA (SAM_SERCOM2_BASE+SAM_SPI_CTRLA_OFFSET)
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#define SAM_SPI2_CTRLB (SAM_SERCOM2_BASE+SAM_SPI_CTRLB_OFFSET)
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#define SAM_SPI2_BAUD (SAM_SERCOM2_BASE+SAM_SPI_BAUD_OFFSET)
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#define SAM_SPI2_INTENCLR (SAM_SERCOM2_BASE+SAM_SPI_INTENCLR_OFFSET)
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#define SAM_SPI2_INTENSET (SAM_SERCOM2_BASE+SAM_SPI_INTENSET_OFFSET)
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#define SAM_SPI2_INTFLAG (SAM_SERCOM2_BASE+SAM_SPI_INTFLAG_OFFSET)
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#define SAM_SPI2_STATUS (SAM_SERCOM2_BASE+SAM_SPI_STATUS_OFFSET)
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#define SAM_SPI2_SYNCBUSY (SAM_SERCOM2_BASE+SAM_SPI_SYNCBUSY_OFFSET)
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#define SAM_SPI2_ADDR (SAM_SERCOM2_BASE+SAM_SPI_ADDR_OFFSET)
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#define SAM_SPI2_DATA (SAM_SERCOM2_BASE+SAM_SPI_DATA_OFFSET)
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#define SAM_SPI2_DBGCTRL (SAM_SERCOM2_BASE+SAM_SPI_DBGCTRL_OFFSET)
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#define SAM_SPI3_CTRLA (SAM_SERCOM3_BASE+SAM_SPI_CTRLA_OFFSET)
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#define SAM_SPI3_CTRLB (SAM_SERCOM3_BASE+SAM_SPI_CTRLB_OFFSET)
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#define SAM_SPI3_BAUD (SAM_SERCOM3_BASE+SAM_SPI_BAUD_OFFSET)
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#define SAM_SPI3_INTENCLR (SAM_SERCOM3_BASE+SAM_SPI_INTENCLR_OFFSET)
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#define SAM_SPI3_INTENSET (SAM_SERCOM3_BASE+SAM_SPI_INTENSET_OFFSET)
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#define SAM_SPI3_INTFLAG (SAM_SERCOM3_BASE+SAM_SPI_INTFLAG_OFFSET)
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#define SAM_SPI3_STATUS (SAM_SERCOM3_BASE+SAM_SPI_STATUS_OFFSET)
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#define SAM_SPI3_SYNCBUSY (SAM_SERCOM3_BASE+SAM_SPI_SYNCBUSY_OFFSET)
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#define SAM_SPI3_ADDR (SAM_SERCOM3_BASE+SAM_SPI_ADDR_OFFSET)
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#define SAM_SPI3_DATA (SAM_SERCOM3_BASE+SAM_SPI_DATA_OFFSET)
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#define SAM_SPI3_DBGCTRL (SAM_SERCOM3_BASE+SAM_SPI_DBGCTRL_OFFSET)
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#define SAM_SPI4_CTRLA (SAM_SERCOM4_BASE+SAM_SPI_CTRLA_OFFSET)
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#define SAM_SPI4_CTRLB (SAM_SERCOM4_BASE+SAM_SPI_CTRLB_OFFSET)
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#define SAM_SPI4_BAUD (SAM_SERCOM4_BASE+SAM_SPI_BAUD_OFFSET)
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#define SAM_SPI4_INTENCLR (SAM_SERCOM4_BASE+SAM_SPI_INTENCLR_OFFSET)
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#define SAM_SPI4_INTENSET (SAM_SERCOM4_BASE+SAM_SPI_INTENSET_OFFSET)
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#define SAM_SPI4_INTFLAG (SAM_SERCOM4_BASE+SAM_SPI_INTFLAG_OFFSET)
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#define SAM_SPI4_STATUS (SAM_SERCOM4_BASE+SAM_SPI_STATUS_OFFSET)
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#define SAM_SPI4_SYNCBUSY (SAM_SERCOM4_BASE+SAM_SPI_SYNCBUSY_OFFSET)
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#define SAM_SPI4_ADDR (SAM_SERCOM4_BASE+SAM_SPI_ADDR_OFFSET)
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#define SAM_SPI4_DATA (SAM_SERCOM4_BASE+SAM_SPI_DATA_OFFSET)
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#define SAM_SPI4_DBGCTRL (SAM_SERCOM4_BASE+SAM_SPI_DBGCTRL_OFFSET)
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#define SAM_SPI5_CTRLA (SAM_SERCOM5_BASE+SAM_SPI_CTRLA_OFFSET)
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#define SAM_SPI5_CTRLB (SAM_SERCOM5_BASE+SAM_SPI_CTRLB_OFFSET)
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#define SAM_SPI5_BAUD (SAM_SERCOM5_BASE+SAM_SPI_BAUD_OFFSET)
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#define SAM_SPI5_INTENCLR (SAM_SERCOM5_BASE+SAM_SPI_INTENCLR_OFFSET)
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#define SAM_SPI5_INTENSET (SAM_SERCOM5_BASE+SAM_SPI_INTENSET_OFFSET)
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#define SAM_SPI5_INTFLAG (SAM_SERCOM5_BASE+SAM_SPI_INTFLAG_OFFSET)
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#define SAM_SPI5_STATUS (SAM_SERCOM5_BASE+SAM_SPI_STATUS_OFFSET)
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#define SAM_SPI5_SYNCBUSY (SAM_SERCOM5_BASE+SAM_SPI_SYNCBUSY_OFFSET)
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#define SAM_SPI5_ADDR (SAM_SERCOM5_BASE+SAM_SPI_ADDR_OFFSET)
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#define SAM_SPI5_DATA (SAM_SERCOM5_BASE+SAM_SPI_DATA_OFFSET)
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#define SAM_SPI5_DBGCTRL (SAM_SERCOM5_BASE+SAM_SPI_DBGCTRL_OFFSET)
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/* SPI register bit definitions *************************************************************/
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/* Control A register */
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#define SPI_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
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#define SPI_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
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#define SPI_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */
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#define SPI_CTRLA_MODE_MASK (7 << SPI_CTRLA_MODE_SHIFT)
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# define SPI_CTRLA_MODE_SLAVE (2 << SPI_CTRLA_MODE_SHIFT) /* SPI slave operation */
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# define SPI_CTRLA_MODE_MASTER (3 << SPI_CTRLA_MODE_SHIFT) /* SPI master operation */
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#define SPI_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */
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#define SPI_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */
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#define SPI_CTRLA_DOPO_SHIFT (16) /* Bit 16-17: Data out pinout */
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#define SPI_CTRLA_DOPO_MASK (3 << SPI_CTRLA_DOPO_SHIFT) /* Bit 16-17: Data out pinout */
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# define SPI_CTRLA_DOPO_DOPAD012 (0 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD0 SCK=PAD1 SS=PAD2 */
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# define SPI_CTRLA_DOPO_DOPAD231 (1 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD2 SCK=PAD3 SS=PAD1 */
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# define SPI_CTRLA_DOPO_DOPAD312 (2 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD3 SCK=PAD1 SS=PAD2 */
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# define SPI_CTRLA_DOPO_DOPAD031 (3 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD0 SCK=PAD3 SS=PAD1 */
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#define SPI_CTRLA_DIPO_SHIFT (20) /* Bits 20-21: Data in pinout */
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#define SPI_CTRLA_DIPO_MASK (3 << SPI_CTRLA_DIPO_SHIFT)
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# define SPI_CTRLA_DIPAD0 (0 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD0 for DI */
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# define SPI_CTRLA_DIPAD1 (1 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD1 for DI */
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# define SPI_CTRLA_DIPAD2 (2 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD2 for DI */
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# define SPI_CTRLA_DIPAD3 (3 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD3 for DI */
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#define SPI_CTRLA_FORM_SHIFT (24) /* Bits 24-27: Frame format */
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#define SPI_CTRLA_FORM_MASK (7 << SPI_CTRLA_FORM_SHIFT)
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# define SPI_CTRLA_FORM_SPI (0 << SPI_CTRLA_FORM_SHIFT) /* SPI frame (no address) */
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# define SPI_CTRLA_FORM_ADDR (2 << SPI_CTRLA_FORM_SHIFT) /* SPI frame (w/address) */
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#define SPI_CTRLA_CPHA (1 << 28) /* Bit 28: Clock phase */
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#define SPI_CTRLA_CPOL (1 << 29) /* Bit 29: Clock polarity */
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#define SPI_CTRLA_DORD (1 << 30) /* Bit 30: Data order */
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# define SPI_CTRLA_MSBFIRST (0)
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# define SPI_CTRLA_LSBFIRST SPI_CTRLA_DORD
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/* Control B register */
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#define SPI_CTRLB_CHSIZE_SHIFT (0) /* Bits 0-2: Character Size */
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#define SPI_CTRLB_CHSIZE_MASK (7 << SPI_CTRLB_CHSIZE_SHIFT)
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# define SPI_CTRLB_CHSIZE_8BITS (0 << SPI_CTRLB_CHSIZE_SHIFT) /* 8 bits */
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# define SPI_CTRLB_CHSIZE_9BITS (1 << SPI_CTRLB_CHSIZE_SHIFT) /* 9 bits */
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#define SPI_CTRLB_PLOADEN (1 << 6) /* Bit 6: Slave Data Preload Enable */
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#define SPI_CTRLB_SSDE (1 << 9) /* Bit 9: Slave select low detect enable */
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#define SPI_CTRLB_MSSEN (1 << 13) /* Bit 13: Master slave select enable */
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#define SPI_CTRLB_AMODE_SHIFT (14) /* Bits 14-15: Address Mode */
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#define SPI_CTRLB_AMODE_MASK (3 << SPI_CTRLB_AMODE_SHIFT)
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# define SPI_CTRLB_AMODE_ADDRMASK (0 << SPI_CTRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */
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# define SPI_CTRLB_AMODE_2ADDRS (1 << SPI_CTRLB_AMODE_SHIFT) /* Slave 2 addresses: ADDR & ADDRMASK */
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# define SPI_CTRLB_AMODE_RANGE (2 << SPI_CTRLB_AMODE_SHIFT) /* Slave range of addresses: ADDRMASK-ADDR */
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#define SPI_CTRLB_RXEN (1 << 17) /* Bit 17: Receiver enable */
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/* Baud register (8-bit baud value) */
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/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and
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* status clear registers.
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*/
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#define SPI_INT_DRE (1 << 0) /* Bit 0: Data register empty interrupt */
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#define SPI_INT_TXC (1 << 1) /* Bit 1: Transmit complete interrupt */
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#define SPI_INT_RXC (1 << 2) /* Bit 2: Receive complete interrupt */
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#define SPI_INT_SSL (1 << 3) /* Bit 3: Slave select low interrupt */
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#define SPI_INT_ERROR (1 << 7) /* Bit 7: Error interrupt */
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#define SPI_INT_ALL (0x0f)
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/* Status register */
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#define SPI_STATUS_BUFOVF (1 << 2) /* Bit 2: Buffer overflow */
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#define SPI_STATUS_CLRALL SPI_STATUS_BUFOVF
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/* Synchronization busy register */
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#define SPI_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */
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#define SPI_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: SERCOM enable synchronization busy */
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#define SPI_SYNCBUSY_CTRLB (1 << 2) /* Bit 2: CTRLB synchronization busy */
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/* Address register */
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#define SPI_ADDR_SHIFT (0) /* Bits 0-7: Address */
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#define SPI_ADDR_MASK (0xff << SPI_ADDR_SHIFT)
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# define SPI_ADDR(n) ((uint32_t)(n) << SPI_ADDR_SHIFT)
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#define SPI_ADDRMASK_SHIFT (16) /* Bits 16-23: Address Mask */
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#define SPI_ADDRMASK_MASK (0xff << SPI_ADDRMASK_SHIFT)
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# define SPI_ADDRMASK(n) ((uint32_t)(n) << SPI_ADDRMASK_SHIFT)
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/* Data register */
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#define SPI_DATA_MASK (0x1ff) /* Bits 0-8: Data */
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/* Debug control register */
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#define SPI_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAML21 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAML_SPI_H */
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@ -64,7 +64,6 @@
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#include "chip.h"
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#include "chip/sam_port.h"
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#include "chip/sam_pinmap.h"
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#include "chip/sam_spi.h"
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#include <arch/board/board.h>
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@ -47,6 +47,12 @@
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#include "sam_config.h"
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#if defined(CONFIG_ARCH_FAMILY_SAMD20)
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# include "chip/samd_spi.h"
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#elif defined(CONFIG_ARCH_FAMILY_SAML21)
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# include "chip/saml_spi.h"
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#endif
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#ifdef SAMDL_HAVE_SPI
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/****************************************************************************
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