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arch/arm/src/tiva/hardware:  Completes the CC13x2 AUX SYSIF header file.

    arch/arm/src/tiva/hardware:  Progress on the CC13x2 AUX SYSIF header file.  Almost complete.

    arch/arm/src/tiva/hardware:  Port needs aux_sysif.h header file.

    arch/arm/src/tiva/cc13xx/cc13x0_rom.h:  Fix a typo

    arch/arm/src/tiva/cc13xx:  More changes to TI DriverLib ROM header files for NuttX coding standard.

    arch/arm/src/tiva/cc13xx:  Convert some (but not all) TI DriverLib ROM function names to NuttX coding standard.  More to be done.

    arm/src/tiva/cc13xx:  ROM header files: missed a couple of conversions of sructure field names to lower case (vs CamelCase).

    arm/src/tiva/cc13xx:  ROM header files: type'ed names must be lower case per coding standard (not upper case); structure field names must be lower case per coding standard (not CamelCase).

     arch/arm/src/tiva/cc13xx:  Trim logic needs to include matching ROM DriverLib interface header file.

    arch/arm/src/tiva/cc13xx:  Add ROM DriverLib header files.  Do not yet fully conform to the NuttX coding style.
This commit is contained in:
Gregory Nutt 2019-01-20 17:59:22 -06:00
parent 3a13d4a5f5
commit aa99e2d6da
12 changed files with 3654 additions and 3 deletions
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1
arch/arm/src/tiva/Make.defs
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@ -107,6 +107,7 @@ else ifeq ($(CONFIG_ARCH_CHIP_CC13X0),y)
else ifeq ($(CONFIG_ARCH_CHIP_CC13X2),y)
CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_chipinfo.c cc13xx_gpio.c
CHIP_CSRCS += cc13xx_gpioirq.c cc13xx_enableclks.c cc13xx_enablepwr.c
CHIP_CSRCS += cc13x2_aux_sysif.c
ifeq ($(CONFIG_ARCH_CHIP_CC13XX_V1),y)
CHIP_CSRCS += cc13x2_v1_trim.c
else

663
arch/arm/src/tiva/cc13xx/cc13x0_rom.h Normal file
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@ -0,0 +1,663 @@
/************************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x0_rom.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* This is a port of TI's rom.h file which has a fully compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13X0_ROM_H
#define __ARCH_ARM_SRC_TIVA_CC13XX_CC13X0_ROM_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Start address of the ROM hard API access table (located after the ROM FW rev field) */
#define ROM_HAPI_TABLE_ADDR 0x10000048
/* Pointer to the ROM HAPI table */
#define P_HARD_API ((hard_api_t *)ROM_HAPI_TABLE_ADDR)
#define hapi_crc32(a,b,c) P_HARD_API->crc32(a,b,c)
#define hapi_get_flashsize() P_HARD_API->get_flashsize()
#define hapi_get_chipid() P_HARD_API->get_chipid()
#define hapi_reset_device() P_HARD_API->reset_device()
#define hapi_fletcher32(a,b,c) P_HARD_API->fletcher32(a,b,c)
#define hapi_min(a,b) P_HARD_API->min(a,b)
#define hapi_max(a,b) P_HARD_API->max(a,b)
#define hapi_mean(a,b) P_HARD_API->mean(a,b)
#define hapi_standard_devation(a,b) P_HARD_API->standard_devation(a,b)
/* REVISIT: In the TI Driverlib, the following go through a "Safe" layer */
#define hapi_source_safeswitch() P_HARD_API->hf_source_safeswitch()
#define hapi_select_compa_input(a) P_HARD_API->select_compa_input(a)
#define hapi_select_compa_ref(a) P_HARD_API->select_compa_ref(a)
#define hapi_select_adc_compb_input(a) P_HARD_API->select_adc_compb_input(a)
#define hapi_select_adc_compb_ref(a) P_HARD_API->select_adc_compb_ref(a)
/* Defines for input parameter to the hapi_select_compa_input function.
* The define values can not be changed!
*/
#define COMPA_IN_NC 0x00
#define COMPA_IN_AUXIO7 0x09
#define COMPA_IN_AUXIO6 0x0a
#define COMPA_IN_AUXIO5 0x0b
#define COMPA_IN_AUXIO4 0x0c
#define COMPA_IN_AUXIO3 0x0d
#define COMPA_IN_AUXIO2 0x0e
#define COMPA_IN_AUXIO1 0x0f
#define COMPA_IN_AUXIO0 0x10
/* Defines for input parameter to the hapi_select_compa_ref function.
* The define values can not be changed!
*/
#define COMPA_REF_NC 0x00
#define COMPA_REF_DCOUPL 0x01
#define COMPA_REF_VSS 0x02
#define COMPA_REF_VDDS 0x03
#define COMPA_REF_ADCVREFP 0x04
#define COMPA_REF_AUXIO7 0x09
#define COMPA_REF_AUXIO6 0x0a
#define COMPA_REF_AUXIO5 0x0b
#define COMPA_REF_AUXIO4 0x0c
#define COMPA_REF_AUXIO3 0x0d
#define COMPA_REF_AUXIO2 0x0e
#define COMPA_REF_AUXIO1 0x0f
#define COMPA_REF_AUXIO0 0x10
/* Defines for input parameter to the hapi_select_adc_compb_input function.
* The define values can not be changed!
*/
#define ADC_COMPB_IN_NC 0x00
#define ADC_COMPB_IN_DCOUPL 0x03
#define ADC_COMPB_IN_VSS 0x04
#define ADC_COMPB_IN_VDDS 0x05
#define ADC_COMPB_IN_AUXIO7 0x09
#define ADC_COMPB_IN_AUXIO6 0x0a
#define ADC_COMPB_IN_AUXIO5 0x0b
#define ADC_COMPB_IN_AUXIO4 0x0c
#define ADC_COMPB_IN_AUXIO3 0x0d
#define ADC_COMPB_IN_AUXIO2 0x0e
#define ADC_COMPB_IN_AUXIO1 0x0f
#define ADC_COMPB_IN_AUXIO0 0x10
/* Defines for input parameter to the hapi_select_adc_compb_ref function.
* The define values can not be changed!
*/
#define COMPB_REF_NC 0x00
#define COMPB_REF_DCOUPL 0x01
#define COMPB_REF_VSS 0x02
#define COMPB_REF_VDDS 0x03
/* Pointers to the main API tables */
#define ROM_API_TABLE ((uint32_t *) 0x10000180)
#define ROM_VERSION (ROM_API_TABLE[0])
#define ROM_API_AON_EVENT_TABLE ((uint32_t *) (ROM_API_TABLE[1]))
#define ROM_API_AON_IOC_TABLE ((uint32_t *) (ROM_API_TABLE[2]))
#define ROM_API_AON_RTC_TABLE ((uint32_t *) (ROM_API_TABLE[3]))
#define ROM_API_AON_WUC_TABLE ((uint32_t *) (ROM_API_TABLE[4]))
#define ROM_API_AUX_CTRL_TABLE ((uint32_t *) (ROM_API_TABLE[5]))
#define ROM_API_AUX_TDC_TABLE ((uint32_t *) (ROM_API_TABLE[6]))
#define ROM_API_AUX_TIMER_TABLE ((uint32_t *) (ROM_API_TABLE[7]))
#define ROM_API_AUX_WUC_TABLE ((uint32_t *) (ROM_API_TABLE[8]))
#define ROM_API_DDI_TABLE ((uint32_t *) (ROM_API_TABLE[9]))
#define ROM_API_FLASH_TABLE ((uint32_t *) (ROM_API_TABLE[10]))
#define ROM_API_I2C_TABLE ((uint32_t *) (ROM_API_TABLE[11]))
#define ROM_API_INTERRUPT_TABLE ((uint32_t *) (ROM_API_TABLE[12]))
#define ROM_API_IOC_TABLE ((uint32_t *) (ROM_API_TABLE[13]))
#define ROM_API_PRCM_TABLE ((uint32_t *) (ROM_API_TABLE[14]))
#define ROM_API_SMPH_TABLE ((uint32_t *) (ROM_API_TABLE[15]))
#define ROM_API_SSI_TABLE ((uint32_t *) (ROM_API_TABLE[17]))
#define ROM_API_TIMER_TABLE ((uint32_t *) (ROM_API_TABLE[18]))
#define ROM_API_TRNG_TABLE ((uint32_t *) (ROM_API_TABLE[19]))
#define ROM_API_UART_TABLE ((uint32_t *) (ROM_API_TABLE[20]))
#define ROM_API_UDMA_TABLE ((uint32_t *) (ROM_API_TABLE[21]))
#define ROM_API_VIMS_TABLE ((uint32_t *) (ROM_API_TABLE[22]))
/* AON_EVENT FUNCTIONS */
#define ROM_AONEventMcuWakeUpSet \
((void (*)(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)) \
ROM_API_AON_EVENT_TABLE[0])
#define ROM_AONEventMcuWakeUpGet \
((uint32_t (*)(uint32_t ui32MCUWUEvent)) \
ROM_API_AON_EVENT_TABLE[1])
#define ROM_AONEventAuxWakeUpSet \
((void (*)(uint32_t ui32AUXWUEvent, uint32_t ui32EventSrc)) \
ROM_API_AON_EVENT_TABLE[2])
#define ROM_AONEventAuxWakeUpGet \
((uint32_t (*)(uint32_t ui32AUXWUEvent)) \
ROM_API_AON_EVENT_TABLE[3])
#define ROM_AONEventMcuSet \
((void (*)(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)) \
ROM_API_AON_EVENT_TABLE[4])
#define ROM_AONEventMcuGet \
((uint32_t (*)(uint32_t ui32MCUEvent)) \
ROM_API_AON_EVENT_TABLE[5])
/* AON_WUC FUNCTIONS */
#define ROM_AONWUCAuxReset \
((void (*)(void)) \
ROM_API_AON_WUC_TABLE[3])
#define ROM_AONWUCRechargeCtrlConfigSet \
((void (*)(bool bAdaptEnable, uint32_t ui32AdaptRate, uint32_t ui32Period, uint32_t ui32MaxPeriod)) \
ROM_API_AON_WUC_TABLE[4])
#define ROM_AONWUCOscConfig \
((void (*)(uint32_t ui32Period)) \
ROM_API_AON_WUC_TABLE[5])
/* AUX_TDC FUNCTIONS */
#define ROM_AUXTDCConfigSet \
((void (*)(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition)) \
ROM_API_AUX_TDC_TABLE[0])
#define ROM_AUXTDCMeasurementDone \
((uint32_t (*)(uint32_t ui32Base)) \
ROM_API_AUX_TDC_TABLE[1])
/* AUX_WUC FUNCTIONS */
#define ROM_AUXWUCClockEnable \
((void (*)(uint32_t ui32Clocks)) \
ROM_API_AUX_WUC_TABLE[0])
#define ROM_AUXWUCClockDisable \
((void (*)(uint32_t ui32Clocks)) \
ROM_API_AUX_WUC_TABLE[1])
#define ROM_AUXWUCClockStatus \
((uint32_t (*)(uint32_t ui32Clocks)) \
ROM_API_AUX_WUC_TABLE[2])
#define ROM_AUXWUCPowerCtrl \
((void (*)(uint32_t ui32PowerMode)) \
ROM_API_AUX_WUC_TABLE[3])
/* DDI FUNCTIONS */
#define ROM_DDI16BitWrite \
((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData)) \
ROM_API_DDI_TABLE[0])
#define ROM_DDI16BitfieldWrite \
((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)) \
ROM_API_DDI_TABLE[1])
#define ROM_DDI16BitRead \
((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)) \
ROM_API_DDI_TABLE[2])
#define ROM_DDI16BitfieldRead \
((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift)) \
ROM_API_DDI_TABLE[3])
/* FLASH FUNCTIONS */
#define ROM_FlashPowerModeGet \
((uint32_t (*)(void)) \
ROM_API_FLASH_TABLE[1])
#define ROM_FlashProtectionSet \
((void (*)(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)) \
ROM_API_FLASH_TABLE[2])
#define ROM_FlashProtectionGet \
((uint32_t (*)(uint32_t ui32SectorAddress)) \
ROM_API_FLASH_TABLE[3])
#define ROM_FlashProtectionSave \
((uint32_t (*)(uint32_t ui32SectorAddress)) \
ROM_API_FLASH_TABLE[4])
#define ROM_FlashEfuseReadRow \
((bool (*)(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)) \
ROM_API_FLASH_TABLE[8])
#define ROM_FlashDisableSectorsForWrite \
((void (*)(void)) \
ROM_API_FLASH_TABLE[9])
/* I2C FUNCTIONS */
#define ROM_I2CMasterInitExpClk \
((void (*)(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)) \
ROM_API_I2C_TABLE[0])
#define ROM_I2CMasterErr \
((uint32_t (*)(uint32_t ui32Base)) \
ROM_API_I2C_TABLE[1])
/* INTERRUPT FUNCTIONS */
#define ROM_IntPriorityGroupingSet \
((void (*)(uint32_t ui32Bits)) \
ROM_API_INTERRUPT_TABLE[0])
#define ROM_IntPriorityGroupingGet \
((uint32_t (*)(void)) \
ROM_API_INTERRUPT_TABLE[1])
#define ROM_IntPrioritySet \
((void (*)(uint32_t ui32Interrupt, uint8_t ui8Priority)) \
ROM_API_INTERRUPT_TABLE[2])
#define ROM_IntPriorityGet \
((int32_t (*)(uint32_t ui32Interrupt)) \
ROM_API_INTERRUPT_TABLE[3])
#define ROM_IntEnable \
((void (*)(uint32_t ui32Interrupt)) \
ROM_API_INTERRUPT_TABLE[4])
#define ROM_IntDisable \
((void (*)(uint32_t ui32Interrupt)) \
ROM_API_INTERRUPT_TABLE[5])
#define ROM_IntPendSet \
((void (*)(uint32_t ui32Interrupt)) \
ROM_API_INTERRUPT_TABLE[6])
#define ROM_IntPendGet \
((bool (*)(uint32_t ui32Interrupt)) \
ROM_API_INTERRUPT_TABLE[7])
#define ROM_IntPendClear \
((void (*)(uint32_t ui32Interrupt)) \
ROM_API_INTERRUPT_TABLE[8])
/* IOC FUNCTIONS */
#define ROM_IOCPortConfigureSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)) \
ROM_API_IOC_TABLE[0])
#define ROM_IOCPortConfigureGet \
((uint32_t (*)(uint32_t ui32IOId)) \
ROM_API_IOC_TABLE[1])
#define ROM_IOCIOShutdownSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32IOShutdown)) \
ROM_API_IOC_TABLE[2])
#define ROM_IOCIOModeSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32IOMode)) \
ROM_API_IOC_TABLE[4])
#define ROM_IOCIOIntSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)) \
ROM_API_IOC_TABLE[5])
#define ROM_IOCIOPortPullSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32Pull)) \
ROM_API_IOC_TABLE[6])
#define ROM_IOCIOHystSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32Hysteresis)) \
ROM_API_IOC_TABLE[7])
#define ROM_IOCIOInputSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32Input)) \
ROM_API_IOC_TABLE[8])
#define ROM_IOCIOSlewCtrlSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32SlewEnable)) \
ROM_API_IOC_TABLE[9])
#define ROM_IOCIODrvStrengthSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength)) \
ROM_API_IOC_TABLE[10])
#define ROM_IOCIOPortIdSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32PortId)) \
ROM_API_IOC_TABLE[11])
#define ROM_IOCIntEnable \
((void (*)(uint32_t ui32IOId)) \
ROM_API_IOC_TABLE[12])
#define ROM_IOCIntDisable \
((void (*)(uint32_t ui32IOId)) \
ROM_API_IOC_TABLE[13])
#define ROM_IOCPinTypeGpioInput \
((void (*)(uint32_t ui32IOId)) \
ROM_API_IOC_TABLE[14])
#define ROM_IOCPinTypeGpioOutput \
((void (*)(uint32_t ui32IOId)) \
ROM_API_IOC_TABLE[15])
#define ROM_IOCPinTypeUart \
((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts)) \
ROM_API_IOC_TABLE[16])
#define ROM_IOCPinTypeSsiMaster \
((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \
ROM_API_IOC_TABLE[17])
#define ROM_IOCPinTypeSsiSlave \
((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \
ROM_API_IOC_TABLE[18])
#define ROM_IOCPinTypeI2c \
((void (*)(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)) \
ROM_API_IOC_TABLE[19])
#define ROM_IOCPinTypeAux \
((void (*)(uint32_t ui32IOId)) \
ROM_API_IOC_TABLE[21])
/* PRCM FUNCTIONS */
#define ROM_PRCMInfClockConfigureSet \
((void (*)(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)) \
ROM_API_PRCM_TABLE[0])
#define ROM_PRCMInfClockConfigureGet \
((uint32_t (*)(uint32_t ui32PowerMode)) \
ROM_API_PRCM_TABLE[1])
#define ROM_PRCMAudioClockConfigSet \
((void (*)(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)) \
ROM_API_PRCM_TABLE[4])
#define ROM_PRCMPowerDomainOn \
((void (*)(uint32_t ui32Domains)) \
ROM_API_PRCM_TABLE[5])
#define ROM_PRCMPowerDomainOff \
((void (*)(uint32_t ui32Domains)) \
ROM_API_PRCM_TABLE[6])
#define ROM_PRCMPeripheralRunEnable \
((void (*)(uint32_t ui32Peripheral)) \
ROM_API_PRCM_TABLE[7])
#define ROM_PRCMPeripheralRunDisable \
((void (*)(uint32_t ui32Peripheral)) \
ROM_API_PRCM_TABLE[8])
#define ROM_PRCMPeripheralSleepEnable \
((void (*)(uint32_t ui32Peripheral)) \
ROM_API_PRCM_TABLE[9])
#define ROM_PRCMPeripheralSleepDisable \
((void (*)(uint32_t ui32Peripheral)) \
ROM_API_PRCM_TABLE[10])
#define ROM_PRCMPeripheralDeepSleepEnable \
((void (*)(uint32_t ui32Peripheral)) \
ROM_API_PRCM_TABLE[11])
#define ROM_PRCMPeripheralDeepSleepDisable \
((void (*)(uint32_t ui32Peripheral)) \
ROM_API_PRCM_TABLE[12])
#define ROM_PRCMPowerDomainStatus \
((uint32_t (*)(uint32_t ui32Domains)) \
ROM_API_PRCM_TABLE[13])
#define ROM_PRCMDeepSleep \
((void (*)(void)) \
ROM_API_PRCM_TABLE[14])
/* SMPH FUNCTIONS */
#define ROM_SMPHAcquire \
((void (*)(uint32_t ui32Semaphore)) \
ROM_API_SMPH_TABLE[0])
/* SSI FUNCTIONS */
#define ROM_SSIConfigSetExpClk \
((void (*)(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth)) \
ROM_API_SSI_TABLE[0])
#define ROM_SSIDataPut \
((void (*)(uint32_t ui32Base, uint32_t ui32Data)) \
ROM_API_SSI_TABLE[1])
#define ROM_SSIDataPutNonBlocking \
((int32_t (*)(uint32_t ui32Base, uint32_t ui32Data)) \
ROM_API_SSI_TABLE[2])
#define ROM_SSIDataGet \
((void (*)(uint32_t ui32Base, uint32_t *pui32Data)) \
ROM_API_SSI_TABLE[3])
#define ROM_SSIDataGetNonBlocking \
((int32_t (*)(uint32_t ui32Base, uint32_t *pui32Data)) \
ROM_API_SSI_TABLE[4])
/* TIMER FUNCTIONS */
#define ROM_TimerConfigure \
((void (*)(uint32_t ui32Base, uint32_t ui32Config)) \
ROM_API_TIMER_TABLE[0])
#define ROM_TimerLevelControl \
((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)) \
ROM_API_TIMER_TABLE[1])
#define ROM_TimerStallControl \
((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)) \
ROM_API_TIMER_TABLE[3])
#define ROM_TimerWaitOnTriggerControl \
((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)) \
ROM_API_TIMER_TABLE[4])
/* TRNG FUNCTIONS */
#define ROM_TRNGNumberGet \
((uint32_t (*)(uint32_t ui32Word)) \
ROM_API_TRNG_TABLE[1])
/* UART FUNCTIONS */
#define ROM_UARTFIFOLevelGet \
((void (*)(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel)) \
ROM_API_UART_TABLE[0])
#define ROM_UARTConfigSetExpClk \
((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config)) \
ROM_API_UART_TABLE[1])
#define ROM_UARTConfigGetExpClk \
((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config)) \
ROM_API_UART_TABLE[2])
#define ROM_UARTDisable \
((void (*)(uint32_t ui32Base)) \
ROM_API_UART_TABLE[3])
#define ROM_UARTCharGetNonBlocking \
((int32_t (*)(uint32_t ui32Base)) \
ROM_API_UART_TABLE[4])
#define ROM_UARTCharGet \
((int32_t (*)(uint32_t ui32Base)) \
ROM_API_UART_TABLE[5])
#define ROM_UARTCharPutNonBlocking \
((bool (*)(uint32_t ui32Base, uint8_t ui8Data)) \
ROM_API_UART_TABLE[6])
#define ROM_UARTCharPut \
((void (*)(uint32_t ui32Base, uint8_t ui8Data)) \
ROM_API_UART_TABLE[7])
/* UDMA FUNCTIONS */
#define ROM_uDMAChannelAttributeEnable \
((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \
ROM_API_UDMA_TABLE[0])
#define ROM_uDMAChannelAttributeDisable \
((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \
ROM_API_UDMA_TABLE[1])
#define ROM_uDMAChannelAttributeGet \
((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \
ROM_API_UDMA_TABLE[2])
#define ROM_uDMAChannelControlSet \
((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control)) \
ROM_API_UDMA_TABLE[3])
#define ROM_uDMAChannelScatterGatherSet \
((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)) \
ROM_API_UDMA_TABLE[5])
#define ROM_uDMAChannelSizeGet \
((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \
ROM_API_UDMA_TABLE[6])
#define ROM_uDMAChannelModeGet \
((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \
ROM_API_UDMA_TABLE[7])
/* VIMS FUNCTIONS */
#define ROM_VIMSConfigure \
((void (*)(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)) \
ROM_API_VIMS_TABLE[0])
#define ROM_VIMSModeSet \
((void (*)(uint32_t ui32Base, uint32_t ui32Mode)) \
ROM_API_VIMS_TABLE[1])
/************************************************************************************
* Public Types
************************************************************************************/
/* ROM Hard-API function interface types */
typedef uint32_t (*fptr_crc32_t) (uint8_t * /* data */,\
uint32_t /* bytecount */,\
uint32_t /* repeatcount */);
typedef uint32_t (*fptr_getflsize_t) (void);
typedef uint32_t (*fptr_getchipid_t) (void);
typedef uint32_t (*fptr_reserved1_t) (uint32_t);
typedef uint32_t (*fptr_reserved2_t) (void);
typedef uint32_t (*fptr_reserved3_t) (uint8_t *,\
uint32_t ,\
uint32_t);
typedef void (*fptr_resetdev_t) (void);
typedef uint32_t (*fptr_fletcher32_t) (uint16_t * /* data */,\
uint16_t /* wordcount */,\
uint16_t /* repeatcount */);
typedef uint32_t (*fptr_minval_t) (uint32_t * /* data */,\
uint32_t /* count */);
typedef uint32_t (*fptr_maxval_t) (uint32_t * /* buffer */,\
uint32_t /* count */);
typedef uint32_t (*fptr_meanval_t) (uint32_t * /* buffer */,\
uint32_t /* count */);
typedef uint32_t (*fptr_stddval_t) (uint32_t * /* buffer */,\
uint32_t /* count */);
typedef void (*fptr_hfsourcesafeswitch_t) (void);
typedef void (*fptr_reserved4_t) (uint32_t);
typedef void (*fptr_reserved5_t) (uint32_t);
typedef void (*fptr_compain_t) (uint8_t /* signal */);
typedef void (*fptr_comparef_t) (uint8_t /* signal */);
typedef void (*fptr_adccompbin_t) (uint8_t /* signal */);
typedef void (*fptr_compbref_t) (uint8_t /* signal */);
/* ROM Hard-API access table type */
struct hard_api_s
{
fptr_crc32_t crc32;
fptr_getflsize_t get_flashsize;
fptr_getchipid_t get_chipid;
fptr_reserved1_t reserved1;
fptr_reserved2_t reserved2;
fptr_reserved3_t reserved3;
fptr_resetdev_t reset_device;
fptr_fletcher32_t fletcher32;
fptr_minval_t min;
fptr_maxval_t max;
fptr_meanval_t mean;
fptr_stddval_t standard_devation;
fptr_reserved4_t reserved4;
fptr_reserved5_t reserved5;
fptr_hfsourcesafeswitch_t hf_source_safeswitch;
fptr_compain_t select_compa_input;
fptr_comparef_t select_compa_ref;
fptr_adccompbin_t select_adc_compb_input;
fptr_compbref_t select_adc_compb_ref;
};
typedef struct hard_api_s hard_api_t;
#endif /* __ARCH_ARM_SRC_TIVA_CC13XX_CC13X0_ROM_H */

2
arch/arm/src/tiva/cc13xx/cc13x0_trim.c
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@ -57,6 +57,8 @@
#include "hardware/tiva_prcm.h"
#include "hardware/tiva_vims.h"
#include "cc13xx/cc13x0_rom.h"
/******************************************************************************
* Private Functions
******************************************************************************/

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/*****************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x2_aux_sysif.c
* Driver for the AUX System Interface
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI aux_sysif.c file that has a compatible BSD
* license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <stdint.h>
#include "up_arch.h"
#include "hardware/tiva_aux_sysif.h"
#include "cc13xx/cc13x2_aux_sysif.h"
/*****************************************************************************
* Private Data
*****************************************************************************/
/* Used in aux_sysif_opmode() to control the change of the operational mode. */
static const uint8_t g_opmode_to_order[4] =
{
1, 2, 0, 3
};
static const uint8_t g_order_to_opmode[4] =
{
2, 0, 1, 3
};
/*****************************************************************************
* Public Functions
*****************************************************************************/
/************************************************************************************
* Name: aux_sysif_opmode
*
* Description:
*
* This function controls the change of the AUX operational mode.
* The function controls the change of the current operational mode to the
* operational mode target by adhering to rules specified by HW.
*
* Input Parameters:
* - opmode: AUX operational mode. One of
* AUX_SYSIF_OPMODE_TARGET_PDLP: Power down operational mode with wakeup
* to low power mode)
* AUX_SYSIF_OPMODE_TARGET_PDA: Power down operational mode with wakeup
to active mode
* AUX_SYSIF_OPMODE_TARGET_LP: Low power operational mode)
* AUX_SYSIF_OPMODE_TARGET_A: Active operational mode
*
* Returned Value:
* None
*
************************************************************************************/
void aux_sysif_opmode(uint32_t opmode)
{
uint32_t currmode;
uint32_t currorder;
uint32_t nextmode;
do
{
currmode = getreg32(TIVA_AUX_SYSIF_OPMODEREQ);
while (currmode != getreg32(TIVA_AUX_SYSIF_OPMODEACK))
{
}
if (currmode != opmode)
{
currorder = g_opmode_to_order[currmode];
if (currorder < g_opmode_to_order[opmode])
{
nextmode = g_order_to_opmode[currorder + 1];
}
else
{
nextmode = g_order_to_opmode[currorder - 1];
}
putreg32(nextmode, TIVA_AUX_SYSIF_OPMODEREQ);
}
}
while (currmode != opmode);
}

89
arch/arm/src/tiva/cc13xx/cc13x2_aux_sysif.h Normal file
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@ -0,0 +1,89 @@
/************************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x2_aux_sysif.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* This is a port of TI's aux_sysif.h file which has a fully compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_AUX_SYSIF_H
#define __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_AUX_SYSIF_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <stdint.h>
#include "hardware/tiva_aux_sysif.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#define AUX_SYSIF_OPMODE_TARGET_PDLP AUX_SYSIF_OPMODEREQ_REQ_PDLP
#define AUX_SYSIF_OPMODE_TARGET_PDA AUX_SYSIF_OPMODEREQ_REQ_PDA
#define AUX_SYSIF_OPMODE_TARGET_LP AUX_SYSIF_OPMODEREQ_REQ_LP
#define AUX_SYSIF_OPMODE_TARGET_A AUX_SYSIF_OPMODEREQ_REQ_A
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: aux_sysif_opmode
*
* Description:
*
* This function controls the change of the AUX operational mode.
* The function controls the change of the current operational mode to the
* operational mode target by adhering to rules specified by HW.
*
* Input Parameters:
* - opmode: AUX operational mode. One of
* AUX_SYSIF_OPMODE_TARGET_PDLP: Power down operational mode with wakeup
* to low power mode)
* AUX_SYSIF_OPMODE_TARGET_PDA: Power down operational mode with wakeup
to active mode
* AUX_SYSIF_OPMODE_TARGET_LP: Low power operational mode)
* AUX_SYSIF_OPMODE_TARGET_A: Active operational mode
*
* Returned Value:
* None
*
************************************************************************************/
void aux_sysif_opmode(uint32_t opmode);
#endif /* __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_AUX_SYSIF_H */

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arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h Normal file
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@ -0,0 +1,895 @@
/************************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x2_cc26xx2_v1_rom.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* This is a port of TI's rom.h file which has a fully compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_CC26X2_V1_ROM_H
#define __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_CC26X2_V1_ROM_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Start address of the ROM hard API access table (located after the ROM FW rev field) */
#define ROM_HAPI_TABLE_ADDR 0x10000048
/* Pointer to the ROM HAPI table */
#define P_HARD_API ((hard_api_t *)ROM_HAPI_TABLE_ADDR)
#define hapi_crc32(a,b,c) P_HARD_API->crc32(a,b,c)
#define hapi_get_flashsize() P_HARD_API->get_flashsize()
#define hapi_get_chipid() P_HARD_API->get_chipid()
#define hapi_reset_device() P_HARD_API->reset_device()
#define hapi_fletcher32(a,b,c) P_HARD_API->fletcher32(a,b,c)
#define hapi_min(a,b) P_HARD_API->min(a,b)
#define hapi_max(a,b) P_HARD_API->max(a,b)
#define hapi_mean(a,b) P_HARD_API->mean(a,b)
#define hapi_standard_devation(a,b) P_HARD_API->standard_devation(a,b)
#define hapi_source_safeswitch() P_HARD_API->hf_source_safeswitch()
#define hapi_select_compa_input(a) P_HARD_API->select_compa_input(a)
#define hapi_select_compa_ref(a) P_HARD_API->select_compa_ref(a)
#define hapi_select_adc_compb_input(a) P_HARD_API->select_adc_compb_input(a)
#define hapi_select_dac_vref(a) P_HARD_API->select_dac_vref(a)
/* Defines for input parameter to the hapi_select_compa_input function.
* The define values can not be changed!
*/
#define COMPA_IN_NC 0x00
#define COMPA_IN_AUXIO7 0x09
#define COMPA_IN_AUXIO6 0x0a
#define COMPA_IN_AUXIO5 0x0b
#define COMPA_IN_AUXIO4 0x0c
#define COMPA_IN_AUXIO3 0x0d
#define COMPA_IN_AUXIO2 0x0e
#define COMPA_IN_AUXIO1 0x0f
#define COMPA_IN_AUXIO0 0x10
/* Defines for input parameter to the hapi_select_compa_ref function.
* The define values can not be changed!
*/
#define COMPA_REF_NC 0x00
#define COMPA_REF_DCOUPL 0x01
#define COMPA_REF_VSS 0x02
#define COMPA_REF_VDDS 0x03
#define COMPA_REF_ADCVREFP 0x04
#define COMPA_REF_AUXIO7 0x09
#define COMPA_REF_AUXIO6 0x0a
#define COMPA_REF_AUXIO5 0x0b
#define COMPA_REF_AUXIO4 0x0c
#define COMPA_REF_AUXIO3 0x0d
#define COMPA_REF_AUXIO2 0x0e
#define COMPA_REF_AUXIO1 0x0f
#define COMPA_REF_AUXIO0 0x10
/* Defines for input parameter to the hapi_select_adc_compb_input function.
* The define values can not be changed!
*/
#define ADC_COMPB_IN_NC 0x00
#define ADC_COMPB_IN_DCOUPL 0x03
#define ADC_COMPB_IN_VSS 0x04
#define ADC_COMPB_IN_VDDS 0x05
#define ADC_COMPB_IN_AUXIO7 0x09
#define ADC_COMPB_IN_AUXIO6 0x0a
#define ADC_COMPB_IN_AUXIO5 0x0b
#define ADC_COMPB_IN_AUXIO4 0x0c
#define ADC_COMPB_IN_AUXIO3 0x0d
#define ADC_COMPB_IN_AUXIO2 0x0e
#define ADC_COMPB_IN_AUXIO1 0x0f
#define ADC_COMPB_IN_AUXIO0 0x10
/* Defines for input parameter to the hapi_select_dac_vref function.
* The define values can not be changed!
*/
#define DAC_REF_NC 0x00
#define DAC_REF_DCOUPL 0x01
#define DAC_REF_VSS 0x02
#define DAC_REF_VDDS 0x03
/* Pointers to the main API tables */
#define ROM_API_TABLE ((uint32_t *) 0x10000180)
#define ROM_VERSION (ROM_API_TABLE[0])
#define ROM_API_AON_EVENT_TABLE ((uint32_t *)(ROM_API_TABLE[1]))
#define ROM_API_AON_IOC_TABLE ((uint32_t *)(ROM_API_TABLE[2]))
#define ROM_API_AON_RTC_TABLE ((uint32_t *)(ROM_API_TABLE[3]))
#define ROM_API_AUX_CTRL_TABLE ((uint32_t *)(ROM_API_TABLE[5]))
#define ROM_API_AUX_TDC_TABLE ((uint32_t *)(ROM_API_TABLE[6]))
#define ROM_API_DDI_TABLE ((uint32_t *)(ROM_API_TABLE[9]))
#define ROM_API_FLASH_TABLE ((uint32_t *)(ROM_API_TABLE[10]))
#define ROM_API_I2C_TABLE ((uint32_t *)(ROM_API_TABLE[11]))
#define ROM_API_INTERRUPT_TABLE ((uint32_t *)(ROM_API_TABLE[12]))
#define ROM_API_IOC_TABLE ((uint32_t *)(ROM_API_TABLE[13]))
#define ROM_API_PRCM_TABLE ((uint32_t *)(ROM_API_TABLE[14]))
#define ROM_API_SMPH_TABLE ((uint32_t *)(ROM_API_TABLE[15]))
#define ROM_API_SSI_TABLE ((uint32_t *)(ROM_API_TABLE[17]))
#define ROM_API_TIMER_TABLE ((uint32_t *)(ROM_API_TABLE[18]))
#define ROM_API_TRNG_TABLE ((uint32_t *)(ROM_API_TABLE[19]))
#define ROM_API_UART_TABLE ((uint32_t *)(ROM_API_TABLE[20]))
#define ROM_API_UDMA_TABLE ((uint32_t *)(ROM_API_TABLE[21]))
#define ROM_API_VIMS_TABLE ((uint32_t *)(ROM_API_TABLE[22]))
#define ROM_API_CRYPTO_TABLE ((uint32_t *)(ROM_API_TABLE[23]))
#define ROM_API_OSC_TABLE ((uint32_t *)(ROM_API_TABLE[24]))
#define ROM_API_AUX_ADC_TABLE ((uint32_t *)(ROM_API_TABLE[25]))
#define ROM_API_SYS_CTRL_TABLE ((uint32_t *)(ROM_API_TABLE[26]))
#define ROM_API_AON_BATMON_TABLE ((uint32_t *)(ROM_API_TABLE[27]))
#define ROM_API_SETUP_ROM_TABLE ((uint32_t *)(ROM_API_TABLE[28]))
#define ROM_API_I2S_TABLE ((uint32_t *)(ROM_API_TABLE[29]))
#define ROM_API_PWR_CTRL_TABLE ((uint32_t *)(ROM_API_TABLE[30]))
/* AON_EVENT FUNCTIONS */
#define ROM_AONEventMcuWakeUpSet \
((void (*)(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)) \
ROM_API_AON_EVENT_TABLE[0])
#define ROM_AONEventMcuWakeUpGet \
((uint32_t (*)(uint32_t ui32MCUWUEvent)) \
ROM_API_AON_EVENT_TABLE[1])
#define ROM_AONEventMcuSet \
((void (*)(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)) \
ROM_API_AON_EVENT_TABLE[4])
#define ROM_AONEventMcuGet \
((uint32_t (*)(uint32_t ui32MCUEvent)) \
ROM_API_AON_EVENT_TABLE[5])
/* AON_RTC FUNCTIONS */
#define ROM_AONRTCCurrent64BitValueGet \
((uint64_t (*)(void)) \
ROM_API_AON_RTC_TABLE[12])
/* AUX_TDC FUNCTIONS */
#define ROM_AUXTDCConfigSet \
((void (*)(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition)) \
ROM_API_AUX_TDC_TABLE[0])
#define ROM_AUXTDCMeasurementDone \
((uint32_t (*)(uint32_t ui32Base)) \
ROM_API_AUX_TDC_TABLE[1])
/* DDI FUNCTIONS */
#define ROM_DDI16BitWrite \
((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData)) \
ROM_API_DDI_TABLE[0])
#define ROM_DDI16BitfieldWrite \
((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)) \
ROM_API_DDI_TABLE[1])
#define ROM_DDI16BitRead \
((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)) \
ROM_API_DDI_TABLE[2])
#define ROM_DDI16BitfieldRead \
((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift)) \
ROM_API_DDI_TABLE[3])
#define ROM_DDI32RegWrite \
((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)) \
ROM_API_DDI_TABLE[4])
/* FLASH FUNCTIONS */
#define ROM_FlashPowerModeSet \
((void (*)(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, uint32_t ui32PumpGracePeriod)) \
ROM_API_FLASH_TABLE[0])
#define ROM_FlashPowerModeGet \
((uint32_t (*)(void)) \
ROM_API_FLASH_TABLE[1])
#define ROM_FlashProtectionSet \
((void (*)(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)) \
ROM_API_FLASH_TABLE[2])
#define ROM_FlashProtectionGet \
((uint32_t (*)(uint32_t ui32SectorAddress)) \
ROM_API_FLASH_TABLE[3])
#define ROM_FlashProtectionSave \
((uint32_t (*)(uint32_t ui32SectorAddress)) \
ROM_API_FLASH_TABLE[4])
#define ROM_FlashEfuseReadRow \
((bool (*)(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)) \
ROM_API_FLASH_TABLE[8])
#define ROM_FlashDisableSectorsForWrite \
((void (*)(void)) \
ROM_API_FLASH_TABLE[9])
/* I2C FUNCTIONS */
#define ROM_I2CMasterInitExpClk \
((void (*)(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)) \
ROM_API_I2C_TABLE[0])
#define ROM_I2CMasterErr \
((uint32_t (*)(uint32_t ui32Base)) \
ROM_API_I2C_TABLE[1])
/* INTERRUPT FUNCTIONS */
#define ROM_IntPriorityGroupingSet \
((void (*)(uint32_t ui32Bits)) \
ROM_API_INTERRUPT_TABLE[0])
#define ROM_IntPriorityGroupingGet \
((uint32_t (*)(void)) \
ROM_API_INTERRUPT_TABLE[1])
#define ROM_IntPrioritySet \
((void (*)(uint32_t ui32Interrupt, uint8_t ui8Priority)) \
ROM_API_INTERRUPT_TABLE[2])
#define ROM_IntPriorityGet \
((int32_t (*)(uint32_t ui32Interrupt)) \
ROM_API_INTERRUPT_TABLE[3])
#define ROM_IntEnable \
((void (*)(uint32_t ui32Interrupt)) \
ROM_API_INTERRUPT_TABLE[4])
#define ROM_IntDisable \
((void (*)(uint32_t ui32Interrupt)) \
ROM_API_INTERRUPT_TABLE[5])
#define ROM_IntPendSet \
((void (*)(uint32_t ui32Interrupt)) \
ROM_API_INTERRUPT_TABLE[6])
#define ROM_IntPendGet \
((bool (*)(uint32_t ui32Interrupt)) \
ROM_API_INTERRUPT_TABLE[7])
#define ROM_IntPendClear \
((void (*)(uint32_t ui32Interrupt)) \
ROM_API_INTERRUPT_TABLE[8])
/* IOC FUNCTIONS */
#define ROM_IOCPortConfigureSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)) \
ROM_API_IOC_TABLE[0])
#define ROM_IOCPortConfigureGet \
((uint32_t (*)(uint32_t ui32IOId)) \
ROM_API_IOC_TABLE[1])
#define ROM_IOCIOShutdownSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32IOShutdown)) \
ROM_API_IOC_TABLE[2])
#define ROM_IOCIOModeSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32IOMode)) \
ROM_API_IOC_TABLE[4])
#define ROM_IOCIOIntSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)) \
ROM_API_IOC_TABLE[5])
#define ROM_IOCIOPortPullSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32Pull)) \
ROM_API_IOC_TABLE[6])
#define ROM_IOCIOHystSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32Hysteresis)) \
ROM_API_IOC_TABLE[7])
#define ROM_IOCIOInputSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32Input)) \
ROM_API_IOC_TABLE[8])
#define ROM_IOCIOSlewCtrlSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32SlewEnable)) \
ROM_API_IOC_TABLE[9])
#define ROM_IOCIODrvStrengthSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength)) \
ROM_API_IOC_TABLE[10])
#define ROM_IOCIOPortIdSet \
((void (*)(uint32_t ui32IOId, uint32_t ui32PortId)) \
ROM_API_IOC_TABLE[11])
#define ROM_IOCIntEnable \
((void (*)(uint32_t ui32IOId)) \
ROM_API_IOC_TABLE[12])
#define ROM_IOCIntDisable \
((void (*)(uint32_t ui32IOId)) \
ROM_API_IOC_TABLE[13])
#define ROM_IOCPinTypeGpioInput \
((void (*)(uint32_t ui32IOId)) \
ROM_API_IOC_TABLE[14])
#define ROM_IOCPinTypeGpioOutput \
((void (*)(uint32_t ui32IOId)) \
ROM_API_IOC_TABLE[15])
#define ROM_IOCPinTypeUart \
((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts)) \
ROM_API_IOC_TABLE[16])
#define ROM_IOCPinTypeSsiMaster \
((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \
ROM_API_IOC_TABLE[17])
#define ROM_IOCPinTypeSsiSlave \
((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \
ROM_API_IOC_TABLE[18])
#define ROM_IOCPinTypeI2c \
((void (*)(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)) \
ROM_API_IOC_TABLE[19])
#define ROM_IOCPinTypeAux \
((void (*)(uint32_t ui32IOId)) \
ROM_API_IOC_TABLE[21])
/* PRCM FUNCTIONS */
#define ROM_PRCMInfClockConfigureSet \
((void (*)(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)) \
ROM_API_PRCM_TABLE[0])
#define ROM_PRCMInfClockConfigureGet \
((uint32_t (*)(uint32_t ui32PowerMode)) \
ROM_API_PRCM_TABLE[1])
#define ROM_PRCMAudioClockConfigSet \
((void (*)(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)) \
ROM_API_PRCM_TABLE[4])
#define ROM_PRCMPowerDomainOn \
((void (*)(uint32_t ui32Domains)) \
ROM_API_PRCM_TABLE[5])
#define ROM_PRCMPowerDomainOff \
((void (*)(uint32_t ui32Domains)) \
ROM_API_PRCM_TABLE[6])
#define ROM_PRCMPeripheralRunEnable \
((void (*)(uint32_t ui32Peripheral)) \
ROM_API_PRCM_TABLE[7])
#define ROM_PRCMPeripheralRunDisable \
((void (*)(uint32_t ui32Peripheral)) \
ROM_API_PRCM_TABLE[8])
#define ROM_PRCMPeripheralSleepEnable \
((void (*)(uint32_t ui32Peripheral)) \
ROM_API_PRCM_TABLE[9])
#define ROM_PRCMPeripheralSleepDisable \
((void (*)(uint32_t ui32Peripheral)) \
ROM_API_PRCM_TABLE[10])
#define ROM_PRCMPeripheralDeepSleepEnable \
((void (*)(uint32_t ui32Peripheral)) \
ROM_API_PRCM_TABLE[11])
#define ROM_PRCMPeripheralDeepSleepDisable \
((void (*)(uint32_t ui32Peripheral)) \
ROM_API_PRCM_TABLE[12])
#define ROM_PRCMPowerDomainStatus \
((uint32_t (*)(uint32_t ui32Domains)) \
ROM_API_PRCM_TABLE[13])
#define ROM_PRCMDeepSleep \
((void (*)(void)) \
ROM_API_PRCM_TABLE[14])
#define ROM_PRCMAudioClockConfigSetOverride \
((void (*)(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, uint32_t ui32BitDiv, uint32_t ui32WordDiv)) \
ROM_API_PRCM_TABLE[17])
/* SMPH FUNCTIONS */
#define ROM_SMPHAcquire \
((void (*)(uint32_t ui32Semaphore)) \
ROM_API_SMPH_TABLE[0])
/* SSI FUNCTIONS */
#define ROM_SSIConfigSetExpClk \
((void (*)(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth)) \
ROM_API_SSI_TABLE[0])
#define ROM_SSIDataPut \
((void (*)(uint32_t ui32Base, uint32_t ui32Data)) \
ROM_API_SSI_TABLE[1])
#define ROM_SSIDataPutNonBlocking \
((int32_t (*)(uint32_t ui32Base, uint32_t ui32Data)) \
ROM_API_SSI_TABLE[2])
#define ROM_SSIDataGet \
((void (*)(uint32_t ui32Base, uint32_t *pui32Data)) \
ROM_API_SSI_TABLE[3])
#define ROM_SSIDataGetNonBlocking \
((int32_t (*)(uint32_t ui32Base, uint32_t *pui32Data)) \
ROM_API_SSI_TABLE[4])
/* TIMER FUNCTIONS */
#define ROM_TimerConfigure \
((void (*)(uint32_t ui32Base, uint32_t ui32Config)) \
ROM_API_TIMER_TABLE[0])
#define ROM_TimerLevelControl \
((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)) \
ROM_API_TIMER_TABLE[1])
#define ROM_TimerStallControl \
((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)) \
ROM_API_TIMER_TABLE[3])
#define ROM_TimerWaitOnTriggerControl \
((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)) \
ROM_API_TIMER_TABLE[4])
#define ROM_TimerIntervalLoadMode \
((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \
ROM_API_TIMER_TABLE[5])
#define ROM_TimerMatchUpdateMode \
((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \
ROM_API_TIMER_TABLE[6])
/* TRNG FUNCTIONS */
#define ROM_TRNGConfigure \
((void (*)(uint32_t ui32MinSamplesPerCycle, uint32_t ui32MaxSamplesPerCycle, uint32_t ui32ClocksPerSample)) \
ROM_API_TRNG_TABLE[0])
#define ROM_TRNGNumberGet \
((uint32_t (*)(uint32_t ui32Word)) \
ROM_API_TRNG_TABLE[1])
/* UART FUNCTIONS */
#define ROM_UARTFIFOLevelGet \
((void (*)(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel)) \
ROM_API_UART_TABLE[0])
#define ROM_UARTConfigSetExpClk \
((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config)) \
ROM_API_UART_TABLE[1])
#define ROM_UARTConfigGetExpClk \
((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config)) \
ROM_API_UART_TABLE[2])
#define ROM_UARTDisable \
((void (*)(uint32_t ui32Base)) \
ROM_API_UART_TABLE[3])
#define ROM_UARTCharGetNonBlocking \
((int32_t (*)(uint32_t ui32Base)) \
ROM_API_UART_TABLE[4])
#define ROM_UARTCharGet \
((int32_t (*)(uint32_t ui32Base)) \
ROM_API_UART_TABLE[5])
#define ROM_UARTCharPutNonBlocking \
((bool (*)(uint32_t ui32Base, uint8_t ui8Data)) \
ROM_API_UART_TABLE[6])
#define ROM_UARTCharPut \
((void (*)(uint32_t ui32Base, uint8_t ui8Data)) \
ROM_API_UART_TABLE[7])
/* UDMA FUNCTIONS */
#define ROM_uDMAChannelAttributeEnable \
((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \
ROM_API_UDMA_TABLE[0])
#define ROM_uDMAChannelAttributeDisable \
((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \
ROM_API_UDMA_TABLE[1])
#define ROM_uDMAChannelAttributeGet \
((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \
ROM_API_UDMA_TABLE[2])
#define ROM_uDMAChannelControlSet \
((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control)) \
ROM_API_UDMA_TABLE[3])
#define ROM_uDMAChannelTransferSet \
((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, uint32_t ui32TransferSize)) \
ROM_API_UDMA_TABLE[4])
#define ROM_uDMAChannelScatterGatherSet \
((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)) \
ROM_API_UDMA_TABLE[5])
#define ROM_uDMAChannelSizeGet \
((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \
ROM_API_UDMA_TABLE[6])
#define ROM_uDMAChannelModeGet \
((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \
ROM_API_UDMA_TABLE[7])
/* VIMS FUNCTIONS */
#define ROM_VIMSConfigure \
((void (*)(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)) \
ROM_API_VIMS_TABLE[0])
#define ROM_VIMSModeSet \
((void (*)(uint32_t ui32Base, uint32_t ui32Mode)) \
ROM_API_VIMS_TABLE[1])
#define ROM_VIMSModeGet \
((uint32_t (*)(uint32_t ui32Base)) \
ROM_API_VIMS_TABLE[2])
#define ROM_VIMSModeSafeSet \
((void (*)(uint32_t ui32Base, uint32_t ui32NewMode, bool blocking)) \
ROM_API_VIMS_TABLE[3])
/* CRYPTO FUNCTIONS */
#define ROM_CRYPTOAesEcb \
((uint32_t (*)(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32KeyLocation, bool bEncrypt, bool bIntEnable)) \
ROM_API_CRYPTO_TABLE[0])
#define ROM_CRYPTOAesEcbStatus \
((uint32_t (*)(void)) \
ROM_API_CRYPTO_TABLE[1])
#define ROM_CRYPTOCcmAuthEncrypt \
((uint32_t (*)(bool bEncrypt, uint32_t ui32AuthLength, uint32_t *pui32Nonce, uint32_t *pui32PlainText, uint32_t ui32PlainTextLength, uint32_t *pui32Header, uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, uint32_t ui32FieldLength, bool bIntEnable)) \
ROM_API_CRYPTO_TABLE[3])
#define ROM_CRYPTOCcmAuthEncryptResultGet \
((uint32_t (*)(uint32_t ui32TagLength, uint32_t *pui32CcmTag)) \
ROM_API_CRYPTO_TABLE[4])
#define ROM_CRYPTOCcmAuthEncryptStatus \
((uint32_t (*)(void)) \
ROM_API_CRYPTO_TABLE[5])
#define ROM_CRYPTOCcmInvAuthDecrypt \
((uint32_t (*)(bool bDecrypt, uint32_t ui32AuthLength, uint32_t *pui32Nonce, uint32_t *pui32CipherText, uint32_t ui32CipherTextLength, uint32_t *pui32Header, uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, uint32_t ui32FieldLength, bool bIntEnable)) \
ROM_API_CRYPTO_TABLE[6])
#define ROM_CRYPTOCcmInvAuthDecryptResultGet \
((uint32_t (*)(uint32_t ui32AuthLength, uint32_t *pui32CipherText, uint32_t ui32CipherTextLength, uint32_t *pui32CcmTag)) \
ROM_API_CRYPTO_TABLE[7])
#define ROM_CRYPTOCcmInvAuthDecryptStatus \
((uint32_t (*)(void)) \
ROM_API_CRYPTO_TABLE[8])
#define ROM_CRYPTOAesCbc \
((uint32_t (*)(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32MsgLength, uint32_t *pui32Nonce, uint32_t ui32KeyLocation, bool bEncrypt, bool bIntEnable)) \
ROM_API_CRYPTO_TABLE[9])
#define ROM_CRYPTOAesCbcStatus \
((uint32_t (*)(void)) \
ROM_API_CRYPTO_TABLE[10])
#define ROM_CRYPTODmaDisable \
((void (*)(uint32_t ui32Channels)) \
ROM_API_CRYPTO_TABLE[11])
#define ROM_CRYPTODmaEnable \
((void (*)(uint32_t ui32Channels)) \
ROM_API_CRYPTO_TABLE[12])
/* OSC FUNCTIONS */
#define ROM_OSCClockSourceGet \
((uint32_t (*)(uint32_t ui32SrcClk)) \
ROM_API_OSC_TABLE[0])
#define ROM_OSCClockSourceSet \
((void (*)(uint32_t ui32SrcClk, uint32_t ui32Osc)) \
ROM_API_OSC_TABLE[1])
#define ROM_OSC_HPOSCRelativeFrequencyOffsetGet \
((int32_t (*)(int32_t tempDegC)) \
ROM_API_OSC_TABLE[2])
#define ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert \
((int16_t (*)(int32_t HPOSC_RelFreqOffset)) \
ROM_API_OSC_TABLE[3])
/* AUX_ADC FUNCTIONS */
#define ROM_AUXADCAdjustValueForGainAndOffset \
((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \
ROM_API_AUX_ADC_TABLE[0])
#define ROM_AUXADCDisable \
((void (*)(void)) \
ROM_API_AUX_ADC_TABLE[1])
#define ROM_AUXADCDisableInputScaling \
((void (*)(void)) \
ROM_API_AUX_ADC_TABLE[2])
#define ROM_AUXADCEnableAsync \
((void (*)(uint32_t refSource, uint32_t trigger)) \
ROM_API_AUX_ADC_TABLE[3])
#define ROM_AUXADCEnableSync \
((void (*)(uint32_t refSource, uint32_t sampleTime, uint32_t trigger)) \
ROM_API_AUX_ADC_TABLE[4])
#define ROM_AUXADCFlushFifo \
((void (*)(void)) \
ROM_API_AUX_ADC_TABLE[5])
#define ROM_AUXADCGetAdjustmentGain \
((int32_t (*)(uint32_t refSource)) \
ROM_API_AUX_ADC_TABLE[6])
#define ROM_AUXADCGetAdjustmentOffset \
((int32_t (*)(uint32_t refSource)) \
ROM_API_AUX_ADC_TABLE[7])
#define ROM_AUXADCMicrovoltsToValue \
((int32_t (*)(int32_t fixedRefVoltage, int32_t microvolts)) \
ROM_API_AUX_ADC_TABLE[8])
#define ROM_AUXADCPopFifo \
((uint32_t (*)(void)) \
ROM_API_AUX_ADC_TABLE[9])
#define ROM_AUXADCReadFifo \
((uint32_t (*)(void)) \
ROM_API_AUX_ADC_TABLE[10])
#define ROM_AUXADCUnadjustValueForGainAndOffset \
((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \
ROM_API_AUX_ADC_TABLE[11])
#define ROM_AUXADCValueToMicrovolts \
((int32_t (*)(int32_t fixedRefVoltage, int32_t adcValue)) \
ROM_API_AUX_ADC_TABLE[12])
/* SYS_CTRL FUNCTIONS */
#define ROM_SysCtrlResetSourceGet \
((uint32_t (*)(void)) \
ROM_API_SYS_CTRL_TABLE[0])
#define ROM_SysCtrl_DCDC_VoltageConditionalControl \
((void (*)(void)) \
ROM_API_SYS_CTRL_TABLE[1])
/* AON_BATMON FUNCTIONS */
#define ROM_AONBatMonTemperatureGetDegC \
((int32_t (*)(void)) \
ROM_API_AON_BATMON_TABLE[0])
/* SETUP_ROM FUNCTIONS */
#define ROM_SetupAfterColdResetWakeupFromShutDownCfg2 \
((void (*)(uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg)) \
ROM_API_SETUP_ROM_TABLE[1])
#define ROM_SetupAfterColdResetWakeupFromShutDownCfg3 \
((void (*)(uint32_t ccfg_ModeConfReg)) \
ROM_API_SETUP_ROM_TABLE[2])
#define ROM_SetupGetTrimForAdcShModeEn \
((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
ROM_API_SETUP_ROM_TABLE[3])
#define ROM_SetupGetTrimForAdcShVbufEn \
((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
ROM_API_SETUP_ROM_TABLE[4])
#define ROM_SetupGetTrimForAmpcompCtrl \
((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
ROM_API_SETUP_ROM_TABLE[5])
#define ROM_SetupGetTrimForAmpcompTh1 \
((uint32_t (*)(void)) \
ROM_API_SETUP_ROM_TABLE[6])
#define ROM_SetupGetTrimForAmpcompTh2 \
((uint32_t (*)(void)) \
ROM_API_SETUP_ROM_TABLE[7])
#define ROM_SetupGetTrimForAnabypassValue1 \
((uint32_t (*)(uint32_t ccfg_ModeConfReg)) \
ROM_API_SETUP_ROM_TABLE[8])
#define ROM_SetupGetTrimForDblrLoopFilterResetVoltage \
((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
ROM_API_SETUP_ROM_TABLE[9])
#define ROM_SetupGetTrimForRadcExtCfg \
((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
ROM_API_SETUP_ROM_TABLE[10])
#define ROM_SetupGetTrimForRcOscLfIBiasTrim \
((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
ROM_API_SETUP_ROM_TABLE[11])
#define ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim \
((uint32_t (*)(void)) \
ROM_API_SETUP_ROM_TABLE[12])
#define ROM_SetupGetTrimForXoscHfCtl \
((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
ROM_API_SETUP_ROM_TABLE[13])
#define ROM_SetupGetTrimForXoscHfFastStart \
((uint32_t (*)(void)) \
ROM_API_SETUP_ROM_TABLE[14])
#define ROM_SetupGetTrimForXoscHfIbiastherm \
((uint32_t (*)(void)) \
ROM_API_SETUP_ROM_TABLE[15])
#define ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio \
((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
ROM_API_SETUP_ROM_TABLE[16])
#define ROM_SetupSetAonRtcSubSecInc \
((void (*)(uint32_t subSecInc)) \
ROM_API_SETUP_ROM_TABLE[17])
#define ROM_SetupSetCacheModeAccordingToCcfgSetting \
((void (*)(void)) \
ROM_API_SETUP_ROM_TABLE[18])
/* I2S FUNCTIONS */
#define ROM_I2SPointerSet \
((void (*)(uint32_t ui32Base, bool bInput, void * pNextPointer)) \
ROM_API_I2S_TABLE[0])
#define ROM_I2SSampleStampGet \
((uint32_t (*)(uint32_t ui32Base, uint32_t ui32Channel)) \
ROM_API_I2S_TABLE[1])
/* PWR_CTRL FUNCTIONS */
#define ROM_PowerCtrlSourceSet \
((void (*)(uint32_t ui32PowerConfig)) \
ROM_API_PWR_CTRL_TABLE[0])
/************************************************************************************
* Public Types
************************************************************************************/
/* ROM Hard-API function interface types */
typedef uint32_t (*fptr_crc32_t) (uint8_t * /* data */,\
uint32_t /* bytecount */,\
uint32_t /* repeatcount */);
typedef uint32_t (*fptr_getflsize_t) (void);
typedef uint32_t (*fptr_getchipid_t) (void);
typedef uint32_t (*fptr_reserved1_t) (uint32_t);
typedef uint32_t (*fptr_reserved2_t) (void);
typedef uint32_t (*fptr_reserved3_t) (uint8_t *,\
uint32_t,\
uint32_t);
typedef void (*fptr_resetdev_t) (void);
typedef uint32_t (*fptr_fletcher32_t) (uint16_t * /* data */,\
uint16_t /* wordcount */,\
uint16_t /* repeatcount */);
typedef uint32_t (*fptr_minval_t) (uint32_t * /* data */,\
uint32_t /* count */);
typedef uint32_t (*fptr_maxval_t) (uint32_t * /* buffer */,\
uint32_t /* count */);
typedef uint32_t (*fptr_meanval_t) (uint32_t * /* buffer */,\
uint32_t /* count */);
typedef uint32_t (*fptr_stddval_t) (uint32_t * /* buffer */,\
uint32_t /* count */);
typedef void (*fptr_hfsourcesafeswitch_t) (void);
typedef void (*fptr_reserved4_t) (uint32_t);
typedef void (*fptr_reserved5_t) (uint32_t);
typedef void (*fptr_compain_t) (uint8_t /* signal */);
typedef void (*fptr_comparef_t) (uint8_t /* signal */);
typedef void (*fptr_adccompbin_t) (uint8_t /* signal */);
typedef void (*fptr_dacvref_t) (uint8_t /* signal */);
/* ROM Hard-API access table type */
struct hard_api_s
{
fptr_crc32_t crc32;
fptr_getflsize_t FlashGetSize;
fptr_getchipid_t get_chipid;
fptr_reserved1_t reserved1;
fptr_reserved2_t reserved2;
fptr_reserved3_t reserved3;
fptr_resetdev_t reset_device;
fptr_fletcher32_t fletcher32;
fptr_minval_t min;
fptr_maxval_t max;
fptr_meanval_t mean;
fptr_stddval_t standard_devation;
fptr_reserved4_t reserved4;
fptr_reserved5_t reserved5;
fptr_hfsourcesafeswitch_t hf_source_safeswitch;
fptr_compain_t select_compa_input;
fptr_comparef_t select_compa_ref;
fptr_adccompbin_t select_adc_compb_input;
fptr_dacvref_t select_dac_vref;
};
typedef struct hard_api_s hard_api_t;
#endif /* __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_CC26X2_V1_ROM_H */

1017
arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h Normal file
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File diff suppressed because it is too large Load Diff

5
arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c
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@ -57,6 +57,9 @@
#include "hardware/tiva_prcm.h"
#include "hardware/tiva_vims.h"
#include "cc13xx/cc13x2_cc26x2_v1_rom.h"
#include "cc13xx/cc13x2_aux_sysif.h"
/******************************************************************************
* Pre-processor Definitions
******************************************************************************/
@ -459,7 +462,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
/* Set AUX into power down active mode */
AUXSYSIFOpModeChange(AUX_SYSIF_OPMODE_TARGET_PDA);
aux_sysif_opmode(AUX_SYSIF_OPMODE_TARGET_PDA);
/* Disable EFUSE clock */

5
arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c
View File

@ -55,6 +55,9 @@
#include "hardware/tiva_prcm.h"
#include "hardware/tiva_vims.h"
#include "cc13xx/cc13x2_cc26x2_v2_rom.h"
#include "cc13xx/cc13x2_aux_sysif.h"
/******************************************************************************
* Private Functions
******************************************************************************/
@ -203,7 +206,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
/* Set AUX into power down active mode */
AUXSYSIFOpModeChange(AUX_SYSIF_OPMODE_TARGET_PDA);
aux_sysif_opmode(AUX_SYSIF_OPMODE_TARGET_PDA);
/* Disable EFUSE clock */

2
arch/arm/src/tiva/cc13xx/cc13xx_chipinfo.c
View File

@ -4,7 +4,7 @@
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD
* Technical content derives from a TI file that has a compatible BSD
* license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated

781
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_sysif.h Normal file
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@ -0,0 +1,781 @@
/********************************************************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_sysif.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AUX_SYSIF_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AUX_SYSIF_H
/********************************************************************************************************************
* Included Files
********************************************************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/********************************************************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
/* AUX SYSIF Register Offsets ***************************************************************************************/
#define TIVA_AUX_SYSIF_OPMODEREQ_OFFSET 0x0000 /* Operational Mode Request */
#define TIVA_AUX_SYSIF_OPMODEACK_OFFSET 0x0004 /* Operational Mode Acknowledgement */
#define TIVA_AUX_SYSIF_PROGWU0CFG_OFFSET 0x0008 /* Programmable Wakeup 0 Configuration */
#define TIVA_AUX_SYSIF_PROGWU1CFG_OFFSET 0x000c /* Programmable Wakeup 1 Configuration */
#define TIVA_AUX_SYSIF_PROGWU2CFG_OFFSET 0x0010 /* Programmable Wakeup 2 Configuration */
#define TIVA_AUX_SYSIF_PROGWU3CFG_OFFSET 0x0014 /* Programmable Wakeup 3 Configuration */
#define TIVA_AUX_SYSIF_SWWUTRIG_OFFSET 0x0018 /* Software Wakeup Triggers */
#define TIVA_AUX_SYSIF_WUFLAGS_OFFSET 0x001c /* Wakeup Flags */
#define TIVA_AUX_SYSIF_WUFLAGSCLR_OFFSET 0x0020 /* Wakeup Flags Clear */
#define TIVA_AUX_SYSIF_WUGATE_OFFSET 0x0024 /* Wakeup Gate */
#define TIVA_AUX_SYSIF_VECCFG0_OFFSET 0x0028 /* Vector Configuration 0 */
#define TIVA_AUX_SYSIF_VECCFG1_OFFSET 0x002c /* Vector Configuration 1 */
#define TIVA_AUX_SYSIF_VECCFG2_OFFSET 0x0030 /* Vector Configuration 2 */
#define TIVA_AUX_SYSIF_VECCFG3_OFFSET 0x0034 /* Vector Configuration 3 */
#define TIVA_AUX_SYSIF_VECCFG4_OFFSET 0x0038 /* Vector Configuration 4 */
#define TIVA_AUX_SYSIF_VECCFG5_OFFSET 0x003c /* Vector Configuration 5 */
#define TIVA_AUX_SYSIF_VECCFG6_OFFSET 0x0040 /* Vector Configuration 6 */
#define TIVA_AUX_SYSIF_VECCFG7_OFFSET 0x0044 /* Vector Configuration 7 */
#define TIVA_AUX_SYSIF_EVSYNCRATE_OFFSET 0x0048 /* Event Synchronization Rate */
#define TIVA_AUX_SYSIF_PEROPRATE_OFFSET 0x004c /* Peripheral Operational Rate */
#define TIVA_AUX_SYSIF_ADCCLKCTL_OFFSET 0x0050 /* ADC Clock Control */
#define TIVA_AUX_SYSIF_TDCCLKCTL_OFFSET 0x0054 /* TDC Counter Clock Control */
#define TIVA_AUX_SYSIF_TDCREFCLKCTL_OFFSET 0x0058 /* TDC Reference Clock Control */
#define TIVA_AUX_SYSIF_TIMER2CLKCTL_OFFSET 0x005c /* AUX_TIMER2 Clock Control */
#define TIVA_AUX_SYSIF_TIMER2CLKSTAT_OFFSET 0x0060 /* AUX_TIMER2 Clock Status */
#define TIVA_AUX_SYSIF_TIMER2CLKSWITCH_OFFSET 0x0064 /* AUX_TIMER2 Clock Switch */
#define TIVA_AUX_SYSIF_TIMER2DBGCTL_OFFSET 0x0068 /* AUX_TIMER2 Debug Control */
#define TIVA_AUX_SYSIF_CLKSHIFTDET_OFFSET 0x0070 /* Clock Shift Detection */
#define TIVA_AUX_SYSIF_RECHARGETRIG_OFFSET 0x0074 /* VDDR Recharge Trigger */
#define TIVA_AUX_SYSIF_RECHARGEDET_OFFSET 0x0078 /* VDDR Recharge Detection */
#define TIVA_AUX_SYSIF_RTCSUBSECINC0_OFFSET 0x007c /* Real Time Counter Sub Second Increment 0 */
#define TIVA_AUX_SYSIF_RTCSUBSECINC1_OFFSET 0x0080 /* Real Time Counter Sub Second Increment 1 */
#define TIVA_AUX_SYSIF_RTCSUBSECINCCTL_OFFSET 0x0084 /* Real Time Counter Sub Second Increment Control */
#define TIVA_AUX_SYSIF_RTCSEC_OFFSET 0x0088 /* Real Time Counter Second */
#define TIVA_AUX_SYSIF_RTCSUBSEC_OFFSET 0x008c /* Real Time Counter Sub-Second */
#define TIVA_AUX_SYSIF_RTCEVCLR_OFFSET 0x0090 /* AON_RTC Event Clear */
#define TIVA_AUX_SYSIF_BATMONBAT_OFFSET 0x0094 /* AON_BATMON Battery Voltage Value */
#define TIVA_AUX_SYSIF_BATMONTEMP_OFFSET 0x009c /* AON_BATMON Temperature Value */
#define TIVA_AUX_SYSIF_TIMERHALT_OFFSET 0x00a0 /* Timer Halt */
#define TIVA_AUX_SYSIF_TIMER2BRIDGE_OFFSET 0x00b0 /* AUX_TIMER2 Bridge */
#define TIVA_AUX_SYSIF_SWPWRPROF_OFFSET 0x00b4 /* Software Power Profiler */
/* AUX SYSIF Register Addresses *************************************************************************************/
#define TIVA_AUX_SYSIF_OPMODEREQ (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_OPMODEREQ_OFFSET)
#define TIVA_AUX_SYSIF_OPMODEACK (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_OPMODEACK_OFFSET)
#define TIVA_AUX_SYSIF_PROGWU0CFG (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_PROGWU0CFG_OFFSET)
#define TIVA_AUX_SYSIF_PROGWU1CFG (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_PROGWU1CFG_OFFSET)
#define TIVA_AUX_SYSIF_PROGWU2CFG (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_PROGWU2CFG_OFFSET)
#define TIVA_AUX_SYSIF_PROGWU3CFG (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_PROGWU3CFG_OFFSET)
#define TIVA_AUX_SYSIF_SWWUTRIG (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_SWWUTRIG_OFFSET)
#define TIVA_AUX_SYSIF_WUFLAGS (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_WUFLAGS_OFFSET)
#define TIVA_AUX_SYSIF_WUFLAGSCLR (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_WUFLAGSCLR_OFFSET)
#define TIVA_AUX_SYSIF_WUGATE (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_WUGATE_OFFSET)
#define TIVA_AUX_SYSIF_VECCFG0 (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_VECCFG0_OFFSET)
#define TIVA_AUX_SYSIF_VECCFG1 (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_VECCFG1_OFFSET)
#define TIVA_AUX_SYSIF_VECCFG2 (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_VECCFG2_OFFSET)
#define TIVA_AUX_SYSIF_VECCFG3 (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_VECCFG3_OFFSET)
#define TIVA_AUX_SYSIF_VECCFG4 (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_VECCFG4_OFFSET)
#define TIVA_AUX_SYSIF_VECCFG5 (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_VECCFG5_OFFSET)
#define TIVA_AUX_SYSIF_VECCFG6 (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_VECCFG6_OFFSET)
#define TIVA_AUX_SYSIF_VECCFG7 (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_VECCFG7_OFFSET)
#define TIVA_AUX_SYSIF_EVSYNCRATE (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_EVSYNCRATE_OFFSET)
#define TIVA_AUX_SYSIF_PEROPRATE (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_PEROPRATE_OFFSET)
#define TIVA_AUX_SYSIF_ADCCLKCTL (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_ADCCLKCTL_OFFSET)
#define TIVA_AUX_SYSIF_TDCCLKCTL (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_TDCCLKCTL_OFFSET)
#define TIVA_AUX_SYSIF_TDCREFCLKCTL (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_TDCREFCLKCTL_OFFSET)
#define TIVA_AUX_SYSIF_TIMER2CLKCTL (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_TIMER2CLKCTL_OFFSET)
#define TIVA_AUX_SYSIF_TIMER2CLKSTAT (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_TIMER2CLKSTAT_OFFSET)
#define TIVA_AUX_SYSIF_TIMER2CLKSWITCH (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_TIMER2CLKSWITCH_OFFSET)
#define TIVA_AUX_SYSIF_TIMER2DBGCTL (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_TIMER2DBGCTL_OFFSET)
#define TIVA_AUX_SYSIF_CLKSHIFTDET (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_CLKSHIFTDET_OFFSET)
#define TIVA_AUX_SYSIF_RECHARGETRIG (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_RECHARGETRIG_OFFSET)
#define TIVA_AUX_SYSIF_RECHARGEDET (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_RECHARGEDET_OFFSET)
#define TIVA_AUX_SYSIF_RTCSUBSECINC0 (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_RTCSUBSECINC0_OFFSET)
#define TIVA_AUX_SYSIF_RTCSUBSECINC1 (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_RTCSUBSECINC1_OFFSET)
#define TIVA_AUX_SYSIF_RTCSUBSECINCCTL (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_RTCSUBSECINCCTL_OFFSET)
#define TIVA_AUX_SYSIF_RTCSEC (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_RTCSEC_OFFSET)
#define TIVA_AUX_SYSIF_RTCSUBSEC (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_RTCSUBSEC_OFFSET)
#define TIVA_AUX_SYSIF_RTCEVCLR (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_RTCEVCLR_OFFSET)
#define TIVA_AUX_SYSIF_BATMONBAT (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_BATMONBAT_OFFSET)
#define TIVA_AUX_SYSIF_BATMONTEMP (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_BATMONTEMP_OFFSET)
#define TIVA_AUX_SYSIF_TIMERHALT (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_TIMERHALT_OFFSET)
#define TIVA_AUX_SYSIF_TIMER2BRIDGE (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_TIMER2BRIDGE_OFFSET)
#define TIVA_AUX_SYSIF_SWPWRPROF (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_SWPWRPROF_OFFSET)
/* AUX SYSIF Register Bifield Definitions ***************************************************************************/
/* AUX_SYSIF_OPMODEREQ */
#define AUX_SYSIF_OPMODEREQ_REQ_SHIFT (0) /* Bits 0-1: AUX operational mode request */
#define AUX_SYSIF_OPMODEREQ_REQ_MASK (3 << AUX_SYSIF_OPMODEREQ_REQ_SHIFT)
# define AUX_SYSIF_OPMODEREQ_REQ(n) ((uint32_t)(n) << AUX_SYSIF_OPMODEREQ_REQ_SHIFT)
# define AUX_SYSIF_OPMODEREQ_REQ_A (0 << AUX_SYSIF_OPMODEREQ_REQ_SHIFT) /* Active operational mode */
# define AUX_SYSIF_OPMODEREQ_REQ_LP (1 << AUX_SYSIF_OPMODEREQ_REQ_SHIFT) /* Low power operational mode */
# define AUX_SYSIF_OPMODEREQ_REQ_PDA (2 << AUX_SYSIF_OPMODEREQ_REQ_SHIFT) /* Power down operational mode
* with wakeup to active mode */
# define AUX_SYSIF_OPMODEREQ_REQ_PDLP (3 << AUX_SYSIF_OPMODEREQ_REQ_SHIFT) /* Powerdown operational mode
* with wakeup to lowpower mode */
/* AUX_SYSIF_OPMODEACK */
#define AUX_SYSIF_OPMODEACK_ACK_SHIFT (0) /* Bits 0-1: AUX operational mode acknowledgment */
#define AUX_SYSIF_OPMODEACK_ACK_MASK (3 << AUX_SYSIF_OPMODEACK_ACK_SHIFT)
# define AUX_SYSIF_OPMODEACK_ACK_A (0 << AUX_SYSIF_OPMODEACK_ACK_SHIFT) /* Active operational mode */
# define AUX_SYSIF_OPMODEACK_ACK_LP (1 << AUX_SYSIF_OPMODEACK_ACK_SHIFT) /* Low power operational mode */
# define AUX_SYSIF_OPMODEACK_ACK_PDA (2 << AUX_SYSIF_OPMODEACK_ACK_SHIFT) /* Power down operational mode
* with wakeup to active mode */
# define AUX_SYSIF_OPMODEACK_ACK_PDLP (3 << AUX_SYSIF_OPMODEACK_ACK_SHIFT) /* Powerdown operational mode
* with wakeup to lowpower mode */
/* AUX_SYSIF_PROGWU0CFG */
#define AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT (0) /* Bits 0-5: Wakeup source from the asynchronous AUX event bus */
#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MASK (0x3f << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC(n) ((uint32_t)(n) << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO0 (0x00 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO1 (0x01 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO2 (0x02 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO3 (0x03 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO4 (0x04 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO5 (0x05 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO6 (0x06 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO7 (0x07 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO8 (0x08 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO9 (0x09 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO10 (0x0a << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO11 (0x0b << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO12 (0x0c << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO13 (0x0d << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO14 (0x0e << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO15 (0x0f << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO16 (0x10 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO17 (0x11 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO18 (0x12 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO19 (0x13 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO20 (0x14 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO21 (0x15 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO22 (0x16 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO23 (0x17 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO24 (0x18 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO25 (0x19 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO26 (0x1a << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO27 (0x1b << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO28 (0x1c << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO29 (0x1d << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO30 (0x1e << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO31 (0x1f << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_MANUAL_EV (0x20 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_CH2 (0x21 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_CH2_DLY (0x22 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_4KHZ (0x23 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_BATMON_BAT_UPD (0x24 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_BATMON_TEMP_UPD (0x25 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_SCLK_LF (0x26 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_PWR_DWN (0x27 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_ACTIVE (0x28 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_VDDR_RECHARGE (0x29 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_ACLK_REF (0x2a << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_EV (0x2b << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_OBSMUX0 (0x2c << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_OBSMUX1 (0x2d << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_COMPA (0x2e << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_COMPB (0x2f << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV0 (0x30 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV1 (0x31 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV2 (0x32 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV3 (0x33 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_PULSE (0x34 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER1_EV (0x35 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER0_EV (0x36 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TDC_DONE (0x37 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ISRC_RESET_N (0x38 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_DONE (0x39 << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_IRQ (0x3a << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL (0x3b << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY (0x3c << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE (0x3d << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU0CFG_WU_SRC_NO_EVENT (0x3f << AUX_SYSIF_PROGWU0CFG_WU_SRC_SHIFT)
#define AUX_SYSIF_PROGWU0CFG_EN (1 << 6) /* Bit 6: Programmable wakeup flag enable */
#define AUX_SYSIF_PROGWU0CFG_POL (1 << 7) /* Bit 7: Polarity of WU_SRC */
# define AUX_SYSIF_PROGWU0CFG_POL_LOW AUX_SYSIF_PROGWU0CFG_POL
# define AUX_SYSIF_PROGWU0CFG_POL_HIGH (0)
/* AUX_SYSIF_PROGWU1CFG */
#define AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT (0) /* Bits 0-5: Wakeup source from the asynchronous AUX event bus */
#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MASK (0x3f << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO0 (0x00 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO1 (0x01 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO2 (0x02 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO3 (0x03 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO4 (0x04 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO5 (0x05 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO6 (0x06 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO7 (0x07 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO8 (0x08 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO9 (0x09 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO10 (0x0a << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO11 (0x0b << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO12 (0x0c << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO13 (0x0d << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO14 (0x0e << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO15 (0x0f << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO16 (0x10 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO17 (0x11 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO18 (0x12 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO19 (0x13 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO20 (0x14 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO21 (0x15 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO22 (0x16 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO23 (0x17 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO24 (0x18 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO25 (0x19 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO26 (0x1a << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO27 (0x1b << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO28 (0x1c << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO29 (0x1d << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO30 (0x1e << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO31 (0x1f << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_MANUAL_EV (0x20 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_CH2 (0x21 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_CH2_DLY (0x22 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_4KHZ (0x23 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_BATMON_BAT_UPD (0x24 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_BATMON_TEMP_UPD (0x25 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_SCLK_LF (0x26 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_PWR_DWN (0x27 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_ACTIVE (0x28 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_VDDR_RECHARGE (0x29 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_ACLK_REF (0x2a << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_EV (0x2b << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_OBSMUX0 (0x2c << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_OBSMUX1 (0x2d << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_COMPA (0x2e << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_COMPB (0x2f << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV0 (0x30 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV1 (0x31 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV2 (0x32 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV3 (0x33 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_PULSE (0x34 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER1_EV (0x35 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER0_EV (0x36 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TDC_DONE (0x37 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ISRC_RESET_N (0x38 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_DONE (0x39 << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_IRQ (0x3a << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL (0x3b << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY (0x3c << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE (0x3d << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU1CFG_WU_SRC_NO_EVENT (0x3f << AUX_SYSIF_PROGWU1CFG_WU_SRC_SHIFT)
#define AUX_SYSIF_PROGWU1CFG_EN (1 << 6) /* Bit 6: Programmable wakeup flag enable */
#define AUX_SYSIF_PROGWU1CFG_POL (1 << 7) /* Bit 7: Polarity of WU_SRC */
# define AUX_SYSIF_PROGWU1CFG_POL_LOW AUX_SYSIF_PROGWU1CFG_POL
# define AUX_SYSIF_PROGWU1CFG_POL_HIGH (0)
/* AUX_SYSIF_PROGWU2CFG */
#define AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT (0) /* Bits 0-5: Wakeup source from the asynchronous AUX event bus */
#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MASK (0x3f << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC(n) ((uint32_t)(n) << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO0 (0x00 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO1 (0x01 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO2 (0x02 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO3 (0x03 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO4 (0x04 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO5 (0x05 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO6 (0x06 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO7 (0x07 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO8 (0x08 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO9 (0x09 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO10 (0x0a << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO11 (0x0b << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO12 (0x0c << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO13 (0x0d << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO14 (0x0e << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO15 (0x0f << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO16 (0x10 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO17 (0x11 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO18 (0x12 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO19 (0x13 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO20 (0x14 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO21 (0x15 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO22 (0x16 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO23 (0x17 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO24 (0x18 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO25 (0x19 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO26 (0x1a << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO27 (0x1b << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO28 (0x1c << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO29 (0x1d << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO30 (0x1e << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO31 (0x1f << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_MANUAL_EV (0x20 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_CH2 (0x21 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_CH2_DLY (0x22 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_4KHZ (0x23 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_BATMON_BAT_UPD (0x24 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_BATMON_TEMP_UPD (0x25 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_SCLK_LF (0x26 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_PWR_DWN (0x27 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_ACTIVE (0x28 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_VDDR_RECHARGE (0x29 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_ACLK_REF (0x2a << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_EV (0x2b << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_OBSMUX0 (0x2c << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_OBSMUX1 (0x2d << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_COMPA (0x2e << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_COMPB (0x2f << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV0 (0x30 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV1 (0x31 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV2 (0x32 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV3 (0x33 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_PULSE (0x34 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER1_EV (0x35 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER0_EV (0x36 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TDC_DONE (0x37 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ISRC_RESET_N (0x38 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_DONE (0x39 << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_IRQ (0x3a << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL (0x3b << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY (0x3c << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE (0x3d << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU2CFG_WU_SRC_NO_EVENT (0x3f << AUX_SYSIF_PROGWU2CFG_WU_SRC_SHIFT)
#define AUX_SYSIF_PROGWU2CFG_EN (1 << 6) /* Bit 6: Programmable wakeup flag enable */
#define AUX_SYSIF_PROGWU2CFG_POL (1 << 7) /* Bit 7: */
# define AUX_SYSIF_PROGWU2CFG_POL_LOW AUX_SYSIF_PROGWU2CFG_POL
# define AUX_SYSIF_PROGWU2CFG_POL_HIGH (0)
/* AUX_SYSIF_PROGWU3CFG */
#define AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT (0) /* Bits 0-5: Wakeup source from the asynchronous AUX event bus */
#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MASK (0x3f << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC(n) ((uint32_t)(n) << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC(n) ((uint32_t)(n) << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO0 (0x00 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO1 (0x01 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO2 (0x02 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO3 (0x03 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO4 (0x04 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO5 (0x05 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO6 (0x06 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO7 (0x07 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO8 (0x08 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO9 (0x09 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO10 (0x0a << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO11 (0x0b << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO12 (0x0c << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO13 (0x0d << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO14 (0x0e << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO15 (0x0f << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO16 (0x10 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO17 (0x11 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO18 (0x12 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO19 (0x13 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO20 (0x14 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO21 (0x15 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO22 (0x16 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO23 (0x17 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO24 (0x18 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO25 (0x19 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO26 (0x1a << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO27 (0x1b << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO28 (0x1c << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO29 (0x1d << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO30 (0x1e << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO31 (0x1f << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_MANUAL_EV (0x20 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_CH2 (0x21 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_CH2_DLY (0x22 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_4KHZ (0x23 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_BATMON_BAT_UPD (0x24 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_BATMON_TEMP_UPD (0x25 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_SCLK_LF (0x26 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_PWR_DWN (0x27 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_ACTIVE (0x28 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_VDDR_RECHARGE (0x29 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_ACLK_REF (0x2a << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_EV (0x2b << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_OBSMUX0 (0x2c << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_OBSMUX1 (0x2d << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_COMPA (0x2e << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_COMPB (0x2f << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV0 (0x30 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV1 (0x31 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV2 (0x32 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV3 (0x33 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_PULSE (0x34 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER1_EV (0x35 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER0_EV (0x36 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TDC_DONE (0x37 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ISRC_RESET_N (0x38 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_DONE (0x39 << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_IRQ (0x3a << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL (0x3b << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY (0x3c << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE (0x3d << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
# define AUX_SYSIF_PROGWU3CFG_WU_SRC_NO_EVENT (0x3f << AUX_SYSIF_PROGWU3CFG_WU_SRC_SHIFT)
#define AUX_SYSIF_PROGWU3CFG_EN (1 << 6) /* Bit 6: Programmable wakeup flag enable */
#define AUX_SYSIF_PROGWU3CFG_POL (1 << 7) /* Bit 7: Polarity of WU_SRC */
# define AUX_SYSIF_PROGWU3CFG_POL_LOW AUX_SYSIF_PROGWU3CFG_POL
# define AUX_SYSIF_PROGWU3CFG_POL_HIGH (0)
/* AUX_SYSIF_SWWUTRIG */
#define AUX_SYSIF_SWWUTRIG_SW_WU0 (1 << 0) /* Bit 0: Software wakeup 0 trigger */
#define AUX_SYSIF_SWWUTRIG_SW_WU1 (1 << 1) /* Bit 1: Software wakeup 1 trigger */
#define AUX_SYSIF_SWWUTRIG_SW_WU2 (1 << 2) /* Bit 2: Software wakeup 2 trigger */
#define AUX_SYSIF_SWWUTRIG_SW_WU3 (1 << 3) /* Bit 3: Software wakeup 3 trigger */
/* AUX_SYSIF_WUFLAGS */
#define AUX_SYSIF_WUFLAGS_PROG_WU0 (1 << 0) /* Bit 0: Programmable wakeup 0. */
#define AUX_SYSIF_WUFLAGS_PROG_WU1 (1 << 1) /* Bit 1: Programmable wakeup 1 */
#define AUX_SYSIF_WUFLAGS_PROG_WU2 (1 << 2) /* Bit 2: Programmable wakeup 2 */
#define AUX_SYSIF_WUFLAGS_PROG_WU3 (1 << 3) /* Bit 3: Programmable wakeup 3 */
#define AUX_SYSIF_WUFLAGS_SW_WU0 (1 << 4) /* Bit 4: Software wakeup 0 flag */
#define AUX_SYSIF_WUFLAGS_SW_WU1 (1 << 5) /* Bit 5: Software wakeup 1 flag */
#define AUX_SYSIF_WUFLAGS_SW_WU2 (1 << 6) /* Bit 6: Software wakeup 2 flag */
#define AUX_SYSIF_WUFLAGS_SW_WU3 (1 << 7) /* Bit 7: Software wakeup 3 flag */
/* AUX_SYSIF_WUFLAGSCLR */
#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0 (1 << 0) /* Bit 0: Programmable wakeup flag 0 */
#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1 (1 << 1) /* Bit 1: Programmable wakeup flag 1 */
#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2 (1 << 2) /* Bit 2: Programmable wakeup flag 2 */
#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3 (1 << 3) /* Bit 3: Programmable wakeup flag 3 */
#define AUX_SYSIF_WUFLAGSCLR_SW_WU0 (1 << 4) /* Bit 4: Clear software wakeup flag 0 */
#define AUX_SYSIF_WUFLAGSCLR_SW_WU1 (1 << 5) /* Bit 5: Clear software wakeup flag 1 */
#define AUX_SYSIF_WUFLAGSCLR_SW_WU2 (1 << 6) /* Bit 6: Clear software wakeup flag 2 */
#define AUX_SYSIF_WUFLAGSCLR_SW_WU3 (1 << 7) /* Bit 7: Clear software wakeup flag 3 */
/* AUX_SYSIF_WUGATE */
#define AUX_SYSIF_WUGATE_EN (1 << 0) /* Bit 0: Wakeup output enable */
/* AUX_SYSIF_VECCFG0 */
#define AUX_SYSIF_VECCFG0_VEC_EV_SHIFT (0) /* Bits 0-3: Select trigger event for vector 0 */
#define AUX_SYSIF_VECCFG0_VEC_EV_MASK (15 << AUX_SYSIF_VECCFG0_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG0_VEC_EV(n) ((uint32_t)(n) << AUX_SYSIF_VECCFG0_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG0_VEC_EV_NONE (0 << AUX_SYSIF_VECCFG0_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU0 (1 << AUX_SYSIF_VECCFG0_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU1 (2 << AUX_SYSIF_VECCFG0_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU2 (3 << AUX_SYSIF_VECCFG0_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU3 (4 << AUX_SYSIF_VECCFG0_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU0 (5 << AUX_SYSIF_VECCFG0_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU1 (6 << AUX_SYSIF_VECCFG0_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU2 (7 << AUX_SYSIF_VECCFG0_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU3 (8 << AUX_SYSIF_VECCFG0_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG0_VEC_EV_AON_RTC_CH2_DLY (9 << AUX_SYSIF_VECCFG0_VEC_EV_SHIFT)
/* AUX_SYSIF_VECCFG1 */
#define AUX_SYSIF_VECCFG1_VEC_EV_SHIFT (0) /* Bits 0-3: Select trigger event for vector 1 */
#define AUX_SYSIF_VECCFG1_VEC_EV_MASK (15 << AUX_SYSIF_VECCFG1_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG1_VEC_EV(n) ((uint32_t)(n) << AUX_SYSIF_VECCFG1_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG1_VEC_EV_NONE (0 << AUX_SYSIF_VECCFG1_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU0 (1 << AUX_SYSIF_VECCFG1_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU1 (2 << AUX_SYSIF_VECCFG1_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU2 (3 << AUX_SYSIF_VECCFG1_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU3 (4 << AUX_SYSIF_VECCFG1_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU0 (5 << AUX_SYSIF_VECCFG1_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU1 (6 << AUX_SYSIF_VECCFG1_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU2 (7 << AUX_SYSIF_VECCFG1_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU3 (8 << AUX_SYSIF_VECCFG1_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG1_VEC_EV_AON_RTC_CH2_DLY (9 << AUX_SYSIF_VECCFG1_VEC_EV_SHIFT)
/* AUX_SYSIF_VECCFG2 */
#define AUX_SYSIF_VECCFG2_VEC_EV_SHIFT (0) /* Bits 0-3: Select trigger event for vector 2 */
#define AUX_SYSIF_VECCFG2_VEC_EV_MASK (15 << AUX_SYSIF_VECCFG2_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG2_VEC_EV(n) ((uint32_t)(n) << AUX_SYSIF_VECCFG2_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG2_VEC_EV_NONE (0 << AUX_SYSIF_VECCFG2_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU0 (1 << AUX_SYSIF_VECCFG2_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU1 (2 << AUX_SYSIF_VECCFG2_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU2 (3 << AUX_SYSIF_VECCFG2_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU3 (4 << AUX_SYSIF_VECCFG2_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU0 (5 << AUX_SYSIF_VECCFG2_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU1 (6 << AUX_SYSIF_VECCFG2_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU2 (7 << AUX_SYSIF_VECCFG2_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU3 (8 << AUX_SYSIF_VECCFG2_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG2_VEC_EV_AON_RTC_CH2_DLY (9 << AUX_SYSIF_VECCFG2_VEC_EV_SHIFT)
/* AUX_SYSIF_VECCFG3 */
#define AUX_SYSIF_VECCFG3_VEC_EV_SHIFT (0) /* Bits 0-3: Select trigger event for vector 3 */
#define AUX_SYSIF_VECCFG3_VEC_EV_MASK (15 << AUX_SYSIF_VECCFG3_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG3_VEC_EV(n) ((uint32_t)(n) << AUX_SYSIF_VECCFG3_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG3_VEC_EV_NONE (0 << AUX_SYSIF_VECCFG3_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU0 (1 << AUX_SYSIF_VECCFG3_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU1 (2 << AUX_SYSIF_VECCFG3_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU2 (3 << AUX_SYSIF_VECCFG3_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU3 (4 << AUX_SYSIF_VECCFG3_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU0 (5 << AUX_SYSIF_VECCFG3_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU1 (6 << AUX_SYSIF_VECCFG3_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU2 (7 << AUX_SYSIF_VECCFG3_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU3 (8 << AUX_SYSIF_VECCFG3_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG3_VEC_EV_AON_RTC_CH2_DLY (9 << AUX_SYSIF_VECCFG3_VEC_EV_SHIFT)
/* AUX_SYSIF_VECCFG4 */
#define AUX_SYSIF_VECCFG4_VEC_EV_SHIFT (0) /* Bits 0-3: Select trigger event for vector 4 */
#define AUX_SYSIF_VECCFG4_VEC_EV_MASK (15 << AUX_SYSIF_VECCFG4_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG4_VEC_EV(n) ((uint32_t)(n) << AUX_SYSIF_VECCFG4_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG4_VEC_EV_NONE (0 << AUX_SYSIF_VECCFG4_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU0 (1 << AUX_SYSIF_VECCFG4_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU1 (2 << AUX_SYSIF_VECCFG4_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU2 (3 << AUX_SYSIF_VECCFG4_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU3 (4 << AUX_SYSIF_VECCFG4_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU0 (5 << AUX_SYSIF_VECCFG4_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU1 (6 << AUX_SYSIF_VECCFG4_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU2 (7 << AUX_SYSIF_VECCFG4_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU3 (8 << AUX_SYSIF_VECCFG4_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG4_VEC_EV_AON_RTC_CH2_DLY (9 << AUX_SYSIF_VECCFG4_VEC_EV_SHIFT)
/* AUX_SYSIF_VECCFG5 */
#define AUX_SYSIF_VECCFG5_VEC_EV_SHIFT (0) /* Bits 0-3: Select trigger event for vector 5 */
#define AUX_SYSIF_VECCFG5_VEC_EV_MASK (15 << AUX_SYSIF_VECCFG5_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG5_VEC_EV(n) ((uint32_t)(n) << AUX_SYSIF_VECCFG5_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG5_VEC_EV_NONE (0 << AUX_SYSIF_VECCFG5_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU0 (1 << AUX_SYSIF_VECCFG5_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU1 (2 << AUX_SYSIF_VECCFG5_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU2 (3 << AUX_SYSIF_VECCFG5_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU3 (4 << AUX_SYSIF_VECCFG5_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU0 (5 << AUX_SYSIF_VECCFG5_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU1 (6 << AUX_SYSIF_VECCFG5_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU2 (7 << AUX_SYSIF_VECCFG5_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU3 (8 << AUX_SYSIF_VECCFG5_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG5_VEC_EV_AON_RTC_CH2_DLY (9 << AUX_SYSIF_VECCFG5_VEC_EV_SHIFT)
/* AUX_SYSIF_VECCFG6 */
#define AUX_SYSIF_VECCFG6_VEC_EV_SHIFT (0) /* Bits 0-3: Select trigger event for vector 6 */
#define AUX_SYSIF_VECCFG6_VEC_EV_MASK (15 << AUX_SYSIF_VECCFG6_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG6_VEC_EV(n) ((uint32_t)(n) << AUX_SYSIF_VECCFG6_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG6_VEC_EV_NONE (0 << AUX_SYSIF_VECCFG6_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU0 (1 << AUX_SYSIF_VECCFG6_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU1 (2 << AUX_SYSIF_VECCFG6_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU2 (3 << AUX_SYSIF_VECCFG6_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU3 (4 << AUX_SYSIF_VECCFG6_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU0 (5 << AUX_SYSIF_VECCFG6_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU1 (6 << AUX_SYSIF_VECCFG6_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU2 (7 << AUX_SYSIF_VECCFG6_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU3 (8 << AUX_SYSIF_VECCFG6_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG6_VEC_EV_AON_RTC_CH2_DLY (9 << AUX_SYSIF_VECCFG6_VEC_EV_SHIFT)
/* AUX_SYSIF_VECCFG7 */
#define AUX_SYSIF_VECCFG7_VEC_EV_SHIFT (0) /* Bits 0-3: Select trigger event for vector 7 */
#define AUX_SYSIF_VECCFG7_VEC_EV_MASK (15 << AUX_SYSIF_VECCFG7_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG7_VEC_EV(n) ((uint32_t)(n) << AUX_SYSIF_VECCFG7_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG7_VEC_EV_NONE (0 << AUX_SYSIF_VECCFG7_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU0 (1 << AUX_SYSIF_VECCFG7_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU1 (2 << AUX_SYSIF_VECCFG7_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU2 (3 << AUX_SYSIF_VECCFG7_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU3 (4 << AUX_SYSIF_VECCFG7_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU0 (5 << AUX_SYSIF_VECCFG7_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU1 (6 << AUX_SYSIF_VECCFG7_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU2 (7 << AUX_SYSIF_VECCFG7_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU3 (8 << AUX_SYSIF_VECCFG7_VEC_EV_SHIFT)
# define AUX_SYSIF_VECCFG7_VEC_EV_AON_RTC_CH2_DLY (9 << AUX_SYSIF_VECCFG7_VEC_EV_SHIFT)
/* AUX_SYSIF_EVSYNCRATE */
#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE (1 << 0) /* Bit 0: Select synchronization rate for
* AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0..AUX_TIMER2_EV3
* and AUX_TIMER2_PULSE */
# define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_BUS_RATE AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE
# define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_SCE_RATE (0)
#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE (1 << 1) /* Bit 1: Select synchronization rate for
* AUX_EVCTL:EVSTAT2.AUX_COMPB event */
# define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_BUS_RATE AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE
# define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_SCE_RATE (0)
#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE (1 << 2) /* Bit 2: Select synchronization rate for
* AUX_EVCTL:EVSTAT2.AUX_COMPA event */
# define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_BUS_RATE AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE
# define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_SCE_RATE (0)
/* AUX_SYSIF_PEROPRATE */
#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE (1 << 0) /* Bit 0: Select operational rate for AUX_MAC */
# define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_BUS_RATE AUX_SYSIF_PEROPRATE_MAC_OP_RATE
# define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_SCE_RATE (0)
#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE (1 << 1) /* Bit 1: Select operational rate for AUX_SPIM */
# define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_BUS_RATE AUX_SYSIF_PEROPRATE_SPIM_OP_RATE
# define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_SCE_RATE (0)
#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE (1 << 2) /* Bit 2: Select operational rate for AUX_TIMER01 */
# define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_BUS_RATE AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE
# define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_SCE_RATE (0)
#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE (1 << 3) /* Bit 3: Select operational rate for AUX_ANAIF
* DAC sample clock state machine */
# define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_BUS_RATE AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE
# define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_SCE_RATE (0)
/* AUX_SYSIF_ADCCLKCTL */
#define AUX_SYSIF_ADCCLKCTL_REQ (1 << 0) /* Bit 0: ADC clock request */
#define AUX_SYSIF_ADCCLKCTL_ACK (1 << 1) /* Bit 1: Clock acknowledgment */
/* AUX_SYSIF_TDCCLKCTL */
#define AUX_SYSIF_TDCCLKCTL_REQ (1 << 0) /* Bit 0: TDC counter clock request */
#define AUX_SYSIF_TDCCLKCTL_ACK (1 << 1) /* Bit 1: TDC counter clock acknowledgment */
/* AUX_SYSIF_TDCREFCLKCTL */
#define AUX_SYSIF_TDCREFCLKCTL_REQ (1 << 0) /* Bit 0: TDC reference clock request */
#define AUX_SYSIF_TDCREFCLKCTL_ACK (1 << 1) /* Bit 1: TDC reference clock acknowledgment */
/* AUX_SYSIF_TIMER2CLKCTL */
#define AUX_SYSIF_TIMER2CLKCTL_SRC_SHIFT (0) /* Bits 0-2: Select clock source for AUX_TIMER2 */
#define AUX_SYSIF_TIMER2CLKCTL_SRC_MASK (7 << AUX_SYSIF_TIMER2CLKCTL_SRC_SHIFT)
# define AUX_SYSIF_TIMER2CLKCTL_SRC(n) ((uint32_t)(n) << AUX_SYSIF_TIMER2CLKCTL_SRC_SHIFT)
# define AUX_SYSIF_TIMER2CLKCTL_SRC_NONE (0 << AUX_SYSIF_TIMER2CLKCTL_SRC_SHIFT)) /* No clock */
# define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_LF (1 << AUX_SYSIF_TIMER2CLKCTL_SRC_SHIFT)) /* SCLK_LF */
# define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_MF (2 << AUX_SYSIF_TIMER2CLKCTL_SRC_SHIFT)) /* SCLK_MF */
# define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_HFDIV2 (4 << AUX_SYSIF_TIMER2CLKCTL_SRC_SHIFT)) /* SCLK_HF / 2 */
/* AUX_SYSIF_TIMER2CLKSTAT */
#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SHIFT (0) /* Bits 0-2: AUX_TIMER2 clock source status */
#define AUX_SYSIF_TIMER2CLKSTAT_STAT_MASK (7 << AUX_SYSIF_TIMER2CLKSTAT_STAT_SHIFT)
# define AUX_SYSIF_TIMER2CLKSTAT_STAT(n) ((uint32_t)(n) << AUX_SYSIF_TIMER2CLKSTAT_STAT_SHIFT)
# define AUX_SYSIF_TIMER2CLKSTAT_STAT_NONE (0 << AUX_SYSIF_TIMER2CLKSTAT_STAT_SHIFT)) /* No clock */
# define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_LF (1 << AUX_SYSIF_TIMER2CLKSTAT_STAT_SHIFT)) /* SCLK_LF */
# define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_MF (2 << AUX_SYSIF_TIMER2CLKSTAT_STAT_SHIFT)) /* SCLK_MF */
# define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_HFDIV2 (4 << AUX_SYSIF_TIMER2CLKSTAT_STAT_SHIFT)) /* SCLK_HF / 2 */
/* AUX_SYSIF_TIMER2CLKSWITCH */
#define AUX_SYSIF_TIMER2CLKSWITCH_RDY (1 << 0) /* Bit 0: Status of clock switcher */
/* 1: TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STA */
/* AUX_SYSIF_TIMER2DBGCTL */
#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN (1 << 0) /* Bit 0: Debug freeze enable */
/* AUX_SYSIF_CLKSHIFTDET */
#define AUX_SYSIF_CLKSHIFTDET_STAT (1 << 0) /* Bit 0: Clock shift detection */
/* AUX_SYSIF_RECHARGETRIG */
#define AUX_SYSIF_RECHARGETRIG_TRIG (1 << 0) /* Bit 0: Recharge trigger */
/* AUX_SYSIF_RECHARGEDET */
#define AUX_SYSIF_RECHARGEDET_EN (1 << 0) /* Bit 0: VDDR recharge detector enable */
#define AUX_SYSIF_RECHARGEDET_STAT (1 << 1) /* Bit 1: VDDR recharge detector status */
/* AUX_SYSIF_RTCSUBSECINC0 */
#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_SHIFT (0) /* Bits 0-15: New value for bits 15:0 in AON_RTC:SUBSECINC */
#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_MASK (0xffff << AUX_SYSIF_RTCSUBSECINC0_INC15_0_SHIFT)
# define AUX_SYSIF_RTCSUBSECINC0_INC15_0(n) ((uint32_t)(n) << AUX_SYSIF_RTCSUBSECINC0_INC15_0_SHIFT)
/* AUX_SYSIF_RTCSUBSECINC1 */
#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_SHIFT (0) /* Bits 0-7: New value for bits 23:16 in AON_RTC:SUBSECINC */
#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_MASK (0xff << AUX_SYSIF_RTCSUBSECINC1_INC23_16_SHIFT)
# define AUX_SYSIF_RTCSUBSECINC1_INC23_16(n) ((uint32_t)(n) << AUX_SYSIF_RTCSUBSECINC1_INC23_16_SHIFT)
/* AUX_SYSIF_RTCSUBSECINCCTL */
#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ (1 << 0) /* Bit 0: Request AON_RTC to update AON_RTC:SUBSECINC */
#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK (1 << 1) /* Bit 1: Update acknowledgment */
/* AUX_SYSIF_RTCSEC */
#define AUX_SYSIF_RTCSEC_SEC_SHIFT (0) /* Bits 0-15: Bits 15:0 in AON_RTC:SEC.VALUE */
#define AUX_SYSIF_RTCSEC_SEC_MASK (0xffff << AUX_SYSIF_RTCSEC_SEC_SHIFT)
# define AUX_SYSIF_RTCSEC_SEC(n) ((uint32_t)(n) << AUX_SYSIF_RTCSEC_SEC_SHIFT)
/* AUX_SYSIF_RTCSUBSEC */
#define AUX_SYSIF_RTCSUBSEC_SUBSEC_SHIFT (0) /* Bits 0-15: Bits 31:16 in AON_RTC:SUBSEC.VALUE */
#define AUX_SYSIF_RTCSUBSEC_SUBSEC_MASK (0xffff << AUX_SYSIF_RTCSUBSEC_SUBSEC_SHIFT)
# define AUX_SYSIF_RTCSUBSEC_SUBSEC(n) ((uint32_t)(n) << AUX_SYSIF_RTCSUBSEC_SUBSEC_SHIFT)
/* AUX_SYSIF_RTCEVCLR */
#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR (1 << 0) /* Bit 0: Clear events from AON_RTC channel 2 */
/* AUX_SYSIF_BATMONBAT */
#define AUX_SYSIF_BATMONBAT_FRAC_SHIFT (0) /* Bits 0-7: See AON_BATMON:BAT.FRAC */
#define AUX_SYSIF_BATMONBAT_FRAC_MASK (0xff << AUX_SYSIF_BATMONBAT_FRAC_SHIFT)
# define AUX_SYSIF_BATMONBAT_FRAC(n) ((uint32_t)(n) << AUX_SYSIF_BATMONBAT_FRAC_SHIFT)
#define AUX_SYSIF_BATMONBAT_INT_SHIFT (8) /* Bits 8-10: See AON_BATMON:BAT.INT */
#define AUX_SYSIF_BATMONBAT_INT_MASK (7 << AUX_SYSIF_BATMONBAT_INT_SHIFT)
# define AUX_SYSIF_BATMONBAT_INT(n) ((uint32_t)(n) << xxAUX_SYSIF_BATMONBAT_INT_SHIFT
/* AUX_SYSIF_BATMONTEMP */
#define AUX_SYSIF_BATMONTEMP_FRAC_SHIFT (0) /* Bits 0-1: See AON_BATMON:TEMP.FRAC */
#define AUX_SYSIF_BATMONTEMP_FRAC_MASK (3 << AUX_SYSIF_BATMONTEMP_FRAC_SHIFT)
# define AUX_SYSIF_BATMONTEMP_FRAC(n) ((uint32_t)(n) << AUX_SYSIF_BATMONTEMP_FRAC_SHIFT)
#define AUX_SYSIF_BATMONTEMP_INT_SHIFT (2) /* Bits 2-10: See AON_BATMON:TEMP.INT */
#define AUX_SYSIF_BATMONTEMP_INT_MASK (0x1ff << AUX_SYSIF_BATMONTEMP_INT_SHIFT)
# define AUX_SYSIF_BATMONTEMP_INT(n) ((uint32_t)(n) << AUX_SYSIF_BATMONTEMP_INT_SHIFT)
#define AUX_SYSIF_BATMONTEMP_SIGN_SHIFT (11) /* Bits 11-15: Sign extension of INT */
#define AUX_SYSIF_BATMONTEMP_SIGN_MASK (31 << AUX_SYSIF_BATMONTEMP_SIGN_SHIFT)
# define AUX_SYSIF_BATMONTEMP_SIGN(n) ((uint32_t)(n) << AUX_SYSIF_BATMONTEMP_SIGN_SHIFT)
/* AUX_SYSIF_TIMERHALT */
#define AUX_SYSIF_TIMERHALT_AUX_TIMER0 (1 << 0) /* Bit 0: Halt AUX_TIMER01 Timer 0 */
#define AUX_SYSIF_TIMERHALT_AUX_TIMER1 (1 << 1) /* Bit 1: Halt AUX_TIMER01 Timer 1 */
#define AUX_SYSIF_TIMERHALT_AUX_TIMER2 (1 << 2) /* Bit 2: Halt AUX_TIMER2 */
#define AUX_SYSIF_TIMERHALT_PROGDLY (1 << 3) /* Bit 3: Halt programmable delay */
/* AUX_SYSIF_TIMER2BRIDGE */
#define AUX_SYSIF_TIMER2BRIDGE_BUSY (1 << 0) /* Bit 0: Status of bus transactions to AUX_TIMER2 */
/* AUX_SYSIF_SWPWRPROF */
#define AUX_SYSIF_SWPWRPROF_STAT_SHIFT (0) /* Bits 0-2: Software status bits read by the power profiler */
#define AUX_SYSIF_SWPWRPROF_STAT_MASK (7 << AUX_SYSIF_SWPWRPROF_STAT_SHIFT)
# define AUX_SYSIF_SWPWRPROF_STAT(n) ((uint32_t)(n) << AUX_SYSIF_SWPWRPROF_STAT_SHIFT)
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AUX_SYSIF_H */

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/************************************************************************************
* arch/arm/src/tiva/hardware/tiva_aux_sysif.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_SYSIF_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_SYSIF_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */
#if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) || \
defined(CONFIG_ARCH_CHIP_CC13X0)
/* These architectures do not support the AUX SYSIF block */
#elif defined(CONFIG_ARCH_CHIP_CC13X2)
# include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_sysif.h"
#else
# error "Unsupported Tiva/Stellaris/SimpleLink AUX SYSIF"
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_SYSIF_H */