From aadf6c6e167cf564a238543a2102a76991196f92 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 10 Mar 2017 17:49:32 -0600 Subject: [PATCH] STM32 F33: Fix another error in ADC base address usage. --- arch/arm/src/stm32/chip/stm32f33xxx_adc.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_adc.h b/arch/arm/src/stm32/chip/stm32f33xxx_adc.h index 7094732e76..b6609d0828 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_adc.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_adc.h @@ -151,9 +151,9 @@ #define STM32_ADC2_DIFSEL (STM32_ADC2_BASE+STM32_ADC_DIFSEL_OFFSET) #define STM32_ADC2_CALFACT (STM32_ADC2_BASE+STM32_ADC_CALFACT_OFFSET) -#define STM32_ADC12_CSR (STM32_ADC12_BASE+STM32_ADC_CSR_OFFSET) -#define STM32_ADC12_CCR (STM32_ADC12_BASE+STM32_ADC_CCR_OFFSET) -#define STM32_ADC12_CDR (STM32_ADC12_BASE+STM32_ADC_CDR_OFFSET) +#define STM32_ADC12_CSR (STM32_ADC12_CMN_BASE+STM32_ADC_CSR_OFFSET) +#define STM32_ADC12_CCR (STM32_ADC12_CMN_BASE+STM32_ADC_CCR_OFFSET) +#define STM32_ADC12_CDR (STM32_ADC12_CMN_BASE+STM32_ADC_CDR_OFFSET) /* Register Bitfield Definitions ********************************************************************/ /* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */