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i.MX6 SMP: Inter-CPU data no saved in a non-cacheable region.

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This commit is contained in:
Gregory Nutt 2016-11-26 12:04:02 -06:00
parent dda0ac8b21
commit aae306e942
11 changed files with 283 additions and 16 deletions
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57
arch/arm/include/arm/spinlock.h Normal file
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@ -0,0 +1,57 @@
/****************************************************************************
* arch/arm/include/armv7-a/spinlock.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H
#define __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_SMP
/* In SMP configurations, save spinlocks and other inter-CPU communications
* data in a non-cached memory region.
*/
# define SP_SECTION __attribute__((section(.nocache)))
#endif
#endif /* __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H */

39
arch/arm/include/armv6-m/spinlock.h Normal file
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@ -0,0 +1,39 @@
/****************************************************************************
* arch/arm/include/armv7-a/spinlock.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_ARMV6_M_SPINLOCK_H
#define __ARCH_ARM_INCLUDE_ARMV6_M_SPINLOCK_H
#endif /* __ARCH_ARM_INCLUDE_ARMV6_M_SPINLOCK_H */

39
arch/arm/include/armv7-a/spinlock.h Normal file
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@ -0,0 +1,39 @@
/****************************************************************************
* arch/arm/include/armv7-a/spinlock.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H
#define __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H
#endif /* __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H */

39
arch/arm/include/armv7-m/spinlock.h Normal file
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@ -0,0 +1,39 @@
/****************************************************************************
* arch/arm/include/armv7-a/spinlock.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_SPINLOCK_H
#define __ARCH_ARM_INCLUDE_ARMV7_M_SPINLOCK_H
#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_SPINLOCK_H */

39
arch/arm/include/armv7-r/spinlock.h Normal file
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@ -0,0 +1,39 @@
/****************************************************************************
* arch/arm/include/armv7-r/spinlock.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_ARMV7_R_SPINLOCK_H
#define __ARCH_ARM_INCLUDE_ARMV7_R_SPINLOCK_H
#endif /* __ARCH_ARM_INCLUDE_ARMV7_R_SPINLOCK_H */

20
arch/arm/include/spinlock.h
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@ -44,6 +44,26 @@
# include <stdint.h>
#endif /* __ASSEMBLY__ */
/* Include ARM architecture-specific IRQ definitions (including register
* save structure and up_irq_save()/up_irq_restore() functions)
*/
#if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8) || \
defined(CONFIG_ARCH_CORTEXA9)
# include <arch/armv7-a/spinlock.h>
#elif defined(CONFIG_ARCH_CORTEXR4) || defined(CONFIG_ARCH_CORTEXR4F) || \
defined(CONFIG_ARCH_CORTEXR5) || defined(CONFIG_ARCH_CORTEXR5F) || \
defined(CONFIG_ARCH_CORTEXR7) || defined(CONFIG_ARCH_CORTEXR7F)
# include <arch/armv7-r/spinlock.h>
#elif defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) || \
defined(CONFIG_ARCH_CORTEXM7)
# include <arch/armv7-m/spinlock.h>
#elif defined(CONFIG_ARCH_CORTEXM0)
# include <arch/armv6-m/spinlock.h>
#else
# include <arch/arm/spinlock.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/

5
arch/arm/src/armv7-a/mmu.h
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@ -601,11 +601,14 @@
#define MMU_L2_PGTABFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_RW1)
#define MMU_L1_VECTORFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PMD_PTE_DOM(0))
#define MMU_L2_VECTRWFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_RW1)
#define MMU_L2_VECTROFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_R1)
#define MMU_L2_VECTORFLAGS MMU_L2_VECTRWFLAGS
#define MMU_L1_INTERCPUFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PMD_DEVICE | \
PMD_PTE_DOM(0))
#define MMU_L2_INTERCPUFLAGS (PTE_TYPE_SMALL | PTE_DEVICE | PTE_AP_R1)
/* Mapped section size */
#define SECTION_SHIFT (20)

10
arch/arm/src/common/up_internal.h
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@ -191,6 +191,11 @@
# define _DATA_INIT &_eronly
# define _START_DATA &_sdata
# define _END_DATA &_edata
#ifdef CONFIG_SMP
# define _START_NOCACHE &_snocache
# define _END_NOCACHE &_enocache
#endif
#endif
/* This is the value used to mark the stack for subsequent stack monitoring
@ -279,6 +284,11 @@ EXTERN uint32_t _edata; /* End+1 of .data */
EXTERN uint32_t _sbss; /* Start of .bss */
EXTERN uint32_t _ebss; /* End+1 of .bss */
#ifdef CONFIG_SMP
EXTERN uint32_t _snocache; /* Start of .nocache */
EXTERN uint32_t _enocache; /* End+1 of .nocache */
#endif
/* Sometimes, functions must be executed from RAM. In this case, the following
* macro may be used (with GCC!) to specify a function that will execute from
* RAM. For example,

18
arch/arm/src/imx6/chip/imx_memorymap.h
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@ -927,9 +927,9 @@
* 0x80000000 0x803fffff 0x000002000 0x000000400 Vectors (1MiB)
* 0x80100000 0x806fffff 0x000002400 0x000001800 Paging (6MiB)
*
* If SMP is enabled, then INTERCPU_L2_PAGES pages are taken from the end
* of the Paging L2 page table to hold non-cacheable, inter-processor
* communication data.
* If SMP is enabled, then 1MiB of address spaces for the INTERCPU_L2_PAGES
* pages are taken from the end of the Paging L2 page table to hold non-
* cacheable, inter-processor communication data.
*/
/* Vector L2 page table offset/size */
@ -951,7 +951,7 @@
/* Paging L2 page table offset/size */
# define PGTABLE_L2_OFFSET 0x000002400
# define PGTABLE_L2_SIZE (0x000001800 - 4*INTERCPU_L2_PAGES)
# define PGTABLE_L2_SIZE 0x000001400
# else
/* Paging L2 page table offset/size */
@ -967,16 +967,16 @@
* ---------- ---------- ------------ ----------------------------
* 0x80000000 0x806fffff 0x000002000 0x000001c00 Paging (7MiB)
*
* If SMP is enabled, then INTERCPU_L2_PAGES pages are taken from the end
* of the Paging L2 page table to hold non-cacheable, inter-processor
* communication data.
* If SMP is enabled, then 1MiB of address spaces for the INTERCPU_L2_PAGES
* pages are taken from the end of the Paging L2 page table to hold non-
* cacheable, inter-processor communication data.
*/
# ifdef CONFIG_SMP
/* Paging L2 page table offset/size */
# define PGTABLE_L2_OFFSET 0x000002000
# define PGTABLE_L2_SIZE (0x000001c00 - 4*INTERCPU_L2_PAGES)
# define PGTABLE_L2_SIZE 0x000001800
# else
/* Paging L2 page table offset/size */
@ -1005,7 +1005,7 @@
/* Non-cached inter-processor communication data */
# define INTERCPU_L2_OFFSET (PGTABLE_L2_OFFSET + PGTABLE_L2_SIZE)
# define INTERCPU_L2_SIZE (4*INTERCPU_L2_PAGES)
# define INTERCPU_L2_SIZE (0x00000400)
/* Inter-processor communications L2 page table virtual base addresse */

25
arch/arm/src/imx6/imx_boot.c
View File

@ -254,9 +254,9 @@ static void imx_intercpu_mapping(void)
/* Now set the level 1 descriptor to refer to the level 2 page table. */
mmu_l1_setentry(VECTOR_L2_PBASE & PMD_PTE_PADDR_MASK,
mmu_l1_setentry(INTERCPU_PBASE & PMD_PTE_PADDR_MASK,
INTERCPU_VADDR & PMD_PTE_PADDR_MASK,
MMU_L1_PGTABFLAGS);
MMU_L1_INTERCPUFLAGS);
}
#else
/* No inter-cpu communications area */
@ -428,8 +428,10 @@ static inline void imx_wdtdisable(void)
void arm_boot(void)
{
#ifdef CONFIG_ARCH_RAMFUNCS
#if defined(CONFIG_ARCH_RAMFUNCS)
const uint32_t *src;
#endif
#if defined(CONFIG_ARCH_RAMFUNCS) || defined(CONFIG_SMP)
uint32_t *dest;
#endif
@ -541,10 +543,21 @@ void arm_boot(void)
imx_lowputc('L');
#endif
#ifdef CONFIG_SMP
/* Initialize the uncached, inter-CPU communications area */
for (dest = &_snocache; dest < &_enocache; )
{
*dest++ = 0;
}
imx_lowputc('M');
#endif
/* Perform common, low-level chip initialization (might do nothing) */
imx_lowsetup();
imx_lowputc('M');
imx_lowputc('N');
#ifdef USE_EARLYSERIALINIT
/* Perform early serial initialization if we are going to use the serial
@ -552,7 +565,7 @@ void arm_boot(void)
*/
imx_earlyserialinit();
imx_lowputc('N');
imx_lowputc('O');
#endif
/* Now we can enable all other CPUs. The enabled CPUs will start execution
@ -561,6 +574,6 @@ void arm_boot(void)
*/
imx_cpu_enable();
imx_lowputc('O');
imx_lowputc('P');
imx_lowputc('\n');
}

8
configs/sabre-6quad/scripts/dramboot.ld
View File

@ -46,6 +46,7 @@ MEMORY
{
oscram (W!RX) : ORIGIN = 0x00900000, LENGTH = 256K - 16K
ddr3 (W!RX) : ORIGIN = 0x10800000, LENGTH = 1024M - 8M
nocache (WR) : ORIGIN = 0x80600000, LENGTH = 4K
}
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
@ -122,6 +123,13 @@ SECTIONS
_enoinit = ABSOLUTE(.);
} > ddr3
.nocache :
{
_snocache = ABSOLUTE(.);
*(.nocache)
_enocache = ABSOLUTE(.);
} > nocahce
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }