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Memory map clean-up

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3011 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-10-13 22:41:31 +00:00
parent d1334d6e14
commit aaf562d567
2 changed files with 70 additions and 37 deletions
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94
arch/avr/src/at91uc3/at91uc3_gpio.h
View File

@ -117,6 +117,12 @@
#define AVR32_GPIO3_BASE (AVR32_GPIO_BASE+AVR32_GPIO3_OFFSET)
#define AVR32_GPIO4_BASE (AVR32_GPIO_BASE+AVR32_GPIO4_OFFSET)
/* Local bus mapped GPIO ports */
#define AVR32_GPIOn_LBUS_BASE(n) (AVR32_GPIO_LBUS_BASE+AVR32_GPIO_OFFSET(n))
#define AVR32_GPIO0_LBUS_BASE (AVR32_GPIO_LBUS_BASE+AVR32_GPIO0_OFFSET)
#define AVR32_GPIO1_LBUS_BASE (AVR32_GPIO_LBUS_BASE+AVR32_GPIO1_OFFSET)
/* Register Addresses ***************************************************************/
#define AVR32_GPIO_GPER(n) (AVR32_GPIOn_BASE(n)+AVR32_GPIO_GPER_OFFSET)
@ -383,43 +389,65 @@
#define AVR32_GPIO4_IFR (AVR32_GPIO4_BASE+AVR32_GPIO_IFR_OFFSET)
#define AVR32_GPIO4_IFRC (AVR32_GPIO4_BASE+AVR32_GPIO_IFRC_OFFSET)
/* Local bus mapped GPIO registers */
#define AVR32_GPIO0_LBUS_ODER (AVR32_GPIO0_LBUS_BASE+AVR32_GPIO_ODER_OFFSET)
#define AVR32_GPIO0_LBUS_ODERS (AVR32_GPIO0_LBUS_BASE+AVR32_GPIO_ODERS_OFFSET)
#define AVR32_GPIO0_LBUS_ODERC (AVR32_GPIO0_LBUS_BASE+AVR32_GPIO_ODERC_OFFSET)
#define AVR32_GPIO0_LBUS_ODERT (AVR32_GPIO0_LBUS_BASE+AVR32_GPIO_ODERT_OFFSET)
#define AVR32_GPIO0_LBUS_OVR (AVR32_GPIO0_LBUS_BASE+AVR32_GPIO_OVR_OFFSET)
#define AVR32_GPIO0_LBUS_OVRS (AVR32_GPIO0_LBUS_BASE+AVR32_GPIO_OVRS_OFFSET)
#define AVR32_GPIO0_LBUS_OVRC (AVR32_GPIO0_LBUS_BASE+AVR32_GPIO_OVRC_OFFSET)
#define AVR32_GPIO0_LBUS_OVRT (AVR32_GPIO0_LBUS_BASE+AVR32_GPIO_OVRT_OFFSET)
#define AVR32_GPIO0_LBUS_PVR (AVR32_GPIO0_LBUS_BASE+AVR32_GPIO_PVR_OFFSET)
#define AVR32_GPIO1_LBUS_ODER (AVR32_GPIO1_LBUS_BASE+AVR32_GPIO_ODER_OFFSET)
#define AVR32_GPIO1_LBUS_ODERS (AVR32_GPIO1_LBUS_BASE+AVR32_GPIO_ODERS_OFFSET)
#define AVR32_GPIO1_LBUS_ODERC (AVR32_GPIO1_LBUS_BASE+AVR32_GPIO_ODERC_OFFSET)
#define AVR32_GPIO1_LBUS_ODERT (AVR32_GPIO1_LBUS_BASE+AVR32_GPIO_ODERT_OFFSET)
#define AVR32_GPIO1_LBUS_OVR (AVR32_GPIO1_LBUS_BASE+AVR32_GPIO_OVR_OFFSET)
#define AVR32_GPIO1_LBUS_OVRS (AVR32_GPIO1_LBUS_BASE+AVR32_GPIO_OVRS_OFFSET)
#define AVR32_GPIO1_LBUS_OVRC (AVR32_GPIO1_LBUS_BASE+AVR32_GPIO_OVRC_OFFSET)
#define AVR32_GPIO1_LBUS_OVRT (AVR32_GPIO1_LBUS_BASE+AVR32_GPIO_OVRT_OFFSET)
#define AVR32_GPIO1_LBUS_PVR (AVR32_GPIO1_LBUS_BASE+AVR32_GPIO_PVR_OFFSET)
/* Register Bit-field Definitions ***************************************************/
/* For all registers, there are 32 bits, each associated with one pin on the port. */
#define GPIO_PIN(n) (1 << (n))
#define GPIO_PIN0 (1 << 0)
#define GPIO_PIN1 (1 << 1)
#define GPIO_PIN2 (1 << 2)
#define GPIO_PIN3 (1 << 3)
#define GPIO_PIN4 (1 << 4)
#define GPIO_PIN5 (1 << 5)
#define GPIO_PIN6 (1 << 6)
#define GPIO_PIN7 (1 << 7)
#define GPIO_PIN8 (1 << 8)
#define GPIO_PIN9 (1 << 9)
#define GPIO_PIN10 (1 << 10)
#define GPIO_PIN11 (1 << 11)
#define GPIO_PIN12 (1 << 12)
#define GPIO_PIN13 (1 << 13)
#define GPIO_PIN14 (1 << 14)
#define GPIO_PIN15 (1 << 15)
#define GPIO_PIN16 (1 << 16)
#define GPIO_PIN17 (1 << 17)
#define GPIO_PIN18 (1 << 18)
#define GPIO_PIN19 (1 << 19)
#define GPIO_PIN20 (1 << 20)
#define GPIO_PIN21 (1 << 21)
#define GPIO_PIN22 (1 << 22)
#define GPIO_PIN23 (1 << 23)
#define GPIO_PIN24 (1 << 24)
#define GPIO_PIN25 (1 << 25)
#define GPIO_PIN26 (1 << 26)
#define GPIO_PIN27 (1 << 27)
#define GPIO_PIN28 (1 << 28)
#define GPIO_PIN29 (1 << 29)
#define GPIO_PIN30 (1 << 30)
#define GPIO_PIN31 (1 << 31)
#define GPIO_PIN(n) (1 << (n))
#define GPIO_PIN0 (1 << 0)
#define GPIO_PIN1 (1 << 1)
#define GPIO_PIN2 (1 << 2)
#define GPIO_PIN3 (1 << 3)
#define GPIO_PIN4 (1 << 4)
#define GPIO_PIN5 (1 << 5)
#define GPIO_PIN6 (1 << 6)
#define GPIO_PIN7 (1 << 7)
#define GPIO_PIN8 (1 << 8)
#define GPIO_PIN9 (1 << 9)
#define GPIO_PIN10 (1 << 10)
#define GPIO_PIN11 (1 << 11)
#define GPIO_PIN12 (1 << 12)
#define GPIO_PIN13 (1 << 13)
#define GPIO_PIN14 (1 << 14)
#define GPIO_PIN15 (1 << 15)
#define GPIO_PIN16 (1 << 16)
#define GPIO_PIN17 (1 << 17)
#define GPIO_PIN18 (1 << 18)
#define GPIO_PIN19 (1 << 19)
#define GPIO_PIN20 (1 << 20)
#define GPIO_PIN21 (1 << 21)
#define GPIO_PIN22 (1 << 22)
#define GPIO_PIN23 (1 << 23)
#define GPIO_PIN24 (1 << 24)
#define GPIO_PIN25 (1 << 25)
#define GPIO_PIN26 (1 << 26)
#define GPIO_PIN27 (1 << 27)
#define GPIO_PIN28 (1 << 28)
#define GPIO_PIN29 (1 << 29)
#define GPIO_PIN30 (1 << 30)
#define GPIO_PIN31 (1 << 31)
/************************************************************************************
* Public Types

13
arch/avr/src/at91uc3/at91uc3_memorymap.h
View File

@ -48,10 +48,15 @@
/* Physical memory map */
#define AVR32_ONCHIP_FLASH_BASE 0x80000000 /* 512Kb Flash Array */
#define AVR32_ONCHIP_SRAM_BASE 0x00000000 /* 16-64Kb SRAM */
#define AVR32_GPIO_LBUS_BASE 0x40000000 /* Local bus mapped GPIO registers */
#define AVR32_ONCHIP_FLASH_BASE 0x80000000 /* 64-512Kb Flash Array */
# define AVR32_APPL_BASE 0x80002000 /* 8Kb offset to application w/bootloader */
#define AVR32_USER_FLASH_BASE 0x80800000 /* Flash User Page */
# define AVR32_USER_FLASH_BASE 0x80800000 /* Flash User Page */
# define AVR32_BTLDR_CONFIG 0x808001fc /* Bootloader configuration word */
#define AVR32_USBDATA_BASE 0xd0000000 /* USB data (64Kb) */
#define AVR32_HSBPB_BRIDGEB 0xfffe0000 /* HSB-PB Bridge B (64Kb) */
#define AVR32_HSBPB_BRIDGEA 0xffff0000 /* HSB-PB Bridge A (64Kb) */
/* Memory map for systems without an MMU */
@ -63,9 +68,9 @@
/* Reset vector addess */
#if defined(CONFIG_ARCH_CHIP_AT91UC3A)
# define AVR32_VECTOR_BASE 0x80000000
# define AVR32_VECTOR_BASE AVR32_P1_BASE
#elif defined(CONFIG_ARCH_CHIP_AT91UC3B)
# define AVR32_VECTOR_BASE 0xa0000000
# define AVR32_VECTOR_BASE AVR32_P2_BASE
#else
# warning "Unknown vector base address"
#endif