fix: arch/.../stm32h7x3xx_memorymap.h invalid address map for fdcan
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@ -125,11 +125,11 @@
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#define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff: DAC */
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#define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff: DAC */
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#define STM32_UART7_BASE 0x40007800 /* 0x40007800-0x40007bff: UART7 */
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#define STM32_UART7_BASE 0x40007800 /* 0x40007800-0x40007bff: UART7 */
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#define STM32_UART8_BASE 0x40007c00 /* 0x40007c00-0x40007fff: UART8 */
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#define STM32_UART8_BASE 0x40007c00 /* 0x40007c00-0x40007fff: UART8 */
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#define STM32_CRS_BASE 0x40008400 /* 0x40007c00-0x40007fff: CRS */
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#define STM32_CRS_BASE 0x40008400 /* 0x40008400-0x400087ff: CRS */
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#define STM32_SWPMI_BASE 0x40008800 /* 0x40008800 - 0x40008bff SWPMI Section */
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#define STM32_SWPMI_BASE 0x40008800 /* 0x40008800 - 0x40008bff SWPMI Section */
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#define STM32_OPAMP_BASE 0x40009000 /* 0x40009000 - 0x400093ff OPAMP Section */
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#define STM32_OPAMP_BASE 0x40009000 /* 0x40009000 - 0x400093ff OPAMP Section */
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#define STM32_MDIOS_BASE 0x4000a000 /* 0x40009400 - 0x400097ff MDIOS Section */
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#define STM32_MDIOS_BASE 0x40009400 /* 0x40009400 - 0x400097ff MDIOS Section */
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#define STM32_FDCAN1_BASE 0x40008400 /* 0x4000a000 - 0x4000a3ff FDCAN1 Section */
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#define STM32_FDCAN1_BASE 0x4000a000 /* 0x4000a000 - 0x4000a3ff FDCAN1 Section */
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#define STM32_FDCAN2_BASE 0x4000a400 /* 0x4000a400 - 0x4000A7ff FDCAN2 Section */
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#define STM32_FDCAN2_BASE 0x4000a400 /* 0x4000a400 - 0x4000A7ff FDCAN2 Section */
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#define STM32_CANCCU_BASE 0x4000a800 /* 0x4000a800 - 0x4000abff CAN CCU Section */
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#define STM32_CANCCU_BASE 0x4000a800 /* 0x4000a800 - 0x4000abff CAN CCU Section */
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#define STM32_CANRAM_BASE 0x4000ac00 /* 0x4000ac00 - 0x4000d3ff CAN Message RAM */
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#define STM32_CANRAM_BASE 0x4000ac00 /* 0x4000ac00 - 0x4000d3ff CAN Message RAM */
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