sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

LPC1788 updates from Rommel Marcelo

Browse Source 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5696 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2013-03-02 00:59:28 +00:00
parent 62d7b325f4
commit ac23001d25
3 changed files with 15 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
configs/open1788/include/board.h
View File

@ -85,8 +85,8 @@
* The input to the divider (PLLCLK) will be determined by the PLL output.
*/
#define BOARD_CCLKCFG_DIVIDER 6
#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_CCLKDIV_SHIFT)
#define BOARD_CCLKCFG_DIVIDER 1
#define BOARD_CCLKCFG_VALUE (BOARD_CCLKCFG_DIVIDER | SYSCON_CCLKCFG_CCLKSEL)
/* PLL0. PLL0 is used to generate the CPU clock (PLLCLK).
*
@ -109,11 +109,11 @@
/* PLL1 : PLL1 is used to generate clock for the USB */
#undef CONFIG_LPC17_PLL1
#define CONFIG_LPC17_PLL1 1
#define BOARD_PLL1CFG_MSEL 4
#define BOARD_PLL1CFG_PSEL 2
#define BOARD_PLL1CFG_VALUE \
#undef CONFIG_LPC17_PLL1
//~ #define CONFIG_LPC17_PLL1 1
#define BOARD_PLL1CFG_MSEL 4
#define BOARD_PLL1CFG_PSEL 2
#define BOARD_PLL1CFG_VALUE \
(((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \
((BOARD_PLL1CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT))
@ -135,7 +135,7 @@
/* Flash access use 6 CPU clocks - Safe for any allowed conditions */
#define BOARD_FLASHCFG_VALUE SYSCON_FLASHCFG_TIM_5
#define BOARD_FLASHCFG_VALUE (SYSCON_FLASHCFG_TIM_5 | 0x03a)
/* Ethernet configuration */

2
configs/open1788/ostest/setenv.sh
View File

@ -65,7 +65,7 @@ fi
export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
# The Olimex-lpc1766stk/tools directory
export LPCTOOL_DIR="${WD}/configs/olimex-lpc1766stk/tools"
export LPCTOOL_DIR="${WD}/configs/open1788/tools"
# Add the path to the toolchain and tools directory to the PATH varialble
export PATH="${TOOLCHAIN_BIN}:${LPCTOOL_DIR}:/sbin:/usr/sbin:${PATH_ORIG}"

22
configs/open1788/scripts/ld.script
View File

@ -37,8 +37,8 @@
/* The LPC1788 has 512Kb of FLASH beginning at address 0x0000:0000 and
* 96Kb of total SRAM: 64Kb of SRAM in the CPU block beginning at address
* 0x10000000 and 32Kb of Peripheral SRAM in two banks, 8Kb at addresses
* 0x20000000 bank0 first and 8kb at 0x20020000 at bank0 second. And 16Kb
* at 0x20040000 on bank1.
* 0x20000000 bank0 first and 8kb at 0x20002000 at bank0 second. And 16Kb
* at 0x20004000 on bank1.
*
* Here we assume that .data and .bss will all fit into the 64Kb CPU SRAM
* address range.
@ -48,8 +48,9 @@ MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
PSRAM0 (rwx) : ORIGIN = 0x20000000, LENGTH = 16K /* Peripheral SRAM Bank 0 */
PSRAM1 (rwx) : ORIGIN = 0x20040000, LENGTH = 16K /* Peripheral SRAM Bank 1 */
AHBRAM8_B0A(rwx): ORIGIN = 0x20000000, LENGTH = 8K
AHBRAM8_B0B(rwx): ORIGIN = 0x20002000, LENGTH = 8K
AHBRAM16(rwx): ORIGIN = 0x20004000, LENGTH = 16K
}
OUTPUT_ARCH(arm)
@ -86,6 +87,7 @@ SECTIONS
.ARM.exidx : {
*(.ARM.exidx*)
} > FLASH
__exidx_end = ABSOLUTE(.);
_eronly = ABSOLUTE(.);
@ -105,20 +107,8 @@ SECTIONS
*(COMMON)
_ebss = ABSOLUTE(.);
} > SRAM
/*
.psram0 (NOLOAD) :
{
*(.psram0)
. = ALIGN(4)
} > PSRAM0
.psram1 (NOLOAD) :
{
*(.psram1)
. = ALIGN(4)
} > PSRAM1
*/
/* Stabs debugging sections */
.stab 0 : { *(.stab) }