sergiotarxz/nuttx
sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

arch/mips: Fix the SW0 priority set by commit eb1adca

Browse Source 
It must be strictly greater than IPL to get serviced.
This commit is contained in:
Ouss4 2020-02-21 23:47:07 +00:00 committed by patacongo
parent 7516f76422
commit ac4049682f
5 changed files with 9 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/mips/include/mips32/cp0.h
View File

@ -218,7 +218,7 @@
# define CP0_STATUS_IPL_SHIFT (10) /* Bits 10-16+18: Interrupt Mask */
# define CP0_STATUS_IPL_MASK (0x17f << CP0_STATUS_IPL_SHIFT)
# define CP0_STATUS_IPL_ENALL (0x00 << CP0_STATUS_IPL_SHIFT)
# define CP0_STATUS_IPL_SW0 ((CHIP_MAX_PRIORITY - 1) << CP0_STATUS_IPL_SHIFT)
# define CP0_STATUS_IPL_SW0 ((CHIP_SW0_PRIORITY - 1) << CP0_STATUS_IPL_SHIFT)
# define CP0_STATUS_IPL_DISALL (CHIP_MAX_PRIORITY << CP0_STATUS_IPL_SHIFT)
# define CP0_STATUS_INT_ENALL CP0_STATUS_IPL_ENALL
# define CP0_STATUS_INT_SW0 CP0_STATUS_IPL_SW0

5
arch/mips/include/pic32mx/chip.h
View File

@ -2405,8 +2405,9 @@
* interrupts.
*/
#define CHIP_MIN_PRIORITY 1 /* Minimum priority. */
#define CHIP_MAX_PRIORITY 7 /* Maximum priority. */
#define CHIP_MIN_PRIORITY 1 /* Minimum priority. */
#define CHIP_MAX_PRIORITY 7 /* Maximum priority. */
#define CHIP_SW0_PRIORITY (CHIP_MAX_PRIORITY - 1) /* SW0 priority. */
/****************************************************************************
* Public Types

5
arch/mips/include/pic32mz/chip.h
View File

@ -203,8 +203,9 @@
* interrupts.
*/
#define CHIP_MIN_PRIORITY 1 /* Minimum priority. */
#define CHIP_MAX_PRIORITY 7 /* Maximum priority. */
#define CHIP_MIN_PRIORITY 1 /* Minimum priority. */
#define CHIP_MAX_PRIORITY 7 /* Maximum priority. */
#define CHIP_SW0_PRIORITY (CHIP_MAX_PRIORITY - 1) /* SW0 priority. */
/****************************************************************************
* Public Types

2
arch/mips/src/pic32mx/pic32mx-irq.c
View File

@ -113,7 +113,7 @@ void up_irqinitialize(void)
/* Set the Software Interrupt0 to a special priority */
up_prioritize_irq(PIC32MX_IRQSRC_CS0, (CHIP_MAX_PRIORITY - 1) << 2);
up_prioritize_irq(PIC32MX_IRQSRC_CS0, (CHIP_SW0_PRIORITY << 2));
/* Set the BEV bit in the STATUS register */

2
arch/mips/src/pic32mz/pic32mz-irq.c
View File

@ -202,7 +202,7 @@ void up_irqinitialize(void)
/* Set the Software Interrupt0 to a special priority */
pic32mz_prioritize_irq(PIC32MZ_IRQ_CS0, (CHIP_MAX_PRIORITY - 1) << 2);
pic32mz_prioritize_irq(PIC32MZ_IRQ_CS0, (CHIP_SW0_PRIORITY << 2));
/* Set the BEV bit in the STATUS register */