From ac4049682fe024768daa1129b7ba04a1c01613f0 Mon Sep 17 00:00:00 2001 From: Ouss4 Date: Fri, 21 Feb 2020 23:47:07 +0000 Subject: [PATCH] arch/mips: Fix the SW0 priority set by commit eb1adca It must be strictly greater than IPL to get serviced. --- arch/mips/include/mips32/cp0.h | 2 +- arch/mips/include/pic32mx/chip.h | 5 +++-- arch/mips/include/pic32mz/chip.h | 5 +++-- arch/mips/src/pic32mx/pic32mx-irq.c | 2 +- arch/mips/src/pic32mz/pic32mz-irq.c | 2 +- 5 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/mips/include/mips32/cp0.h b/arch/mips/include/mips32/cp0.h index 4270e9b7fc..1cbb520d40 100644 --- a/arch/mips/include/mips32/cp0.h +++ b/arch/mips/include/mips32/cp0.h @@ -218,7 +218,7 @@ # define CP0_STATUS_IPL_SHIFT (10) /* Bits 10-16+18: Interrupt Mask */ # define CP0_STATUS_IPL_MASK (0x17f << CP0_STATUS_IPL_SHIFT) # define CP0_STATUS_IPL_ENALL (0x00 << CP0_STATUS_IPL_SHIFT) -# define CP0_STATUS_IPL_SW0 ((CHIP_MAX_PRIORITY - 1) << CP0_STATUS_IPL_SHIFT) +# define CP0_STATUS_IPL_SW0 ((CHIP_SW0_PRIORITY - 1) << CP0_STATUS_IPL_SHIFT) # define CP0_STATUS_IPL_DISALL (CHIP_MAX_PRIORITY << CP0_STATUS_IPL_SHIFT) # define CP0_STATUS_INT_ENALL CP0_STATUS_IPL_ENALL # define CP0_STATUS_INT_SW0 CP0_STATUS_IPL_SW0 diff --git a/arch/mips/include/pic32mx/chip.h b/arch/mips/include/pic32mx/chip.h index d261d895b1..07fb7c274c 100644 --- a/arch/mips/include/pic32mx/chip.h +++ b/arch/mips/include/pic32mx/chip.h @@ -2405,8 +2405,9 @@ * interrupts. */ -#define CHIP_MIN_PRIORITY 1 /* Minimum priority. */ -#define CHIP_MAX_PRIORITY 7 /* Maximum priority. */ +#define CHIP_MIN_PRIORITY 1 /* Minimum priority. */ +#define CHIP_MAX_PRIORITY 7 /* Maximum priority. */ +#define CHIP_SW0_PRIORITY (CHIP_MAX_PRIORITY - 1) /* SW0 priority. */ /**************************************************************************** * Public Types diff --git a/arch/mips/include/pic32mz/chip.h b/arch/mips/include/pic32mz/chip.h index 7a8a5bb38e..b958140a0e 100644 --- a/arch/mips/include/pic32mz/chip.h +++ b/arch/mips/include/pic32mz/chip.h @@ -203,8 +203,9 @@ * interrupts. */ -#define CHIP_MIN_PRIORITY 1 /* Minimum priority. */ -#define CHIP_MAX_PRIORITY 7 /* Maximum priority. */ +#define CHIP_MIN_PRIORITY 1 /* Minimum priority. */ +#define CHIP_MAX_PRIORITY 7 /* Maximum priority. */ +#define CHIP_SW0_PRIORITY (CHIP_MAX_PRIORITY - 1) /* SW0 priority. */ /**************************************************************************** * Public Types diff --git a/arch/mips/src/pic32mx/pic32mx-irq.c b/arch/mips/src/pic32mx/pic32mx-irq.c index 7f00cedcb2..98d11b40a7 100644 --- a/arch/mips/src/pic32mx/pic32mx-irq.c +++ b/arch/mips/src/pic32mx/pic32mx-irq.c @@ -113,7 +113,7 @@ void up_irqinitialize(void) /* Set the Software Interrupt0 to a special priority */ - up_prioritize_irq(PIC32MX_IRQSRC_CS0, (CHIP_MAX_PRIORITY - 1) << 2); + up_prioritize_irq(PIC32MX_IRQSRC_CS0, (CHIP_SW0_PRIORITY << 2)); /* Set the BEV bit in the STATUS register */ diff --git a/arch/mips/src/pic32mz/pic32mz-irq.c b/arch/mips/src/pic32mz/pic32mz-irq.c index 71aac534ca..e3e84e6ed3 100644 --- a/arch/mips/src/pic32mz/pic32mz-irq.c +++ b/arch/mips/src/pic32mz/pic32mz-irq.c @@ -202,7 +202,7 @@ void up_irqinitialize(void) /* Set the Software Interrupt0 to a special priority */ - pic32mz_prioritize_irq(PIC32MZ_IRQ_CS0, (CHIP_MAX_PRIORITY - 1) << 2); + pic32mz_prioritize_irq(PIC32MZ_IRQ_CS0, (CHIP_SW0_PRIORITY << 2)); /* Set the BEV bit in the STATUS register */