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arch/mips: Fix the SW0 priority set by commit eb1adca

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It must be strictly greater than IPL to get serviced.
This commit is contained in:
Ouss4 2020-02-21 23:47:07 +00:00 committed by patacongo
parent 7516f76422
commit ac4049682f
5 changed files with 9 additions and 7 deletions
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2
arch/mips/include/mips32/cp0.h
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@ -218,7 +218,7 @@
# define CP0_STATUS_IPL_SHIFT (10) /* Bits 10-16+18: Interrupt Mask */ # define CP0_STATUS_IPL_SHIFT (10) /* Bits 10-16+18: Interrupt Mask */
# define CP0_STATUS_IPL_MASK (0x17f << CP0_STATUS_IPL_SHIFT) # define CP0_STATUS_IPL_MASK (0x17f << CP0_STATUS_IPL_SHIFT)
# define CP0_STATUS_IPL_ENALL (0x00 << CP0_STATUS_IPL_SHIFT) # define CP0_STATUS_IPL_ENALL (0x00 << CP0_STATUS_IPL_SHIFT)
# define CP0_STATUS_IPL_SW0 ((CHIP_MAX_PRIORITY - 1) << CP0_STATUS_IPL_SHIFT) # define CP0_STATUS_IPL_SW0 ((CHIP_SW0_PRIORITY - 1) << CP0_STATUS_IPL_SHIFT)
# define CP0_STATUS_IPL_DISALL (CHIP_MAX_PRIORITY << CP0_STATUS_IPL_SHIFT) # define CP0_STATUS_IPL_DISALL (CHIP_MAX_PRIORITY << CP0_STATUS_IPL_SHIFT)
# define CP0_STATUS_INT_ENALL CP0_STATUS_IPL_ENALL # define CP0_STATUS_INT_ENALL CP0_STATUS_IPL_ENALL
# define CP0_STATUS_INT_SW0 CP0_STATUS_IPL_SW0 # define CP0_STATUS_INT_SW0 CP0_STATUS_IPL_SW0

5
arch/mips/include/pic32mx/chip.h
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@ -2405,8 +2405,9 @@
* interrupts. * interrupts.
*/ */
#define CHIP_MIN_PRIORITY 1 /* Minimum priority. */ #define CHIP_MIN_PRIORITY 1 /* Minimum priority. */
#define CHIP_MAX_PRIORITY 7 /* Maximum priority. */ #define CHIP_MAX_PRIORITY 7 /* Maximum priority. */
#define CHIP_SW0_PRIORITY (CHIP_MAX_PRIORITY - 1) /* SW0 priority. */
/**************************************************************************** /****************************************************************************
* Public Types * Public Types

5
arch/mips/include/pic32mz/chip.h
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@ -203,8 +203,9 @@
* interrupts. * interrupts.
*/ */
#define CHIP_MIN_PRIORITY 1 /* Minimum priority. */ #define CHIP_MIN_PRIORITY 1 /* Minimum priority. */
#define CHIP_MAX_PRIORITY 7 /* Maximum priority. */ #define CHIP_MAX_PRIORITY 7 /* Maximum priority. */
#define CHIP_SW0_PRIORITY (CHIP_MAX_PRIORITY - 1) /* SW0 priority. */
/**************************************************************************** /****************************************************************************
* Public Types * Public Types

2
arch/mips/src/pic32mx/pic32mx-irq.c
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@ -113,7 +113,7 @@ void up_irqinitialize(void)
/* Set the Software Interrupt0 to a special priority */ /* Set the Software Interrupt0 to a special priority */
up_prioritize_irq(PIC32MX_IRQSRC_CS0, (CHIP_MAX_PRIORITY - 1) << 2); up_prioritize_irq(PIC32MX_IRQSRC_CS0, (CHIP_SW0_PRIORITY << 2));
/* Set the BEV bit in the STATUS register */ /* Set the BEV bit in the STATUS register */

2
arch/mips/src/pic32mz/pic32mz-irq.c
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@ -202,7 +202,7 @@ void up_irqinitialize(void)
/* Set the Software Interrupt0 to a special priority */ /* Set the Software Interrupt0 to a special priority */
pic32mz_prioritize_irq(PIC32MZ_IRQ_CS0, (CHIP_MAX_PRIORITY - 1) << 2); pic32mz_prioritize_irq(PIC32MZ_IRQ_CS0, (CHIP_SW0_PRIORITY << 2));
/* Set the BEV bit in the STATUS register */ /* Set the BEV bit in the STATUS register */