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arch/mips: Clear the software interrupt through a common function

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implemented in the chip specific code.
This commit is contained in:
Ouss4 2020-02-10 17:50:40 +00:00 committed by patacongo
parent 90043390ff
commit ac4e6618bb
4 changed files with 29 additions and 8 deletions
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1
arch/mips/src/common/up_internal.h
View File

@ -237,6 +237,7 @@ void up_sigdeliver(void);
bool up_pending_irq(int irq);
void up_clrpend_irq(int irq);
void up_clrpend_sw0(void);
/* DMA */

10
arch/mips/src/mips32/up_swint0.c
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@ -299,15 +299,9 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
}
#endif
/* Clear the pending software interrupt 0 in the PIC32 interrupt block.
* REVISIT: Does this PIC32 logic really have to be in the MIPS32 code?
*/
/* Clear the pending software interrupt 0 */
#if defined(CONFIG_ARCH_CHIP_PIC32MX)
up_clrpend_irq(PIC32MX_IRQSRC_CS0);
#elif defined(CONFIG_ARCH_CHIP_PIC32MZ)
up_clrpend_irq(PIC32MZ_IRQ_CS0);
#endif
up_clrpend_sw0();
/* And reset the software interrupt bit in the MIPS CAUSE register */

13
arch/mips/src/pic32mx/pic32mx-irq.c
View File

@ -412,6 +412,19 @@ void up_clrpend_irq(int irq)
}
}
/****************************************************************************
* Name: up_clrpend_sw0
*
* Description:
* Clear a pending Software Interrupt.
*
****************************************************************************/
void up_clrpend_sw0(void)
{
up_clrpend_irq(PIC32MX_IRQSRC_CS0);
}
/****************************************************************************
* Name: up_prioritize_irq
*

13
arch/mips/src/pic32mz/pic32mz-irq.c
View File

@ -399,6 +399,19 @@ void up_clrpend_irq(int irq)
}
}
/****************************************************************************
* Name: up_clrpend_sw0
*
* Description:
* Clear a pending Software Interrupt.
*
****************************************************************************/
void up_clrpend_sw0(void)
{
up_clrpend_irq(PIC32MZ_IRQ_CS0);
}
/****************************************************************************
* Name: up_prioritize_irq
*