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Add A/D register definitions

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@202 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2007-05-05 01:55:07 +00:00
parent d97b308dca
commit ac68b7eed4
2 changed files with 49 additions and 14 deletions
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19
arch/arm/src/lpc214x/chip.h
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@ -62,7 +62,9 @@
#define LPC214X_UART0_BASE 0xe000c000 /* UART0 Base Address */
#define LPC214X_UART1_BASE 0xe0010000 /* UART1 Base Address */
#define LPC214X_PINSEL_BASE 0xc002c000 /* Pin funtion select registers */
#define LPC214X_PINSEL_BASE 0xe002c000 /* Pin funtion select registers */
#define LPC214X_AD0_BASE 0xe0034000 /* Analog to Digital Converter 0 Base Address*/
#define LPC214X_AD1_BASE 0xe0060000 /* Analog to Digital Converter 1 Base Address */
#define LPC214X_MAM_BASE 0xe01fc000 /* Memory Accelerator Module (MAM) Base Address */
#define LPC214X_MEMMAP 0xe01fc040 /* Memory Mapping Control */
#define LPC214X_PLL_BASE 0xe01fc080 /* Phase Locked Loop (PLL) Base Address */
@ -94,6 +96,21 @@
#define LPC214X_PINSEL1_OFFSET 0x04 /* Pin function select register 1 */
#define LPC214X_PINSEL2_OFFSET 0x14 /* Pin function select register 2 */
/* Analog to Digital (AD) Converter registger offsets */
#define LPC214X_AD_ADCR_OFFSET 0x00 /* A/D Control Register */
#define LPC214X_AD_ADGDR_OFFSET 0x04 /* A/D Global Data Register (only one common registger!) */
#define LPC214X_AD_ADGSR_OFFSET 0x08 /* A/D Global Start Register */
#define LPC214X_AD_ADINTEN_OFFSET 0x0c /* A/D Interrupt Enable Register */
#define LPC214X_AD_ADDR0_OFFSET 0x10 /* A/D Chanel 0 Data Register */
#define LPC214X_AD_ADDR1_OFFSET 0x14 /* A/D Chanel 0 Data Register */
#define LPC214X_AD_ADDR2_OFFSET 0x18 /* A/D Chanel 0 Data Register */
#define LPC214X_AD_ADDR3_OFFSET 0x1c /* A/D Chanel 0 Data Register */
#define LPC214X_AD_ADDR4_OFFSET 0x20 /* A/D Chanel 0 Data Register */
#define LPC214X_AD_ADDR5_OFFSET 0x24 /* A/D Chanel 0 Data Register */
#define LPC214X_AD_ADDR6_OFFSET 0x28 /* A/D Chanel 0 Data Register */
#define LPC214X_AD_ADDR7_OFFSET 0x2c /* A/D Chanel 0 Data Register */
#define LPC214X_AD_ADSTAT_OFFSET 0x30 /* A/D Status Register */
/* Pin function select registers (these are normally referenced as offsets) */
#define LPC214X_PINSEL0 (LPC214X_PINSEL_BASE + LPC214X_PINSEL0_OFFSET)

44
arch/arm/src/lpc214x/lpc214x_head.S
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@ -135,15 +135,6 @@
# define CONFIG_VPBDIV_VALUE 0x00000001
#endif
/* External Memory Pins definitions
*
* CS0..3, OE, WE, BLS0..3, D0..31, A2..23, JTAG Pins
*/
#ifndef CONFIG_PINSEL2_VALUE /* Can be selected from config file */
# define CONFIG_PINSEL2_VALUE 0x0e6149e4
#endif
/* External Memory Controller (EMC) initialization values
*
* Bank Configuration n (BCFG0..3)
@ -177,8 +168,35 @@
# define CONFIG_AD0CR_VALUE 0x00200402; /* Setup A/D: 10-bit AIN0 @ 3MHz */
#endif
#ifndef CONFIG_PINSEL1_VALUE
# define CONFIG_PINSEL1_VALUE 0x01000000; /* Enable DAC */
/* GIO Pin Selection Register settings
*
* PINSEL0 configures GPIO 0.0 through 0.15
*/
#ifndef CONFIG_PINSEL0_VALUE /* Can be selected from config file */
# define CONFIG_PINSEL0_VALUE 0x00000000 /* Reset value */
#endif
/* PINSEL1 configures GPIO 0.16 through 0.30 and GPO */
#ifndef CONFIG_PINSEL1_VALUE /* Can be selected from the config file */
# ifdef CONFIG_ADC_SETUP
# define CONFIG_PINSEL1_VALUE 0x01000000; /* Enable DAC */
# elsel
# define CONFIG_PINSEL1_VALUE 0x00000000; /* Reset value */
# endif
#endif
/* External Memory Pins definitions
* BIT 0:1 Reserved
* BIT 2 GPIO/DEBUG
* BIT 3 GPIO/TRACE
* BIT 31:4 Reserved
* CS0..3, OE, WE, BLS0..3, D0..31, A2..23, JTAG Pins
*/
#ifndef CONFIG_PINSEL2_VALUE /* Can be selected from config file */
# define CONFIG_PINSEL2_VALUE 0x0e6149e4
#endif
/********************************************************************
@ -304,9 +322,9 @@
.macro configdac, base, tmp
#ifdef CONFIG_ADC_SETUP
ldr \base, =LPC214X_AD0CR
ldr \base, =LPC214X_AD0_BASE
ldr \tmp, =CONFIG_AD0CR_VALUE
str \tmp, [\base]
str \tmp, [\base, #LPC214X_AD_ADCR_OFFSET]
ldr \base,=LPC214X_PINSEL1
ldr \tmp, =CONFIG_PINSEL1_VALUE