diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c
index 46e847e54e..9bb6e99e8f 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/stm32/stm32f40xxx_rcc.c
  *
- *   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2011-2012, 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -51,6 +51,10 @@
 
 #define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
 
+/* Same for HSI */
+
+#define HSIRDY_TIMEOUT HSERDY_TIMEOUT
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -81,10 +85,10 @@ static inline void rcc_reset(void)
 
   putreg32(0x00000000, STM32_RCC_CFGR);
 
-  /* Reset HSEON, CSSON and PLLON bits */
+  /* Reset HSION, HSEON, CSSON and PLLON bits */
 
   regval  = getreg32(STM32_RCC_CR);
-  regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
+  regval &= ~(RCC_CR_HSION|RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
   putreg32(regval, STM32_RCC_CR);
 
   /* Reset PLLCFGR register to reset default */
@@ -597,6 +601,27 @@ static void stm32_stdclockconfig(void)
   uint32_t regval;
   volatile int32_t timeout;
 
+#ifdef STM32_BOARD_USEHSI
+  /* Enable Internal High-Speed Clock (HSI) */
+
+  regval  = getreg32(STM32_RCC_CR);
+  regval |= RCC_CR_HSION;           /* Enable HSI */
+  putreg32(regval, STM32_RCC_CR);
+
+  /* Wait until the HSI is ready (or until a timeout elapsed) */
+
+  for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--)
+  {
+    /* Check if the HSIRDY flag is the set in the CR */
+
+    if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0)
+      {
+        /* If so, then break-out with timeout > 0 */
+
+        break;
+      }
+  }
+#else /* if STM32_BOARD_USEHSE */
   /* Enable External High-Speed Clock (HSE) */
 
   regval  = getreg32(STM32_RCC_CR);
@@ -616,6 +641,7 @@ static void stm32_stdclockconfig(void)
         break;
       }
   }
+#endif
 
   /* Check for a timeout.  If this timeout occurs, then we are hosed.  We
    * have no real back-up plan, although the following logic makes it look
@@ -664,8 +690,13 @@ static void stm32_stdclockconfig(void)
 
       /* Set the PLL dividers and multiplers to configure the main PLL */
 
+#ifdef STM32_BOARD_USEHSI
+      regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
+                RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ);
+#else /* if STM32_BOARD_USEHSE */
       regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
                 RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ);
+#endif
       putreg32(regval, STM32_RCC_PLLCFG);
 
       /* Enable the main PLL */
@@ -696,7 +727,6 @@ static void stm32_stdclockconfig(void)
       while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0)
         {
         }
-
 #endif
 
       /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */