Add USB header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2696 42af7a65-404d-4744-a932-0658087f49c3
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arch/arm/src/lpc17xx/lpc17_usb.h
Executable file
487
arch/arm/src/lpc17xx/lpc17_usb.h
Executable file
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/************************************************************************************
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* arch/arm/src/lpc17xx/lpc17_usb.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H
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#define __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "lp17_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register offsets *****************************************************************/
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/* USB Host Controller **************************************************************/
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#define LPC17_USBHOST_HCIREV_OFFSET 0x0000 /* Version of HCI specification */
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#define LPC17_USBHOST_CTRL_OFFSET 0x0004 /* HC control */
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#define LPC17_USBHOST_CMDST_OFFSET 0x0008 /* HC command status */
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#define LPC17_USBHOST_INTST_OFFSET 0x000c /* HC interrupt status */
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#define LPC17_USBHOST_INTEN_OFFSET 0x0010 /* HC interrupt enable */
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#define LPC17_USBHOST_INTDIS_OFFSET 0x0014 /* HC interrupt disable */
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#define LPC17_USBHOST_HCCA_OFFSET 0x0018 /* HC communication area */
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#define LPC17_USBHOST_IIED_OFFSET 0x001c /* Current isoc or int endpoint desc */
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#define LPC17_USBHOST_CTRLHEADED_OFFSET 0x0020 /* First EP desc in the control list */
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#define LPC17_USBHOST_CTRLED_OFFSET 0x0024 /* Current EP desc in the control list */
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#define LPC17_USBHOST_BULKHEADED_OFFSET 0x0028 /* First EP desc in the bulk list */
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#define LPC17_USBHOST_BULKED_OFFSET 0x002c /* Current EP desc in the bulk list */
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#define LPC17_USBHOST_DONEHEAD_OFFSET 0x0030 /* Last transfer desc added to DONE queue */
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#define LPC17_USBHOST_FMINT_OFFSET 0x0034 /* Bit time interval that would not cause overrun */
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#define LPC17_USBHOST_FMREM_OFFSET 0x0038 /* Bit time remaining in current frame */
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#define LPC17_USBHOST_FMNO_OFFSET 0x003c /* Frame number counter */
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#define LPC17_USBHOST_PERSTART_OFFSET 0x0040 /* Time to start processing periodic list */
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#define LPC17_USBHOST_LSTHRES_OFFSET 0x0044 /* Commit to transfer threshold */
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#define LPC17_USBHOST_RHDESCA_OFFSET 0x0048 /* Describes root hub (part A) */
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#define LPC17_USBHOST_RHDESCB_OFFSET 0x004c /* Describes root hub (part B) */
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#define LPC17_USBHOST_RHSTATUS_OFFSET 0x0050 /* Root hub status */
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#define LPC17_USBHOST_RHPORTST0_OFFSET 0x0054 /* Root hub port status 1 */
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#define LPC17_USBHOST_RHPORTST1_OFFSET 0x0058 /* Root hub port status 2 */
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#define LPC17_USBHOST_MODID_OFFSET 0x00fc /* Module ID/Revision ID */
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/* USB OTG Controller ***************************************************************/
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/* OTG registers */
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#define LPC17_USBOTG_INTST_OFFSET 0x0100 /* OTG Interrupt Status */
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#define LPC17_USBOTG_INTEN_OFFSET 0x0104 /* OTG Interrupt Enable */
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#define LPC17_USBOTG_INTSET_OFFSET 0x0108 /* OTG Interrupt Set */
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#define LPC17_USBOTG_INTCLR_OFFSET 0x010c /* OTG Interrupt Clear */
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#define LPC17_USBOTG_STCTRL_OFFSET 0x0110 /* OTG Status and Control */
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#define LPC17_USBOTG_TMR_OFFSET 0x0114 /* OTG Timer */
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/* USB Device Controller ************************************************************/
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/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */
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#define LPC17_USBDEV_INTST_OFFSET 0x0200 /* USB Device Interrupt Status */
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#define LPC17_USBDEV_INTEN_OFFSET 0x0204 /* USB Device Interrupt Enable */
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#define LPC17_USBDEV_INTCLR_OFFSET 0x0208 /* USB Device Interrupt Clear */
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#define LPC17_USBDEV_INTSET_OFFSET 0x020c /* USB Device Interrupt Set */
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/* SIE Command registers */
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#define LPC17_USBDEV_CMDCODE_OFFSET 0x0210 /* USB Command Code */
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#define LPC17_USBDEV_CMDDATA_OFFSET 0x0214 /* USB Command Data */
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/* USB transfer registers */
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#define LPC17_USBDEV_RXDATA_OFFSET 0x0218 /* USB Receive Data */
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#define LPC17_USBDEV_RXPLEN_OFFSET 0x0220 /* USB Receive Packet Length */
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#define LPC17_USBDEV_TXDATA_OFFSET 0x021c /* USB Transmit Data */
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#define LPC17_USBDEV_TXPLEN_OFFSET 0x0224 /* USB Transmit Packet Length */
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#define LPC17_USBDEV_CTRL_OFFSET 0x0228 /* USB Control */
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/* More Device interrupt registers */
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#define LPC17_USBDEV_INTPRI_OFFSET 0x022c /* USB Device Interrupt Priority */
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/* Endpoint interrupt registers */
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#define LPC17_USBDEV_EPINTST_OFFSET 0x0230 /* USB Endpoint Interrupt Status */
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#define LPC17_USBDEV_EPINTEN_OFFSET 0x0234 /* USB Endpoint Interrupt Enable */
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#define LPC17_USBDEV_EPINTCLR_OFFSET 0x0238 /* USB Endpoint Interrupt Clear */
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#define LPC17_USBDEV_EPINTSET_OFFSET 0x023c /* USB Endpoint Interrupt Set */
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#define LPC17_USBDEV_EPINTPRI_OFFSET 0x0240 /* USB Endpoint Priority */
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/* Endpoint realization registers */
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#define LPC17_USBDEV_REEP_OFFSET 0x0244 /* USB Realize Endpoint */
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#define LPC17_USBDEV_EPIND_OFFSET 0x0248 /* USB Endpoint Index */
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#define LPC17_USBDEV_MAXPSIZE_OFFSET 0x024c /* USB MaxPacketSize */
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/* DMA registers */
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#define LPC17_USBDEV_DMARST_OFFSET 0x0250 /* USB DMA Request Status */
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#define LPC17_USBDEV_DMARCLR_OFFSET 0x0254 /* USB DMA Request Clear */
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#define LPC17_USBDEV_DMARSET_OFFSET 0x0258 /* USB DMA Request Set */
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#define LPC17_USBDEV_UDCAH_OFFSET 0x0280 /* USB UDCA Head */
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#define LPC17_USBDEV_EPDMAST_OFFSET 0x0284 /* USB Endpoint DMA Status */
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#define LPC17_USBDEV_EPDMAEN_OFFSET 0x0288 /* USB Endpoint DMA Enable */
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#define LPC17_USBDEV_EPDMADIS_OFFSET 0x028c /* USB Endpoint DMA Disable */
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#define LPC17_USBDEV_DMAINTST_OFFSET 0x0290 /* USB DMA Interrupt Status */
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#define LPC17_USBDEV_DMAINTEN_OFFSET 0x0294 /* USB DMA Interrupt Enable */
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#define LPC17_USBDEV_EOTINTST_OFFSET 0x02a0 /* USB End of Transfer Interrupt Status */
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#define LPC17_USBDEV_EOTINTCLR_OFFSET 0x02a4 /* USB End of Transfer Interrupt Clear */
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#define LPC17_USBDEV_EOTINTSET_OFFSET 0x02a8 /* USB End of Transfer Interrupt Set */
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#define LPC17_USBDEV_NDDRINTST_OFFSET 0x02ac /* USB New DD Request Interrupt Status */
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#define LPC17_USBDEV_NDDRINTCLR_OFFSET 0x02b0 /* USB New DD Request Interrupt Clear */
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#define LPC17_USBDEV_NDDRINTSET_OFFSET 0x02b4 /* USB New DD Request Interrupt Set */
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#define LPC17_USBDEV_SYSERRINTST_OFFSET 0x02b8 /* USB System Error Interrupt Status */
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#define LPC17_USBDEV_SYSERRINTCLR_OFFSET 0x02bc /* USB System Error Interrupt Clear */
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#define LPC17_USBDEV_SYSERRINTSET_OFFSET 0x02c0 /* USB System Error Interrupt Set */
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/* OTG I2C registers ****************************************************************/
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#define LPC17_OTGI2C_RX_OFFSET 0x0300 /* I2C Receive */
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#define LPC17_OTGI2C_TX_OFFSET 0x0300 /* I2C Transmit */
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#define LPC17_OTGI2C_STS_OFFSET 0x0304 /* I2C Status */
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#define LPC17_OTGI2C_CTL_OFFSET 0x0308 /* I2C Control */
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#define LPC17_OTGI2C_CLKHI_OFFSET 0x030c /* I2C Clock High */
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#define LPC17_OTGI2C_CLKLO_OFFSET 0x0310 /* I2C Clock Low */
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/* Clock control registers ***********************************************************/
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#define LPC17_USBOTG_CLKCTRL_OFFSET 0x0ff4 /* OTG clock controller */
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#define LPC17_USBOTG_CLKST_OFFSET 0x0ff8 /* OTG clock status */
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#define LPC17_USBDEV_CLKCTRL_OFFSET 0x0ff4 /* USB Clock Control */
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#define LPC17_USBDEV_CLKST_OFFSET 0x0ff8 /* USB Clock Status */
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/* Register addresses ***************************************************************/
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/* USB Host Controller **************************************************************/
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#define LPC17_USBHOST_HCIREV (LPC17_USB_BASE+LPC17_USBHOST_HCIREV_OFFSET)
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#define LPC17_USBHOST_CTRL (LPC17_USB_BASE+LPC17_USBHOST_CTRL_OFFSET)
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#define LPC17_USBHOST_CMDST (LPC17_USB_BASE+LPC17_USBHOST_CMDST_OFFSET)
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#define LPC17_USBHOST_INTST (LPC17_USB_BASE+LPC17_USBHOST_INTST_OFFSET)
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#define LPC17_USBHOST_INTEN (LPC17_USB_BASE+LPC17_USBHOST_INTEN_OFFSET)
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#define LPC17_USBHOST_INTDIS (LPC17_USB_BASE+LPC17_USBHOST_INTDIS_OFFSET)
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#define LPC17_USBHOST_HCCA (LPC17_USB_BASE+LPC17_USBHOST_HCCA_OFFSET)
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#define LPC17_USBHOST_IIED (LPC17_USB_BASE+LPC17_USBHOST_IIED_OFFSET)
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#define LPC17_USBHOST_CTRLHEADED (LPC17_USB_BASE+LPC17_USBHOST_CTRLHEADED_OFFSET)
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#define LPC17_USBHOST_CTRLED (LPC17_USB_BASE+LPC17_USBHOST_CTRLED_OFFSET)
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#define LPC17_USBHOST_BULKHEADED (LPC17_USB_BASE+LPC17_USBHOST_BULKHEADED_OFFSET)
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#define LPC17_USBHOST_BULKED (LPC17_USB_BASE+LPC17_USBHOST_BULKED_OFFSET)
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#define LPC17_USBHOST_DONEHEAD (LPC17_USB_BASE+LPC17_USBHOST_DONEHEAD_OFFSET)
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#define LPC17_USBHOST_FMINT (LPC17_USB_BASE+LPC17_USBHOST_FMINT_OFFSET)
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#define LPC17_USBHOST_FMREM (LPC17_USB_BASE+LPC17_USBHOST_FMREM_OFFSET)
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#define LPC17_USBHOST_FMNO (LPC17_USB_BASE+LPC17_USBHOST_FMNO_OFFSET)
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#define LPC17_USBHOST_PERSTART (LPC17_USB_BASE+LPC17_USBHOST_PERSTART_OFFSET)
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#define LPC17_USBHOST_LSTHRES (LPC17_USB_BASE+LPC17_USBHOST_LSTHRES_OFFSET)
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#define LPC17_USBHOST_RHDESCA (LPC17_USB_BASE+LPC17_USBHOST_RHDESCA_OFFSET)
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#define LPC17_USBHOST_RHDESCB (LPC17_USB_BASE+LPC17_USBHOST_RHDESCB_OFFSET)
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#define LPC17_USBHOST_RHSTATUS (LPC17_USB_BASE+LPC17_USBHOST_RHSTATUS_OFFSET)
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#define LPC17_USBHOST_RHPORTST0 (LPC17_USB_BASE+LPC17_USBHOST_RHPORTST0_OFFSET)
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#define LPC17_USBHOST_RHPORTST1 (LPC17_USB_BASE+LPC17_USBHOST_RHPORTST1_OFFSET)
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#define LPC17_USBHOST_MODID (LPC17_USB_BASE+LPC17_USBHOST_MODID_OFFSET)
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/* USB OTG Controller ***************************************************************/
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/* OTG registers */
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#define LPC17_USBOTG_INTST (LPC17_USB_BASE+LPC17_USBOTG_INTST_OFFSET)
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#define LPC17_USBOTG_INTEN (LPC17_USB_BASE+LPC17_USBOTG_INTEN_OFFSET)
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#define LPC17_USBOTG_INTSET (LPC17_USB_BASE+LPC17_USBOTG_INTSET_OFFSET)
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#define LPC17_USBOTG_INTCLR (LPC17_USB_BASE+LPC17_USBOTG_INTCLR_OFFSET)
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#define LPC17_USBOTG_STCTRL (LPC17_USB_BASE+LPC17_USBOTG_STCTRL_OFFSET)
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#define LPC17_USBOTG_TMR (LPC17_USB_BASE+LPC17_USBOTG_TMR_OFFSET)
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/* USB Device Controller ************************************************************/
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/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */
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#define LPC17_USBDEV_INTST (LPC17_USB_BASE+LPC17_USBDEV_INTST_OFFSET)
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#define LPC17_USBDEV_INTEN (LPC17_USB_BASE+LPC17_USBDEV_INTEN_OFFSET)
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#define LPC17_USBDEV_INTCLR (LPC17_USB_BASE+LPC17_USBDEV_INTCLR_OFFSET)
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#define LPC17_USBDEV_INTSET (LPC17_USB_BASE+LPC17_USBDEV_INTSET_OFFSET)
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/* SIE Command registers */
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#define LPC17_USBDEV_CMDCODE (LPC17_USB_BASE+LPC17_USBDEV_CMDCODE_OFFSET)
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#define LPC17_USBDEV_CMDDATA (LPC17_USB_BASE+LPC17_USBDEV_CMDDATA_OFFSET)
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/* USB transfer registers */
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#define LPC17_USBDEV_RXDATA (LPC17_USB_BASE+LPC17_USBDEV_RXDATA_OFFSET)
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#define LPC17_USBDEV_RXPLEN (LPC17_USB_BASE+LPC17_USBDEV_RXPLEN_OFFSET)
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#define LPC17_USBDEV_TXDATA (LPC17_USB_BASE+LPC17_USBDEV_TXDATA_OFFSET)
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#define LPC17_USBDEV_TXPLEN (LPC17_USB_BASE+LPC17_USBDEV_TXPLEN_OFFSET)
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#define LPC17_USBDEV_CTRL (LPC17_USB_BASE+LPC17_USBDEV_CTRL_OFFSET)
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/* More Device interrupt registers */
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#define LPC17_USBDEV_INTPRI (LPC17_USB_BASE+LPC17_USBDEV_INTPRI_OFFSET)
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/* Endpoint interrupt registers */
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#define LPC17_USBDEV_EPINTST (LPC17_USB_BASE+LPC17_USBDEV_EPINTST_OFFSET)
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#define LPC17_USBDEV_EPINTEN (LPC17_USB_BASE+LPC17_USBDEV_EPINTEN_OFFSET)
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#define LPC17_USBDEV_EPINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EPINTCLR_OFFSET)
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#define LPC17_USBDEV_EPINTSET (LPC17_USB_BASE+LPC17_USBDEV_EPINTSET_OFFSET)
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#define LPC17_USBDEV_EPINTPRI (LPC17_USB_BASE+LPC17_USBDEV_EPINTPRI_OFFSET)
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/* Endpoint realization registers */
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#define LPC17_USBDEV_REEP (LPC17_USB_BASE+LPC17_USBDEV_REEP_OFFSET)
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#define LPC17_USBDEV_EPIND (LPC17_USB_BASE+LPC17_USBDEV_EPIND_OFFSET)
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#define LPC17_USBDEV_MAXPSIZE (LPC17_USB_BASE+LPC17_USBDEV_MAXPSIZE_OFFSET)
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/* DMA registers */
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#define LPC17_USBDEV_DMARST (LPC17_USB_BASE+LPC17_USBDEV_DMARST_OFFSET)
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#define LPC17_USBDEV_DMARCLR (LPC17_USB_BASE+LPC17_USBDEV_DMARCLR_OFFSET)
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#define LPC17_USBDEV_DMARSET (LPC17_USB_BASE+LPC17_USBDEV_DMARSET_OFFSET)
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#define LPC17_USBDEV_UDCAH (LPC17_USB_BASE+LPC17_USBDEV_UDCAH_OFFSET)
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#define LPC17_USBDEV_EPDMAST (LPC17_USB_BASE+LPC17_USBDEV_EPDMAST_OFFSET)
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#define LPC17_USBDEV_EPDMAEN (LPC17_USB_BASE+LPC17_USBDEV_EPDMAEN_OFFSET)
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#define LPC17_USBDEV_EPDMADIS (LPC17_USB_BASE+LPC17_USBDEV_EPDMADIS_OFFSET)
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#define LPC17_USBDEV_DMAINTST (LPC17_USB_BASE+LPC17_USBDEV_DMAINTST_OFFSET)
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#define LPC17_USBDEV_DMAINTEN (LPC17_USB_BASE+LPC17_USBDEV_DMAINTEN_OFFSET)
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#define LPC17_USBDEV_EOTINTST (LPC17_USB_BASE+LPC17_USBDEV_EOTINTST_OFFSET)
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#define LPC17_USBDEV_EOTINTCLR (LPC17_USB_BASE+LPC17_USBDEV_EOTINTCLR_OFFSET)
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#define LPC17_USBDEV_EOTINTSET (LPC17_USB_BASE+LPC17_USBDEV_EOTINTSET_OFFSET)
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#define LPC17_USBDEV_NDDRINTST (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTST_OFFSET)
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#define LPC17_USBDEV_NDDRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTCLR_OFFSET)
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#define LPC17_USBDEV_NDDRINTSET (LPC17_USB_BASE+LPC17_USBDEV_NDDRINTSET_OFFSET)
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#define LPC17_USBDEV_SYSERRINTST (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTST_OFFSET)
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#define LPC17_USBDEV_SYSERRINTCLR (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTCLR_OFFSET)
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#define LPC17_USBDEV_SYSERRINTSET (LPC17_USB_BASE+LPC17_USBDEV_SYSERRINTSET_OFFSET)
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/* OTG I2C registers ****************************************************************/
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#define LPC17_OTGI2C_RX (LPC17_USB_BASE+LPC17_OTGI2C_RX_OFFSET)
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#define LPC17_OTGI2C_TX (LPC17_USB_BASE+LPC17_OTGI2C_TX_OFFSET)
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#define LPC17_OTGI2C_STS (LPC17_USB_BASE+LPC17_OTGI2C_STS_OFFSET)
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#define LPC17_OTGI2C_CTL (LPC17_USB_BASE+LPC17_OTGI2C_CTL_OFFSET)
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#define LPC17_OTGI2C_CLKHI (LPC17_USB_BASE+LPC17_OTGI2C_CLKHI_OFFSET)
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#define LPC17_OTGI2C_CLKLO (LPC17_USB_BASE+LPC17_OTGI2C_CLKLO_OFFSET)
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/* Clock control registers ***********************************************************/
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#define LPC17_USBOTG_CLKCTRL (LPC17_USB_BASE+LPC17_USBOTG_CLKCTRL_OFFSET)
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#define LPC17_USBOTG_CLKST (LPC17_USB_BASE+LPC17_USBOTG_CLKST_OFFSET)
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#define LPC17_USBDEV_CLKCTRL (LPC17_USB_BASE+LPC17_USBDEV_CLKCTRL_OFFSET)
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#define LPC17_USBDEV_CLKST (LPC17_USB_BASE+LPC17_USBDEV_CLKST_OFFSET)
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/* Register bit definitions *********************************************************/
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/* USB Host Controller **************************************************************/
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/* Version of HCI specification */
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#define USBHOST_HCIREV_
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/* HC control */
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#define USBHOST_CTRL_
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/* HC command status */
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#define USBHOST_CMDST_
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/* HC interrupt status */
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#define USBHOST_INTST_
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/* HC interrupt enable */
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#define USBHOST_INTEN_
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/* HC interrupt disable */
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#define USBHOST_INTDIS_
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/* HC communication area */
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#define USBHOST_HCCA_
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/* Current isoc or int endpoint desc */
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#define USBHOST_IIED_
|
||||
/* First EP desc in the control list */
|
||||
#define USBHOST_CTRLHEADED_
|
||||
/* Current EP desc in the control list */
|
||||
#define USBHOST_CTRLED_
|
||||
/* First EP desc in the bulk list */
|
||||
#define USBHOST_BULKHEADED_
|
||||
/* Current EP desc in the bulk list */
|
||||
#define USBHOST_BULKED_
|
||||
/* Last transfer desc added to DONE queue */
|
||||
#define USBHOST_DONEHEAD_
|
||||
/* Bit time interval that would not cause overrun */
|
||||
#define USBHOST_FMINT_
|
||||
/* Bit time remaining in current frame */
|
||||
#define USBHOST_FMREM_
|
||||
/* Frame number counter */
|
||||
#define USBHOST_FMNO_
|
||||
/* Time to start processing periodic list */
|
||||
#define USBHOST_PERSTART_
|
||||
/* Commit to transfer threshold */
|
||||
#define USBHOST_LSTHRES_
|
||||
/* Describes root hub (part A) */
|
||||
#define USBHOST_RHDESCA_
|
||||
/* Describes root hub (part B) */
|
||||
#define USBHOST_RHDESCB_
|
||||
/* Root hub status */
|
||||
#define USBHOST_RHSTATUS_
|
||||
/* Root hub port status 1 */
|
||||
#define USBHOST_RHPORTST0_
|
||||
/* Root hub port status 2 */
|
||||
#define USBHOST_RHPORTST1_
|
||||
/* Module ID/Revision ID */
|
||||
#define USBHOST_MODID_
|
||||
|
||||
/* USB OTG Controller ***************************************************************/
|
||||
/* OTG registers */
|
||||
|
||||
/* OTG Interrupt Status */
|
||||
#define USBOTG_INTST_
|
||||
/* OTG Interrupt Enable */
|
||||
#define USBOTG_INTEN_
|
||||
/* OTG Interrupt Set */
|
||||
#define USBOTG_INTSET_
|
||||
/* OTG Interrupt Clear */
|
||||
#define USBOTG_INTCLR_
|
||||
/* OTG Status and Control */
|
||||
#define USBOTG_STCTRL_
|
||||
/* OTG Timer */
|
||||
#define USBOTG_TMR_
|
||||
|
||||
/* USB Device Controller ************************************************************/
|
||||
/* Device interrupt registers. See also SYSCON_USBINTST in lpc17_syscon.h */
|
||||
|
||||
/* USB Device Interrupt Status */
|
||||
#define USBDEV_INTST_
|
||||
/* USB Device Interrupt Enable */
|
||||
#define USBDEV_INTEN_
|
||||
/* USB Device Interrupt Clear */
|
||||
#define USBDEV_INTCLR_
|
||||
/* USB Device Interrupt Set */
|
||||
#define USBDEV_INTSET_
|
||||
|
||||
/* SIE Command registers */
|
||||
|
||||
/* USB Command Code */
|
||||
#define USBDEV_CMDCODE_
|
||||
/* USB Command Data */
|
||||
#define USBDEV_CMDDATA_
|
||||
|
||||
/* USB transfer registers */
|
||||
|
||||
/* USB Receive Data */
|
||||
#define USBDEV_RXDATA_
|
||||
/* USB Receive Packet Length */
|
||||
#define USBDEV_RXPLEN_
|
||||
/* USB Transmit Data */
|
||||
#define USBDEV_TXDATA_
|
||||
/* USB Transmit Packet Length */
|
||||
#define USBDEV_TXPLEN_
|
||||
/* USB Control */
|
||||
#define USBDEV_CTRL_
|
||||
|
||||
/* More Device interrupt registers */
|
||||
|
||||
/* USB Device Interrupt Priority */
|
||||
#define USBDEV_INTPRI_
|
||||
|
||||
/* Endpoint interrupt registers */
|
||||
|
||||
/* USB Endpoint Interrupt Status */
|
||||
#define USBDEV_EPINTST_
|
||||
/* USB Endpoint Interrupt Enable */
|
||||
#define USBDEV_EPINTEN_
|
||||
/* USB Endpoint Interrupt Clear */
|
||||
#define USBDEV_EPINTCLR_
|
||||
/* USB Endpoint Interrupt Set */
|
||||
#define USBDEV_EPINTSET_
|
||||
/* USB Endpoint Priority */
|
||||
#define USBDEV_EPINTPRI_
|
||||
|
||||
/* Endpoint realization registers */
|
||||
|
||||
/* USB Realize Endpoint */
|
||||
#define USBDEV_REEP_
|
||||
/* USB Endpoint Index */
|
||||
#define USBDEV_EPIND_
|
||||
/* USB MaxPacketSize */
|
||||
#define USBDEV_MAXPSIZE_
|
||||
|
||||
/* DMA registers */
|
||||
|
||||
/* USB DMA Request Status */
|
||||
#define USBDEV_DMARST_
|
||||
/* USB DMA Request Clear */
|
||||
#define USBDEV_DMARCLR_
|
||||
/* USB DMA Request Set */
|
||||
#define USBDEV_DMARSET_
|
||||
/* USB UDCA Head */
|
||||
#define USBDEV_UDCAH_
|
||||
/* USB Endpoint DMA Status */
|
||||
#define USBDEV_EPDMAST_
|
||||
/* USB Endpoint DMA Enable */
|
||||
#define USBDEV_EPDMAEN_
|
||||
/* USB Endpoint DMA Disable */
|
||||
#define USBDEV_EPDMADIS_
|
||||
/* USB DMA Interrupt Status */
|
||||
#define USBDEV_DMAINTST_
|
||||
/* USB DMA Interrupt Enable */
|
||||
#define USBDEV_DMAINTEN_
|
||||
/* USB End of Transfer Interrupt Status */
|
||||
#define USBDEV_EOTINTST_
|
||||
/* USB End of Transfer Interrupt Clear */
|
||||
#define USBDEV_EOTINTCLR_
|
||||
/* USB End of Transfer Interrupt Set */
|
||||
#define USBDEV_EOTINTSET_
|
||||
/* USB New DD Request Interrupt Status */
|
||||
#define USBDEV_NDDRINTST_
|
||||
/* USB New DD Request Interrupt Clear */
|
||||
#define USBDEV_NDDRINTCLR_
|
||||
/* USB New DD Request Interrupt Set */
|
||||
#define USBDEV_NDDRINTSET_
|
||||
/* USB System Error Interrupt Status */
|
||||
#define USBDEV_SYSERRINTST_
|
||||
/* USB System Error Interrupt Clear */
|
||||
#define USBDEV_SYSERRINTCLR_
|
||||
/* USB System Error Interrupt Set */
|
||||
#define USBDEV_SYSERRINTSET_
|
||||
|
||||
/* OTG I2C registers ****************************************************************/
|
||||
|
||||
/* I2C Receive */
|
||||
#define OTGI2C_RX_
|
||||
/* I2C Transmit */
|
||||
#define OTGI2C_TX_
|
||||
/* I2C Status */
|
||||
#define OTGI2C_STS_
|
||||
/* I2C Control */
|
||||
#define OTGI2C_CTL_
|
||||
/* I2C Clock High */
|
||||
#define OTGI2C_CLKHI_
|
||||
/* I2C Clock Low */
|
||||
#define OTGI2C_CLKLO_
|
||||
|
||||
/* Clock control registers ***********************************************************/
|
||||
|
||||
/* OTG clock controller */
|
||||
#define USBOTG_CLKCTRL_
|
||||
/* OTG clock status */
|
||||
#define USBOTG_CLKST_
|
||||
|
||||
/* USB Clock Control */
|
||||
#define USBDEV_CLKCTRL_
|
||||
/* USB Clock Status */
|
||||
#define USBDEV_CLKST_
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_USB_H */
|
||||
Loading…
Reference in New Issue
Block a user