Add support for multiplexed SDIO pins from Uros
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3898 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
parent
d4fd560ea0
commit
ad0721c9d7
@ -59,6 +59,22 @@
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#define HSERDY_TIMEOUT 256
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* Activity reference count, showing inactivity after start-up.
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* Device drivers increment this count using rcclock() and rccunlock()
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*
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* If this value goes beyond the range [0, MAX_RCCs] indicates
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* reference count leakage (asymetric number of locks vs. unlocks) and
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* system enters permanent active state.
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*/
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#ifdef CONFIG_STM32_RCCLOCK
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static int stm32_rcclock_count = 0;
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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@ -98,7 +114,6 @@ static inline void rcc_reset(void)
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putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */
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}
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static inline void rcc_enableahb(void)
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{
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uint32_t regval;
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@ -140,7 +155,6 @@ static inline void rcc_enableahb(void)
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putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */
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}
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static inline void rcc_enableapb1(void)
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{
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uint32_t regval;
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@ -292,7 +306,6 @@ static inline void rcc_enableapb1(void)
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putreg32(regval, STM32_RCC_APB1ENR);
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}
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static inline void rcc_enableapb2(void)
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{
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uint32_t regval;
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@ -374,14 +387,14 @@ static inline void rcc_enableapb2(void)
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putreg32(regval, STM32_RCC_APB2ENR);
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}
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#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
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/** Called to change to new clock based on settings in board.h
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/* Called to change to new clock based on settings in board.h
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*
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* NOTE: This logic would need to be extended if you need to select low-
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* power clocking modes!
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**/
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* NOTE: This logic would need to be extended if you need to select low-
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* power clocking modes!
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*/
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static inline void stm32_stdclockconfig(void)
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{
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uint32_t regval;
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@ -469,7 +482,6 @@ static inline void stm32_stdclockconfig(void)
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}
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -501,22 +513,66 @@ void stm32_clockconfig(void)
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rcc_enableapb1();
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}
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/**
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/*
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* \todo Check for LSE good timeout and return with -1,
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* possible ISR optimization? or at least ISR should be cough in case of failure
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*/
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void stm32_rcc_enablelse(void)
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{
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/* Enable LSE */
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modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
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/* Enable LSE */
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/* We could wait for ISR here ... */
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while( !(getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) ) up_waste();
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modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
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/* We could wait for ISR here ... */
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while( !(getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) ) up_waste();
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/* Select LSE as RTC Clock Source */
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modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
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/* Select LSE as RTC Clock Source */
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modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
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/* Enable Clock */
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modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
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/* Enable Clock */
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modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
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}
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#ifdef CONFIG_STM32_RCCLOCK
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uint32_t stm32_rcclock(uint8_t domain_id)
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{
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// THINK:
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// maybe just shift domain_id into 32-bit or 64-bit register
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// and if there value of this var != 0, we are active...
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// increment some variable, so it is possible to test leakage
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// multiple locks or multiple unlocks
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if (stm32_rcclock_count >= 0)
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{
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stm32_rcclock_count++;
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if (stm32_rcclock_count > 64)
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{
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stm32_rcclock_count = -1; /* capture error */
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}
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}
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return 0;
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}
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uint32_t stm32_rccunlock(uint8_t domain_id)
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{
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if (stm32_rcclock_count > -1)
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{
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stm32_rcclock_count--;
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}
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return 0;
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}
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uint32_t stm32_setrccoptions(uint8_t domain_id, uint32_t options)
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{
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}
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int stm32_getrccactivity(void)
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{
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return stm32_rcclock_count;
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}
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#endif
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@ -72,22 +72,21 @@ extern "C" {
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extern uint32_t stm32_vectors[]; /* See stm32_vectors.S */
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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/** Called to change to new clock based on settings in board.h
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/* Called to change to new clock based on settings in board.h
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*
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* NOTE: This logic needs to be extended so that we can selected low-power
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* clocking modes as well!
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**/
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* NOTE: This logic needs to be extended so that we can selected low-power
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* clocking modes as well!
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*/
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EXTERN void stm32_clockconfig(void);
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/** Enable LSE Clock
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**/
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EXTERN void stm32_rcc_enablelse(void);
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/* Enable LSE Clock */
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EXTERN void stm32_rcc_enablelse(void);
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#undef EXTERN
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#if defined(__cplusplus)
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@ -317,6 +317,12 @@ static int stm32_interrupt(int irq, void *context);
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/* SDIO interface methods ***************************************************/
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/* Mutual exclusion */
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#ifdef CONFIG_SDIO_MUXBUS
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static int stm32_lock(FAR struct sdio_dev_s *dev, bool lock);
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#endif
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/* Initialization/setup */
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static void stm32_reset(FAR struct sdio_dev_s *dev);
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@ -380,6 +386,9 @@ struct stm32_dev_s g_sdiodev =
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{
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.dev =
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{
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#ifdef CONFIG_SDIO_MUXBUS
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.lock = stm32_lock,
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#endif
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.reset = stm32_reset,
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.status = stm32_status,
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.widebus = stm32_widebus,
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@ -1312,6 +1321,35 @@ static int stm32_interrupt(int irq, void *context)
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/****************************************************************************
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* SDIO Interface Methods
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_lock
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*
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* Description:
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* Locks the bus. Function calls low-level multiplexed bus routines to
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* resolve bus requests and acknowledgment issues.
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*
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* Input Parameters:
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* dev - An instance of the SDIO device interface
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* lock - TRUE to lock, FALSE to unlock.
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*
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* Returned Value:
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* OK on success; a negated errno on failure
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*
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****************************************************************************/
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#ifdef CONFIG_SDIO_MUXBUS
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static int stm32_lock(FAR struct sdio_dev_s *dev, bool lock)
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{
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/* Single SDIO instance so there is only one possibility. The multiplex
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* bus is part of board support package.
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*/
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stm32_muxbus_sdio_lock(lock);
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return OK;
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}
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#endif
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/****************************************************************************
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* Name: stm32_reset
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*
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@ -2574,8 +2612,12 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
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/* Configure GPIOs for 4-bit, wide-bus operation (the chip is capable of
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* 8-bit wide bus operation but D4-D7 are not configured).
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*
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* If bus is multiplexed then there is a custom bus configuration utility
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* in the scope of the board support package.
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*/
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#ifndef CONFIG_SDIO_MUXBUS
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stm32_configgpio(GPIO_SDIO_D0);
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#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
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stm32_configgpio(GPIO_SDIO_D1);
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@ -2584,6 +2626,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
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#endif
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stm32_configgpio(GPIO_SDIO_CK);
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stm32_configgpio(GPIO_SDIO_CMD);
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#endif
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/* Reset the card and assure that it is in the initial, unconfigured
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* state.
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