Fix compilation error with debug on
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2164 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
2dc7bcfb5e
commit
ad3c39383e
@ -38,7 +38,7 @@
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <assert.h>
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@ -46,102 +46,102 @@
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "chip.h"
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#include "stm32_fsmc.h"
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#include "up_arch.h"
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#include "chip.h"
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#include "stm32_fsmc.h"
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#include "stm32_gpio.h"
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#include "stm32_internal.h"
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#include "stm3210e-internal.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#ifndef CONFIG_STM32_FSMC
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# warning "FSMC is not enabled"
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#endif
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#if STM32_NGPIO_PORTS < 6
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# error "Required GPIO ports not enabled"
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#endif
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************************************************************************************/
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#ifndef CONFIG_STM32_FSMC
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# warning "FSMC is not enabled"
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#endif
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#if STM32_NGPIO_PORTS < 6
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# error "Required GPIO ports not enabled"
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#endif
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/************************************************************************************
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* Private Data
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************************************************************************************/
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/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and 16-bit
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* accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of SRAM,
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* respectively.
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*
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* Pin Usage (per schematic)
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* FLASH SRAM NAND
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* D[0..15] [0..15] [0..15] [0..7]
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* A[0..23] [0..22] [0..18] [16,17]
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* PSMC_NE3 PG10 OUT ~CE --- ---
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* PSMC_NBL0 PE0 OUT ~BLE --- ---
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* PSMC_NBL1 PE1 OUT ~BHE --- ---
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* PSMC_NE2 PG9 OUT --- ~E ---
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* PSMC_NWE PD5 OUT ~WE ~W ~W
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* PSMC_NOE PD4 OUT ~OE ~G ~R
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* PSMC_NWAIT PD6 IN --- R~B ---
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* PSMC_INT2 PG6* IN --- --- R~B
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*
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* *JP7 will switch to PD6
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*/
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/* It would be much more efficient to brute force these all into the
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* the appropriate registers. Just a little tricky.
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*/
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/* GPIO configurations common to SRAM and NOR Flash */
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static const uint16 g_commonconfig[] =
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{
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/* A0... A18 */
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GPIO_NPS_A0, GPIO_NPS_A1, GPIO_NPS_A2, GPIO_NPS_A3,
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GPIO_NPS_A4, GPIO_NPS_A5, GPIO_NPS_A6, GPIO_NPS_A7,
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GPIO_NPS_A8, GPIO_NPS_A9, GPIO_NPS_A10, GPIO_NPS_A11,
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GPIO_NPS_A12, GPIO_NPS_A13, GPIO_NPS_A14, GPIO_NPS_A15,
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GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18,
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/* D0... D15 */
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GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3,
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GPIO_NPS_D4, GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7,
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GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11,
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GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15,
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/* NOE, NWE, NE3 */
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GPIO_NPS_NOE, GPIO_NPS_NWE
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};
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#define NCOMMON_CONFIG (sizeof(g_commonconfig)/sizeof(uint16))
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/* GPIO configurations unique to SRAM */
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static const uint16 g_sramconfig[] =
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{
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/* NE3, NBL0, NBL1, */
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GPIO_NPS_NE3, GPIO_NPS_NBL0, GPIO_NPS_NBL1
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};
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/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and 16-bit
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* accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of SRAM,
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* respectively.
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*
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* Pin Usage (per schematic)
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* FLASH SRAM NAND
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* D[0..15] [0..15] [0..15] [0..7]
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* A[0..23] [0..22] [0..18] [16,17]
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* PSMC_NE3 PG10 OUT ~CE --- ---
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* PSMC_NBL0 PE0 OUT ~BLE --- ---
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* PSMC_NBL1 PE1 OUT ~BHE --- ---
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* PSMC_NE2 PG9 OUT --- ~E ---
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* PSMC_NWE PD5 OUT ~WE ~W ~W
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* PSMC_NOE PD4 OUT ~OE ~G ~R
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* PSMC_NWAIT PD6 IN --- R~B ---
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* PSMC_INT2 PG6* IN --- --- R~B
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*
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* *JP7 will switch to PD6
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*/
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/* It would be much more efficient to brute force these all into the
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* the appropriate registers. Just a little tricky.
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*/
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/* GPIO configurations common to SRAM and NOR Flash */
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static const uint16 g_commonconfig[] =
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{
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/* A0... A18 */
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GPIO_NPS_A0, GPIO_NPS_A1, GPIO_NPS_A2, GPIO_NPS_A3,
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GPIO_NPS_A4, GPIO_NPS_A5, GPIO_NPS_A6, GPIO_NPS_A7,
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GPIO_NPS_A8, GPIO_NPS_A9, GPIO_NPS_A10, GPIO_NPS_A11,
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GPIO_NPS_A12, GPIO_NPS_A13, GPIO_NPS_A14, GPIO_NPS_A15,
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GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18,
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/* D0... D15 */
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GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3,
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GPIO_NPS_D4, GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7,
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GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11,
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GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15,
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/* NOE, NWE, NE3 */
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GPIO_NPS_NOE, GPIO_NPS_NWE
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};
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#define NCOMMON_CONFIG (sizeof(g_commonconfig)/sizeof(uint16))
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/* GPIO configurations unique to SRAM */
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static const uint16 g_sramconfig[] =
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{
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/* NE3, NBL0, NBL1, */
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GPIO_NPS_NE3, GPIO_NPS_NBL0, GPIO_NPS_NBL1
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};
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#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint16))
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/* GPIO configurations unique to NOR Flash */
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static const uint16 g_norconfig[] =
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{
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/* A19... A22 */
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GPIO_NPS_A19, GPIO_NPS_A20, GPIO_NPS_A21, GPIO_NPS_A22,
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/* NE2 */
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GPIO_NPS_NE2
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};
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/* GPIO configurations unique to NOR Flash */
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static const uint16 g_norconfig[] =
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{
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/* A19... A22 */
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GPIO_NPS_A19, GPIO_NPS_A20, GPIO_NPS_A21, GPIO_NPS_A22,
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/* NE2 */
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GPIO_NPS_NE2
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};
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#define NNOR_CONFIG (sizeof(g_norconfig)/sizeof(uint16))
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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@ -153,19 +153,19 @@ static const uint16 g_norconfig[] =
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* Initialize GPIOs for NOR or SRAM
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*
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************************************************************************************/
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static void stm32_extmemgpios(const uint16 *gpios, int ngpios)
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{
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int i;
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/* Configure GPIOs */
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for (i = 0; i < ngpios; i++)
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{
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stm32_configgpio(gpios[i]);
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}
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static void stm32_extmemgpios(const uint16 *gpios, int ngpios)
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{
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int i;
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/* Configure GPIOs */
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for (i = 0; i < ngpios; i++)
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{
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stm32_configgpio(gpios[i]);
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}
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}
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/************************************************************************************
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* Name: stm32_savegpios
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*
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@ -173,10 +173,10 @@ static void stm32_extmemgpios(const uint16 *gpios, int ngpios)
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* Save current GPIOs that will used by external memory configurations
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*
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************************************************************************************/
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static void stm32_savegpios(struct extmem_save_s *save)
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{
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DEBUGASSERT(save != NULL);
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static void stm32_savegpios(struct extmem_save_s *save)
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{
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DEBUGASSERT(save != NULL);
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save->gpiod_crl = getreg32(STM32_GPIOE_CRL);
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save->gpiod_crh = getreg32(STM32_GPIOE_CRH);
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save->gpioe_crl = getreg32(STM32_GPIOD_CRL);
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@ -184,9 +184,9 @@ static void stm32_savegpios(struct extmem_save_s *save)
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save->gpiof_crl = getreg32(STM32_GPIOF_CRL);
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save->gpiof_crh = getreg32(STM32_GPIOF_CRH);
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save->gpiog_crl = getreg32(STM32_GPIOG_CRL);
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save->gpiog_crh = getreg32(STM32_GPIOG_CRH);
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save->gpiog_crh = getreg32(STM32_GPIOG_CRH);
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}
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/************************************************************************************
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* Name: stm32_restoregpios
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*
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@ -194,10 +194,10 @@ static void stm32_savegpios(struct extmem_save_s *save)
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* Restore GPIOs that were used by external memory configurations
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*
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************************************************************************************/
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static void stm32_restoregpios(struct extmem_save_s *restore)
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{
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DEBUGASSERT(save != NULL);
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static void stm32_restoregpios(struct extmem_save_s *restore)
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{
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DEBUGASSERT(restore != NULL);
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putreg32(restore->gpiod_crl, STM32_GPIOE_CRL);
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putreg32(restore->gpiod_crh, STM32_GPIOE_CRH);
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putreg32(restore->gpioe_crl, STM32_GPIOD_CRL);
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@ -205,47 +205,47 @@ static void stm32_restoregpios(struct extmem_save_s *restore)
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putreg32(restore->gpiof_crl, STM32_GPIOF_CRL);
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putreg32(restore->gpiof_crh, STM32_GPIOF_CRH);
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putreg32(restore->gpiog_crl, STM32_GPIOG_CRL);
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putreg32(restore->gpiog_crh, STM32_GPIOG_CRH);
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putreg32(restore->gpiog_crh, STM32_GPIOG_CRH);
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}
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/************************************************************************************
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* Name: stm32_enableclocks
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*
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* Description:
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* enable clocking to the FSMC module
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*
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************************************************************************************/
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static void stm32_enableclocks(void)
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{
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uint32 regval;
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************************************************************************************/
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static void stm32_enableclocks(void)
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{
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uint32 regval;
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/* Enable AHB clocking to the FSMC */
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regval = getreg32( STM32_RCC_AHBENR);
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regval |= RCC_AHBENR_FSMCEN;
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putreg32(regval, STM32_RCC_AHBENR);
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}
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/* Enable AHB clocking to the FSMC */
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regval = getreg32( STM32_RCC_AHBENR);
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regval |= RCC_AHBENR_FSMCEN;
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putreg32(regval, STM32_RCC_AHBENR);
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}
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/************************************************************************************
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* Name: stm32_disableclocks
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*
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* Description:
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* enable clocking to the FSMC module
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*
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************************************************************************************/
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static void stm32_disableclocks(void)
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{
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uint32 regval;
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************************************************************************************/
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static void stm32_disableclocks(void)
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{
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uint32 regval;
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/* Enable AHB clocking to the FSMC */
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regval = getreg32( STM32_RCC_AHBENR);
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regval &= ~RCC_AHBENR_FSMCEN;
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putreg32(regval, STM32_RCC_AHBENR);
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}
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/* Enable AHB clocking to the FSMC */
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regval = getreg32( STM32_RCC_AHBENR);
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regval &= ~RCC_AHBENR_FSMCEN;
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putreg32(regval, STM32_RCC_AHBENR);
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}
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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@ -257,36 +257,36 @@ static void stm32_disableclocks(void)
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* Initialize to access NOR flash
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*
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************************************************************************************/
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void stm32_selectnor(struct extmem_save_s *save)
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{
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/* Save current GPIO state */
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stm32_savegpios(save);
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/* Configure new GPIO state */
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stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG);
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stm32_extmemgpios(g_sramconfig, NNOR_CONFIG);
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/* Enable AHB clocking to the FSMC */
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stm32_enableclocks();
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/* Bank1 NOR/SRAM control register configuration */
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putreg32(FSMC_BCR2_MTYP1|FSMC_BCR2_FACCEN|FSMC_BCR2_MWID0|FSMC_BCR2_WREN, STM32_FSMC_BCR2);
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/* Bank1 NOR/SRAM timing register configuration */
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putreg32(FSMC_BTR2_ADDSET1|FSMC_BTR2_DATAST0|FSMC_BTR2_DATAST2| FSMC_BTR2_DATLAT0, STM32_FSMC_BTR2);
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putreg32(0x0fffffff, STM32_FSMC_BCR3);
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/* Enable the bank */
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putreg32(FSMC_BCR3_MBKEN|FSMC_BCR2_MTYP1|FSMC_BCR2_FACCEN|FSMC_BCR2_MWID0|FSMC_BCR2_WREN, STM32_FSMC_BCR2);
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}
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{
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/* Save current GPIO state */
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stm32_savegpios(save);
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/* Configure new GPIO state */
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stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG);
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stm32_extmemgpios(g_sramconfig, NNOR_CONFIG);
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/* Enable AHB clocking to the FSMC */
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stm32_enableclocks();
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/* Bank1 NOR/SRAM control register configuration */
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putreg32(FSMC_BCR2_MTYP1|FSMC_BCR2_FACCEN|FSMC_BCR2_MWID0|FSMC_BCR2_WREN, STM32_FSMC_BCR2);
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/* Bank1 NOR/SRAM timing register configuration */
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putreg32(FSMC_BTR2_ADDSET1|FSMC_BTR2_DATAST0|FSMC_BTR2_DATAST2| FSMC_BTR2_DATLAT0, STM32_FSMC_BTR2);
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putreg32(0x0fffffff, STM32_FSMC_BCR3);
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/* Enable the bank */
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putreg32(FSMC_BCR3_MBKEN|FSMC_BCR2_MTYP1|FSMC_BCR2_FACCEN|FSMC_BCR2_MWID0|FSMC_BCR2_WREN, STM32_FSMC_BCR2);
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}
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/************************************************************************************
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* Name: stm32_deselectnor
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*
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@ -294,26 +294,26 @@ void stm32_selectnor(struct extmem_save_s *save)
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* Disable NOR FLASH
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*
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************************************************************************************/
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void stm32_deselectnor(struct extmem_save_s *restore)
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{
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/* Restore registers to their power up settings */
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putreg32(0x000030d2, STM32_FSMC_BCR2);
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/* Bank1 NOR/SRAM timing register configuration */
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putreg32(0x0fffffff, STM32_FSMC_BTR2);
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/* Disable AHB clocking to the FSMC */
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stm32_disableclocks();
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/* Restore GPIOs */
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stm32_restoregpios(restore);
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}
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{
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/* Restore registers to their power up settings */
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putreg32(0x000030d2, STM32_FSMC_BCR2);
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/* Bank1 NOR/SRAM timing register configuration */
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putreg32(0x0fffffff, STM32_FSMC_BTR2);
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/* Disable AHB clocking to the FSMC */
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stm32_disableclocks();
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/* Restore GPIOs */
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stm32_restoregpios(restore);
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}
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/************************************************************************************
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* Name: stm32_selectsram
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*
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@ -321,35 +321,35 @@ void stm32_deselectnor(struct extmem_save_s *restore)
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* Initialize to access external SRAM
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*
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************************************************************************************/
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void stm32_selectsram(struct extmem_save_s *save)
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{
|
||||
/* Save current GPIO state */
|
||||
|
||||
stm32_savegpios(save);
|
||||
|
||||
/* Configure new GPIO state */
|
||||
|
||||
stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG);
|
||||
stm32_extmemgpios(g_norconfig, NSRAM_CONFIG);
|
||||
|
||||
/* Enable AHB clocking to the FSMC */
|
||||
|
||||
stm32_enableclocks();
|
||||
|
||||
/* Bank1 NOR/SRAM control register configuration */
|
||||
|
||||
putreg32(FSMC_BCR3_MWID0|FSMC_BCR3_WREN, STM32_FSMC_BCR3);
|
||||
|
||||
/* Bank1 NOR/SRAM timing register configuration */
|
||||
|
||||
putreg32(FSMC_BCR3_WAITPOL, STM32_FSMC_BTR3);
|
||||
putreg32(0xffffffff, STM32_FSMC_BCR3);
|
||||
|
||||
/* Enable the bank */
|
||||
|
||||
putreg32(FSMC_BCR3_MBKEN|FSMC_BCR3_MWID0|FSMC_BCR3_WREN, STM32_FSMC_BCR3);
|
||||
}
|
||||
{
|
||||
/* Save current GPIO state */
|
||||
|
||||
stm32_savegpios(save);
|
||||
|
||||
/* Configure new GPIO state */
|
||||
|
||||
stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG);
|
||||
stm32_extmemgpios(g_norconfig, NSRAM_CONFIG);
|
||||
|
||||
/* Enable AHB clocking to the FSMC */
|
||||
|
||||
stm32_enableclocks();
|
||||
|
||||
/* Bank1 NOR/SRAM control register configuration */
|
||||
|
||||
putreg32(FSMC_BCR3_MWID0|FSMC_BCR3_WREN, STM32_FSMC_BCR3);
|
||||
|
||||
/* Bank1 NOR/SRAM timing register configuration */
|
||||
|
||||
putreg32(FSMC_BCR3_WAITPOL, STM32_FSMC_BTR3);
|
||||
putreg32(0xffffffff, STM32_FSMC_BCR3);
|
||||
|
||||
/* Enable the bank */
|
||||
|
||||
putreg32(FSMC_BCR3_MBKEN|FSMC_BCR3_MWID0|FSMC_BCR3_WREN, STM32_FSMC_BCR3);
|
||||
}
|
||||
/************************************************************************************
|
||||
* Name: stm32_deselectsram
|
||||
*
|
||||
@ -357,24 +357,24 @@ void stm32_selectsram(struct extmem_save_s *save)
|
||||
* Disable NOR FLASH
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
|
||||
void stm32_deselectsram(struct extmem_save_s *restore)
|
||||
{
|
||||
/* Restore registers to their power up settings */
|
||||
|
||||
putreg32(0x000030d2, STM32_FSMC_BCR3);
|
||||
|
||||
/* Bank1 NOR/SRAM timing register configuration */
|
||||
|
||||
putreg32(0x0fffffff, STM32_FSMC_BTR3);
|
||||
|
||||
/* Disable AHB clocking to the FSMC */
|
||||
|
||||
stm32_disableclocks();
|
||||
|
||||
/* Restore GPIOs */
|
||||
|
||||
stm32_restoregpios(restore);
|
||||
}
|
||||
|
||||
|
||||
{
|
||||
/* Restore registers to their power up settings */
|
||||
|
||||
putreg32(0x000030d2, STM32_FSMC_BCR3);
|
||||
|
||||
/* Bank1 NOR/SRAM timing register configuration */
|
||||
|
||||
putreg32(0x0fffffff, STM32_FSMC_BTR3);
|
||||
|
||||
/* Disable AHB clocking to the FSMC */
|
||||
|
||||
stm32_disableclocks();
|
||||
|
||||
/* Restore GPIOs */
|
||||
|
||||
stm32_restoregpios(restore);
|
||||
}
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user